0001 /*
0002 * ARM Ltd. Juno Platform
0003 *
0004 * Copyright (c) 2013-2014 ARM Ltd.
0005 *
0006 * This file is licensed under a dual GPLv2 or BSD license.
0007 */
0008
0009 /dts-v1/;
0010
0011 #include <dt-bindings/interrupt-controller/arm-gic.h>
0012 #include <dt-bindings/arm/coresight-cti-dt.h>
0013 #include "juno-base.dtsi"
0014
0015 / {
0016 model = "ARM Juno development board (r0)";
0017 compatible = "arm,juno", "arm,vexpress";
0018 interrupt-parent = <&gic>;
0019 #address-cells = <2>;
0020 #size-cells = <2>;
0021
0022 aliases {
0023 serial0 = &soc_uart0;
0024 };
0025
0026 chosen {
0027 stdout-path = "serial0:115200n8";
0028 };
0029
0030 psci {
0031 compatible = "arm,psci-0.2";
0032 method = "smc";
0033 };
0034
0035 cpus {
0036 #address-cells = <2>;
0037 #size-cells = <0>;
0038
0039 cpu-map {
0040 cluster0 {
0041 core0 {
0042 cpu = <&A57_0>;
0043 };
0044 core1 {
0045 cpu = <&A57_1>;
0046 };
0047 };
0048
0049 cluster1 {
0050 core0 {
0051 cpu = <&A53_0>;
0052 };
0053 core1 {
0054 cpu = <&A53_1>;
0055 };
0056 core2 {
0057 cpu = <&A53_2>;
0058 };
0059 core3 {
0060 cpu = <&A53_3>;
0061 };
0062 };
0063 };
0064
0065 idle-states {
0066 entry-method = "psci";
0067
0068 CPU_SLEEP_0: cpu-sleep-0 {
0069 compatible = "arm,idle-state";
0070 arm,psci-suspend-param = <0x0010000>;
0071 local-timer-stop;
0072 entry-latency-us = <300>;
0073 exit-latency-us = <1200>;
0074 min-residency-us = <2000>;
0075 };
0076
0077 CLUSTER_SLEEP_0: cluster-sleep-0 {
0078 compatible = "arm,idle-state";
0079 arm,psci-suspend-param = <0x1010000>;
0080 local-timer-stop;
0081 entry-latency-us = <400>;
0082 exit-latency-us = <1200>;
0083 min-residency-us = <2500>;
0084 };
0085 };
0086
0087 A57_0: cpu@0 {
0088 compatible = "arm,cortex-a57";
0089 reg = <0x0 0x0>;
0090 device_type = "cpu";
0091 enable-method = "psci";
0092 i-cache-size = <0xc000>;
0093 i-cache-line-size = <64>;
0094 i-cache-sets = <256>;
0095 d-cache-size = <0x8000>;
0096 d-cache-line-size = <64>;
0097 d-cache-sets = <256>;
0098 next-level-cache = <&A57_L2>;
0099 clocks = <&scpi_dvfs 0>;
0100 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0101 capacity-dmips-mhz = <1024>;
0102 dynamic-power-coefficient = <530>;
0103 };
0104
0105 A57_1: cpu@1 {
0106 compatible = "arm,cortex-a57";
0107 reg = <0x0 0x1>;
0108 device_type = "cpu";
0109 enable-method = "psci";
0110 i-cache-size = <0xc000>;
0111 i-cache-line-size = <64>;
0112 i-cache-sets = <256>;
0113 d-cache-size = <0x8000>;
0114 d-cache-line-size = <64>;
0115 d-cache-sets = <256>;
0116 next-level-cache = <&A57_L2>;
0117 clocks = <&scpi_dvfs 0>;
0118 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0119 capacity-dmips-mhz = <1024>;
0120 dynamic-power-coefficient = <530>;
0121 };
0122
0123 A53_0: cpu@100 {
0124 compatible = "arm,cortex-a53";
0125 reg = <0x0 0x100>;
0126 device_type = "cpu";
0127 enable-method = "psci";
0128 i-cache-size = <0x8000>;
0129 i-cache-line-size = <64>;
0130 i-cache-sets = <256>;
0131 d-cache-size = <0x8000>;
0132 d-cache-line-size = <64>;
0133 d-cache-sets = <128>;
0134 next-level-cache = <&A53_L2>;
0135 clocks = <&scpi_dvfs 1>;
0136 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0137 capacity-dmips-mhz = <578>;
0138 dynamic-power-coefficient = <140>;
0139 };
0140
0141 A53_1: cpu@101 {
0142 compatible = "arm,cortex-a53";
0143 reg = <0x0 0x101>;
0144 device_type = "cpu";
0145 enable-method = "psci";
0146 i-cache-size = <0x8000>;
0147 i-cache-line-size = <64>;
0148 i-cache-sets = <256>;
0149 d-cache-size = <0x8000>;
0150 d-cache-line-size = <64>;
0151 d-cache-sets = <128>;
0152 next-level-cache = <&A53_L2>;
0153 clocks = <&scpi_dvfs 1>;
0154 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0155 capacity-dmips-mhz = <578>;
0156 dynamic-power-coefficient = <140>;
0157 };
0158
0159 A53_2: cpu@102 {
0160 compatible = "arm,cortex-a53";
0161 reg = <0x0 0x102>;
0162 device_type = "cpu";
0163 enable-method = "psci";
0164 i-cache-size = <0x8000>;
0165 i-cache-line-size = <64>;
0166 i-cache-sets = <256>;
0167 d-cache-size = <0x8000>;
0168 d-cache-line-size = <64>;
0169 d-cache-sets = <128>;
0170 next-level-cache = <&A53_L2>;
0171 clocks = <&scpi_dvfs 1>;
0172 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0173 capacity-dmips-mhz = <578>;
0174 dynamic-power-coefficient = <140>;
0175 };
0176
0177 A53_3: cpu@103 {
0178 compatible = "arm,cortex-a53";
0179 reg = <0x0 0x103>;
0180 device_type = "cpu";
0181 enable-method = "psci";
0182 i-cache-size = <0x8000>;
0183 i-cache-line-size = <64>;
0184 i-cache-sets = <256>;
0185 d-cache-size = <0x8000>;
0186 d-cache-line-size = <64>;
0187 d-cache-sets = <128>;
0188 next-level-cache = <&A53_L2>;
0189 clocks = <&scpi_dvfs 1>;
0190 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0191 capacity-dmips-mhz = <578>;
0192 dynamic-power-coefficient = <140>;
0193 };
0194
0195 A57_L2: l2-cache0 {
0196 compatible = "cache";
0197 cache-size = <0x200000>;
0198 cache-line-size = <64>;
0199 cache-sets = <2048>;
0200 cache-level = <2>;
0201 };
0202
0203 A53_L2: l2-cache1 {
0204 compatible = "cache";
0205 cache-size = <0x100000>;
0206 cache-line-size = <64>;
0207 cache-sets = <1024>;
0208 cache-level = <2>;
0209 };
0210 };
0211
0212 pmu-a57 {
0213 compatible = "arm,cortex-a57-pmu";
0214 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
0215 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
0216 interrupt-affinity = <&A57_0>,
0217 <&A57_1>;
0218 };
0219
0220 pmu-a53 {
0221 compatible = "arm,cortex-a53-pmu";
0222 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0223 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
0224 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
0225 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0226 interrupt-affinity = <&A53_0>,
0227 <&A53_1>,
0228 <&A53_2>,
0229 <&A53_3>;
0230 };
0231 };
0232
0233 &etm0 {
0234 cpu = <&A57_0>;
0235 };
0236
0237 &etm1 {
0238 cpu = <&A57_1>;
0239 };
0240
0241 &etm2 {
0242 cpu = <&A53_0>;
0243 };
0244
0245 &etm3 {
0246 cpu = <&A53_1>;
0247 };
0248
0249 &etm4 {
0250 cpu = <&A53_2>;
0251 };
0252
0253 &etm5 {
0254 cpu = <&A53_3>;
0255 };
0256
0257 &etf0_out_port {
0258 remote-endpoint = <&replicator_in_port0>;
0259 };
0260
0261 &replicator_in_port0 {
0262 remote-endpoint = <&etf0_out_port>;
0263 };
0264
0265 &stm_out_port {
0266 remote-endpoint = <&main_funnel_in_port2>;
0267 };
0268
0269 &main_funnel_in_ports {
0270 port@2 {
0271 reg = <2>;
0272 main_funnel_in_port2: endpoint {
0273 remote-endpoint = <&stm_out_port>;
0274 };
0275 };
0276 };
0277
0278 &cpu_debug0 {
0279 cpu = <&A57_0>;
0280 };
0281
0282 &cpu_debug1 {
0283 cpu = <&A57_1>;
0284 };
0285
0286 &cpu_debug2 {
0287 cpu = <&A53_0>;
0288 };
0289
0290 &cpu_debug3 {
0291 cpu = <&A53_1>;
0292 };
0293
0294 &cpu_debug4 {
0295 cpu = <&A53_2>;
0296 };
0297
0298 &cpu_debug5 {
0299 cpu = <&A53_3>;
0300 };
0301
0302 &cti0 {
0303 cpu = <&A57_0>;
0304 };
0305
0306 &cti1 {
0307 cpu = <&A57_1>;
0308 };
0309
0310 &cti2 {
0311 cpu = <&A53_0>;
0312 };
0313
0314 &cti3 {
0315 cpu = <&A53_1>;
0316 };
0317
0318 &cti4 {
0319 cpu = <&A53_2>;
0320 };
0321
0322 &cti5 {
0323 cpu = <&A53_3>;
0324 };
