0001 /*
0002 * ARM Ltd. Juno Platform
0003 *
0004 * Copyright (c) 2015 ARM Ltd.
0005 *
0006 * This file is licensed under a dual GPLv2 or BSD license.
0007 */
0008
0009 /dts-v1/;
0010
0011 #include <dt-bindings/interrupt-controller/arm-gic.h>
0012 #include <dt-bindings/arm/coresight-cti-dt.h>
0013 #include "juno-base.dtsi"
0014 #include "juno-cs-r1r2.dtsi"
0015
0016 / {
0017 model = "ARM Juno development board (r2)";
0018 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
0019 interrupt-parent = <&gic>;
0020 #address-cells = <2>;
0021 #size-cells = <2>;
0022
0023 aliases {
0024 serial0 = &soc_uart0;
0025 };
0026
0027 chosen {
0028 stdout-path = "serial0:115200n8";
0029 };
0030
0031 psci {
0032 compatible = "arm,psci-0.2";
0033 method = "smc";
0034 };
0035
0036 cpus {
0037 #address-cells = <2>;
0038 #size-cells = <0>;
0039
0040 cpu-map {
0041 cluster0 {
0042 core0 {
0043 cpu = <&A72_0>;
0044 };
0045 core1 {
0046 cpu = <&A72_1>;
0047 };
0048 };
0049
0050 cluster1 {
0051 core0 {
0052 cpu = <&A53_0>;
0053 };
0054 core1 {
0055 cpu = <&A53_1>;
0056 };
0057 core2 {
0058 cpu = <&A53_2>;
0059 };
0060 core3 {
0061 cpu = <&A53_3>;
0062 };
0063 };
0064 };
0065
0066 idle-states {
0067 entry-method = "psci";
0068
0069 CPU_SLEEP_0: cpu-sleep-0 {
0070 compatible = "arm,idle-state";
0071 arm,psci-suspend-param = <0x0010000>;
0072 local-timer-stop;
0073 entry-latency-us = <300>;
0074 exit-latency-us = <1200>;
0075 min-residency-us = <2000>;
0076 };
0077
0078 CLUSTER_SLEEP_0: cluster-sleep-0 {
0079 compatible = "arm,idle-state";
0080 arm,psci-suspend-param = <0x1010000>;
0081 local-timer-stop;
0082 entry-latency-us = <400>;
0083 exit-latency-us = <1200>;
0084 min-residency-us = <2500>;
0085 };
0086 };
0087
0088 A72_0: cpu@0 {
0089 compatible = "arm,cortex-a72";
0090 reg = <0x0 0x0>;
0091 device_type = "cpu";
0092 enable-method = "psci";
0093 i-cache-size = <0xc000>;
0094 i-cache-line-size = <64>;
0095 i-cache-sets = <256>;
0096 d-cache-size = <0x8000>;
0097 d-cache-line-size = <64>;
0098 d-cache-sets = <256>;
0099 next-level-cache = <&A72_L2>;
0100 clocks = <&scpi_dvfs 0>;
0101 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0102 capacity-dmips-mhz = <1024>;
0103 dynamic-power-coefficient = <450>;
0104 };
0105
0106 A72_1: cpu@1 {
0107 compatible = "arm,cortex-a72";
0108 reg = <0x0 0x1>;
0109 device_type = "cpu";
0110 enable-method = "psci";
0111 i-cache-size = <0xc000>;
0112 i-cache-line-size = <64>;
0113 i-cache-sets = <256>;
0114 d-cache-size = <0x8000>;
0115 d-cache-line-size = <64>;
0116 d-cache-sets = <256>;
0117 next-level-cache = <&A72_L2>;
0118 clocks = <&scpi_dvfs 0>;
0119 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0120 capacity-dmips-mhz = <1024>;
0121 dynamic-power-coefficient = <450>;
0122 };
0123
0124 A53_0: cpu@100 {
0125 compatible = "arm,cortex-a53";
0126 reg = <0x0 0x100>;
0127 device_type = "cpu";
0128 enable-method = "psci";
0129 i-cache-size = <0x8000>;
0130 i-cache-line-size = <64>;
0131 i-cache-sets = <256>;
0132 d-cache-size = <0x8000>;
0133 d-cache-line-size = <64>;
0134 d-cache-sets = <128>;
0135 next-level-cache = <&A53_L2>;
0136 clocks = <&scpi_dvfs 1>;
0137 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0138 capacity-dmips-mhz = <485>;
0139 dynamic-power-coefficient = <140>;
0140 };
0141
0142 A53_1: cpu@101 {
0143 compatible = "arm,cortex-a53";
0144 reg = <0x0 0x101>;
0145 device_type = "cpu";
0146 enable-method = "psci";
0147 i-cache-size = <0x8000>;
0148 i-cache-line-size = <64>;
0149 i-cache-sets = <256>;
0150 d-cache-size = <0x8000>;
0151 d-cache-line-size = <64>;
0152 d-cache-sets = <128>;
0153 next-level-cache = <&A53_L2>;
0154 clocks = <&scpi_dvfs 1>;
0155 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0156 capacity-dmips-mhz = <485>;
0157 dynamic-power-coefficient = <140>;
0158 };
0159
0160 A53_2: cpu@102 {
0161 compatible = "arm,cortex-a53";
0162 reg = <0x0 0x102>;
0163 device_type = "cpu";
0164 enable-method = "psci";
0165 i-cache-size = <0x8000>;
0166 i-cache-line-size = <64>;
0167 i-cache-sets = <256>;
0168 d-cache-size = <0x8000>;
0169 d-cache-line-size = <64>;
0170 d-cache-sets = <128>;
0171 next-level-cache = <&A53_L2>;
0172 clocks = <&scpi_dvfs 1>;
0173 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0174 capacity-dmips-mhz = <485>;
0175 dynamic-power-coefficient = <140>;
0176 };
0177
0178 A53_3: cpu@103 {
0179 compatible = "arm,cortex-a53";
0180 reg = <0x0 0x103>;
0181 device_type = "cpu";
0182 enable-method = "psci";
0183 i-cache-size = <0x8000>;
0184 i-cache-line-size = <64>;
0185 i-cache-sets = <256>;
0186 d-cache-size = <0x8000>;
0187 d-cache-line-size = <64>;
0188 d-cache-sets = <128>;
0189 next-level-cache = <&A53_L2>;
0190 clocks = <&scpi_dvfs 1>;
0191 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0192 capacity-dmips-mhz = <485>;
0193 dynamic-power-coefficient = <140>;
0194 };
0195
0196 A72_L2: l2-cache0 {
0197 compatible = "cache";
0198 cache-size = <0x200000>;
0199 cache-line-size = <64>;
0200 cache-sets = <2048>;
0201 cache-level = <2>;
0202 };
0203
0204 A53_L2: l2-cache1 {
0205 compatible = "cache";
0206 cache-size = <0x100000>;
0207 cache-line-size = <64>;
0208 cache-sets = <1024>;
0209 cache-level = <2>;
0210 };
0211 };
0212
0213 pmu-a72 {
0214 compatible = "arm,cortex-a72-pmu";
0215 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
0216 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
0217 interrupt-affinity = <&A72_0>,
0218 <&A72_1>;
0219 };
0220
0221 pmu-a53 {
0222 compatible = "arm,cortex-a53-pmu";
0223 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0224 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
0225 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
0226 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0227 interrupt-affinity = <&A53_0>,
0228 <&A53_1>,
0229 <&A53_2>,
0230 <&A53_3>;
0231 };
0232 };
0233
0234 &memtimer {
0235 status = "okay";
0236 };
0237
0238 &pcie_ctlr {
0239 status = "okay";
0240 };
0241
0242 &smmu_pcie {
0243 status = "okay";
0244 };
0245
0246 &etm0 {
0247 cpu = <&A72_0>;
0248 };
0249
0250 &etm1 {
0251 cpu = <&A72_1>;
0252 };
0253
0254 &etm2 {
0255 cpu = <&A53_0>;
0256 };
0257
0258 &etm3 {
0259 cpu = <&A53_1>;
0260 };
0261
0262 &etm4 {
0263 cpu = <&A53_2>;
0264 };
0265
0266 &etm5 {
0267 cpu = <&A53_3>;
0268 };
0269
0270 &big_cluster_thermal_zone {
0271 status = "okay";
0272 };
0273
0274 &little_cluster_thermal_zone {
0275 status = "okay";
0276 };
0277
0278 &gpu0_thermal_zone {
0279 status = "okay";
0280 };
0281
0282 &gpu1_thermal_zone {
0283 status = "okay";
0284 };
0285
0286 &etf0_out_port {
0287 remote-endpoint = <&csys2_funnel_in_port0>;
0288 };
0289
0290 &replicator_in_port0 {
0291 remote-endpoint = <&csys2_funnel_out_port>;
0292 };
0293
0294 &csys1_funnel_in_port0 {
0295 remote-endpoint = <&stm_out_port>;
0296 };
0297
0298 &stm_out_port {
0299 remote-endpoint = <&csys1_funnel_in_port0>;
0300 };
0301
0302 &cpu_debug0 {
0303 cpu = <&A72_0>;
0304 };
0305
0306 &cpu_debug1 {
0307 cpu = <&A72_1>;
0308 };
0309
0310 &cpu_debug2 {
0311 cpu = <&A53_0>;
0312 };
0313
0314 &cpu_debug3 {
0315 cpu = <&A53_1>;
0316 };
0317
0318 &cpu_debug4 {
0319 cpu = <&A53_2>;
0320 };
0321
0322 &cpu_debug5 {
0323 cpu = <&A53_3>;
0324 };
0325
0326 &cti0 {
0327 cpu = <&A72_0>;
0328 };
0329
0330 &cti1 {
0331 cpu = <&A72_1>;
0332 };
0333
0334 &cti2 {
0335 cpu = <&A53_0>;
0336 };
0337
0338 &cti3 {
0339 cpu = <&A53_1>;
0340 };
0341
0342 &cti4 {
0343 cpu = <&A53_2>;
0344 };
0345
0346 &cti5 {
0347 cpu = <&A53_3>;
0348 };
