0001 /*
0002 * ARM Ltd. Juno Platform
0003 *
0004 * Copyright (c) 2015 ARM Ltd.
0005 *
0006 * This file is licensed under a dual GPLv2 or BSD license.
0007 */
0008
0009 /dts-v1/;
0010
0011 #include <dt-bindings/interrupt-controller/arm-gic.h>
0012 #include <dt-bindings/arm/coresight-cti-dt.h>
0013 #include "juno-base.dtsi"
0014 #include "juno-cs-r1r2.dtsi"
0015
0016 / {
0017 model = "ARM Juno development board (r1)";
0018 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
0019 interrupt-parent = <&gic>;
0020 #address-cells = <2>;
0021 #size-cells = <2>;
0022
0023 aliases {
0024 serial0 = &soc_uart0;
0025 };
0026
0027 chosen {
0028 stdout-path = "serial0:115200n8";
0029 };
0030
0031 psci {
0032 compatible = "arm,psci-0.2";
0033 method = "smc";
0034 };
0035
0036 cpus {
0037 #address-cells = <2>;
0038 #size-cells = <0>;
0039
0040 cpu-map {
0041 cluster0 {
0042 core0 {
0043 cpu = <&A57_0>;
0044 };
0045 core1 {
0046 cpu = <&A57_1>;
0047 };
0048 };
0049
0050 cluster1 {
0051 core0 {
0052 cpu = <&A53_0>;
0053 };
0054 core1 {
0055 cpu = <&A53_1>;
0056 };
0057 core2 {
0058 cpu = <&A53_2>;
0059 };
0060 core3 {
0061 cpu = <&A53_3>;
0062 };
0063 };
0064 };
0065
0066 idle-states {
0067 entry-method = "psci";
0068
0069 CPU_SLEEP_0: cpu-sleep-0 {
0070 compatible = "arm,idle-state";
0071 arm,psci-suspend-param = <0x0010000>;
0072 local-timer-stop;
0073 entry-latency-us = <300>;
0074 exit-latency-us = <1200>;
0075 min-residency-us = <2000>;
0076 };
0077
0078 CLUSTER_SLEEP_0: cluster-sleep-0 {
0079 compatible = "arm,idle-state";
0080 arm,psci-suspend-param = <0x1010000>;
0081 local-timer-stop;
0082 entry-latency-us = <400>;
0083 exit-latency-us = <1200>;
0084 min-residency-us = <2500>;
0085 };
0086 };
0087
0088 A57_0: cpu@0 {
0089 compatible = "arm,cortex-a57";
0090 reg = <0x0 0x0>;
0091 device_type = "cpu";
0092 enable-method = "psci";
0093 i-cache-size = <0xc000>;
0094 i-cache-line-size = <64>;
0095 i-cache-sets = <256>;
0096 d-cache-size = <0x8000>;
0097 d-cache-line-size = <64>;
0098 d-cache-sets = <256>;
0099 next-level-cache = <&A57_L2>;
0100 clocks = <&scpi_dvfs 0>;
0101 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0102 capacity-dmips-mhz = <1024>;
0103 };
0104
0105 A57_1: cpu@1 {
0106 compatible = "arm,cortex-a57";
0107 reg = <0x0 0x1>;
0108 device_type = "cpu";
0109 enable-method = "psci";
0110 i-cache-size = <0xc000>;
0111 i-cache-line-size = <64>;
0112 i-cache-sets = <256>;
0113 d-cache-size = <0x8000>;
0114 d-cache-line-size = <64>;
0115 d-cache-sets = <256>;
0116 next-level-cache = <&A57_L2>;
0117 clocks = <&scpi_dvfs 0>;
0118 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0119 capacity-dmips-mhz = <1024>;
0120 };
0121
0122 A53_0: cpu@100 {
0123 compatible = "arm,cortex-a53";
0124 reg = <0x0 0x100>;
0125 device_type = "cpu";
0126 enable-method = "psci";
0127 i-cache-size = <0x8000>;
0128 i-cache-line-size = <64>;
0129 i-cache-sets = <256>;
0130 d-cache-size = <0x8000>;
0131 d-cache-line-size = <64>;
0132 d-cache-sets = <128>;
0133 next-level-cache = <&A53_L2>;
0134 clocks = <&scpi_dvfs 1>;
0135 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0136 capacity-dmips-mhz = <578>;
0137 };
0138
0139 A53_1: cpu@101 {
0140 compatible = "arm,cortex-a53";
0141 reg = <0x0 0x101>;
0142 device_type = "cpu";
0143 enable-method = "psci";
0144 i-cache-size = <0x8000>;
0145 i-cache-line-size = <64>;
0146 i-cache-sets = <256>;
0147 d-cache-size = <0x8000>;
0148 d-cache-line-size = <64>;
0149 d-cache-sets = <128>;
0150 next-level-cache = <&A53_L2>;
0151 clocks = <&scpi_dvfs 1>;
0152 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0153 capacity-dmips-mhz = <578>;
0154 };
0155
0156 A53_2: cpu@102 {
0157 compatible = "arm,cortex-a53";
0158 reg = <0x0 0x102>;
0159 device_type = "cpu";
0160 enable-method = "psci";
0161 i-cache-size = <0x8000>;
0162 i-cache-line-size = <64>;
0163 i-cache-sets = <256>;
0164 d-cache-size = <0x8000>;
0165 d-cache-line-size = <64>;
0166 d-cache-sets = <128>;
0167 next-level-cache = <&A53_L2>;
0168 clocks = <&scpi_dvfs 1>;
0169 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0170 capacity-dmips-mhz = <578>;
0171 };
0172
0173 A53_3: cpu@103 {
0174 compatible = "arm,cortex-a53";
0175 reg = <0x0 0x103>;
0176 device_type = "cpu";
0177 enable-method = "psci";
0178 i-cache-size = <0x8000>;
0179 i-cache-line-size = <64>;
0180 i-cache-sets = <256>;
0181 d-cache-size = <0x8000>;
0182 d-cache-line-size = <64>;
0183 d-cache-sets = <128>;
0184 next-level-cache = <&A53_L2>;
0185 clocks = <&scpi_dvfs 1>;
0186 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0187 capacity-dmips-mhz = <578>;
0188 };
0189
0190 A57_L2: l2-cache0 {
0191 compatible = "cache";
0192 cache-size = <0x200000>;
0193 cache-line-size = <64>;
0194 cache-sets = <2048>;
0195 cache-level = <2>;
0196 };
0197
0198 A53_L2: l2-cache1 {
0199 compatible = "cache";
0200 cache-size = <0x100000>;
0201 cache-line-size = <64>;
0202 cache-sets = <1024>;
0203 cache-level = <2>;
0204 };
0205 };
0206
0207 pmu-a57 {
0208 compatible = "arm,cortex-a57-pmu";
0209 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
0210 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
0211 interrupt-affinity = <&A57_0>,
0212 <&A57_1>;
0213 };
0214
0215 pmu-a53 {
0216 compatible = "arm,cortex-a53-pmu";
0217 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0218 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
0219 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
0220 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0221 interrupt-affinity = <&A53_0>,
0222 <&A53_1>,
0223 <&A53_2>,
0224 <&A53_3>;
0225 };
0226 };
0227
0228 &memtimer {
0229 status = "okay";
0230 };
0231
0232 &pcie_ctlr {
0233 status = "okay";
0234 };
0235
0236 &smmu_pcie {
0237 status = "okay";
0238 };
0239
0240 &etm0 {
0241 cpu = <&A57_0>;
0242 };
0243
0244 &etm1 {
0245 cpu = <&A57_1>;
0246 };
0247
0248 &etm2 {
0249 cpu = <&A53_0>;
0250 };
0251
0252 &etm3 {
0253 cpu = <&A53_1>;
0254 };
0255
0256 &etm4 {
0257 cpu = <&A53_2>;
0258 };
0259
0260 &etm5 {
0261 cpu = <&A53_3>;
0262 };
0263
0264 &big_cluster_thermal_zone {
0265 status = "okay";
0266 };
0267
0268 &little_cluster_thermal_zone {
0269 status = "okay";
0270 };
0271
0272 &gpu0_thermal_zone {
0273 status = "okay";
0274 };
0275
0276 &gpu1_thermal_zone {
0277 status = "okay";
0278 };
0279
0280 &etf0_out_port {
0281 remote-endpoint = <&csys2_funnel_in_port0>;
0282 };
0283
0284 &replicator_in_port0 {
0285 remote-endpoint = <&csys2_funnel_out_port>;
0286 };
0287
0288 &csys1_funnel_in_port0 {
0289 remote-endpoint = <&stm_out_port>;
0290 };
0291
0292 &stm_out_port {
0293 remote-endpoint = <&csys1_funnel_in_port0>;
0294 };
0295
0296 &cpu_debug0 {
0297 cpu = <&A57_0>;
0298 };
0299
0300 &cpu_debug1 {
0301 cpu = <&A57_1>;
0302 };
0303
0304 &cpu_debug2 {
0305 cpu = <&A53_0>;
0306 };
0307
0308 &cpu_debug3 {
0309 cpu = <&A53_1>;
0310 };
0311
0312 &cpu_debug4 {
0313 cpu = <&A53_2>;
0314 };
0315
0316 &cpu_debug5 {
0317 cpu = <&A53_3>;
0318 };
0319
0320 &cti0 {
0321 cpu = <&A57_0>;
0322 };
0323
0324 &cti1 {
0325 cpu = <&A57_1>;
0326 };
0327
0328 &cti2 {
0329 cpu = <&A53_0>;
0330 };
0331
0332 &cti3 {
0333 cpu = <&A53_1>;
0334 };
0335
0336 &cti4 {
0337 cpu = <&A53_2>;
0338 };
0339
0340 &cti5 {
0341 cpu = <&A53_3>;
0342 };
