0001 // SPDX-License-Identifier: GPL-2.0
0002 #include "juno-clocks.dtsi"
0003 #include "juno-motherboard.dtsi"
0004
0005 / {
0006 /*
0007 * Devices shared by all Juno boards
0008 */
0009
0010 memtimer: timer@2a810000 {
0011 compatible = "arm,armv7-timer-mem";
0012 reg = <0x0 0x2a810000 0x0 0x10000>;
0013 clock-frequency = <50000000>;
0014 #address-cells = <1>;
0015 #size-cells = <1>;
0016 ranges = <0 0x0 0x2a820000 0x20000>;
0017 status = "disabled";
0018 frame@2a830000 {
0019 frame-number = <1>;
0020 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0021 reg = <0x10000 0x10000>;
0022 };
0023 };
0024
0025 mailbox: mhu@2b1f0000 {
0026 compatible = "arm,mhu", "arm,primecell";
0027 reg = <0x0 0x2b1f0000 0x0 0x1000>;
0028 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
0029 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
0030 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0031 #mbox-cells = <1>;
0032 clocks = <&soc_refclk100mhz>;
0033 clock-names = "apb_pclk";
0034 };
0035
0036 smmu_gpu: iommu@2b400000 {
0037 compatible = "arm,mmu-400", "arm,smmu-v1";
0038 reg = <0x0 0x2b400000 0x0 0x10000>;
0039 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
0040 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0041 #iommu-cells = <1>;
0042 #global-interrupts = <1>;
0043 power-domains = <&scpi_devpd 1>;
0044 dma-coherent;
0045 status = "disabled";
0046 };
0047
0048 smmu_pcie: iommu@2b500000 {
0049 compatible = "arm,mmu-401", "arm,smmu-v1";
0050 reg = <0x0 0x2b500000 0x0 0x10000>;
0051 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
0052 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
0053 #iommu-cells = <1>;
0054 #global-interrupts = <1>;
0055 dma-coherent;
0056 status = "disabled";
0057 };
0058
0059 smmu_etr: iommu@2b600000 {
0060 compatible = "arm,mmu-401", "arm,smmu-v1";
0061 reg = <0x0 0x2b600000 0x0 0x10000>;
0062 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
0063 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0064 #iommu-cells = <1>;
0065 #global-interrupts = <1>;
0066 dma-coherent;
0067 power-domains = <&scpi_devpd 0>;
0068 };
0069
0070 gic: interrupt-controller@2c010000 {
0071 compatible = "arm,gic-400", "arm,cortex-a15-gic";
0072 reg = <0x0 0x2c010000 0 0x1000>,
0073 <0x0 0x2c02f000 0 0x2000>,
0074 <0x0 0x2c04f000 0 0x2000>,
0075 <0x0 0x2c06f000 0 0x2000>;
0076 #address-cells = <1>;
0077 #interrupt-cells = <3>;
0078 #size-cells = <1>;
0079 interrupt-controller;
0080 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
0081 ranges = <0 0 0x2c1c0000 0x40000>;
0082
0083 v2m_0: v2m@0 {
0084 compatible = "arm,gic-v2m-frame";
0085 msi-controller;
0086 reg = <0 0x10000>;
0087 };
0088
0089 v2m@10000 {
0090 compatible = "arm,gic-v2m-frame";
0091 msi-controller;
0092 reg = <0x10000 0x10000>;
0093 };
0094
0095 v2m@20000 {
0096 compatible = "arm,gic-v2m-frame";
0097 msi-controller;
0098 reg = <0x20000 0x10000>;
0099 };
0100
0101 v2m@30000 {
0102 compatible = "arm,gic-v2m-frame";
0103 msi-controller;
0104 reg = <0x30000 0x10000>;
0105 };
0106 };
0107
0108 timer {
0109 compatible = "arm,armv8-timer";
0110 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
0111 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
0112 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
0113 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
0114 };
0115
0116 /*
0117 * Juno TRMs specify the size for these coresight components as 64K.
0118 * The actual size is just 4K though 64K is reserved. Access to the
0119 * unmapped reserved region results in a DECERR response.
0120 */
0121 etf_sys0: etf@20010000 { /* etf0 */
0122 compatible = "arm,coresight-tmc", "arm,primecell";
0123 reg = <0 0x20010000 0 0x1000>;
0124
0125 clocks = <&soc_smc50mhz>;
0126 clock-names = "apb_pclk";
0127 power-domains = <&scpi_devpd 0>;
0128
0129 in-ports {
0130 port {
0131 etf0_in_port: endpoint {
0132 remote-endpoint = <&main_funnel_out_port>;
0133 };
0134 };
0135 };
0136
0137 out-ports {
0138 port {
0139 etf0_out_port: endpoint {
0140 };
0141 };
0142 };
0143 };
0144
0145 tpiu_sys: tpiu@20030000 {
0146 compatible = "arm,coresight-tpiu", "arm,primecell";
0147 reg = <0 0x20030000 0 0x1000>;
0148
0149 clocks = <&soc_smc50mhz>;
0150 clock-names = "apb_pclk";
0151 power-domains = <&scpi_devpd 0>;
0152 in-ports {
0153 port {
0154 tpiu_in_port: endpoint {
0155 remote-endpoint = <&replicator_out_port0>;
0156 };
0157 };
0158 };
0159 };
0160
0161 /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
0162 main_funnel: funnel@20040000 {
0163 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0164 reg = <0 0x20040000 0 0x1000>;
0165
0166 clocks = <&soc_smc50mhz>;
0167 clock-names = "apb_pclk";
0168 power-domains = <&scpi_devpd 0>;
0169
0170 out-ports {
0171 port {
0172 main_funnel_out_port: endpoint {
0173 remote-endpoint = <&etf0_in_port>;
0174 };
0175 };
0176 };
0177
0178 main_funnel_in_ports: in-ports {
0179 #address-cells = <1>;
0180 #size-cells = <0>;
0181
0182 port@0 {
0183 reg = <0>;
0184 main_funnel_in_port0: endpoint {
0185 remote-endpoint = <&cluster0_funnel_out_port>;
0186 };
0187 };
0188
0189 port@1 {
0190 reg = <1>;
0191 main_funnel_in_port1: endpoint {
0192 remote-endpoint = <&cluster1_funnel_out_port>;
0193 };
0194 };
0195 };
0196 };
0197
0198 etr_sys: etr@20070000 {
0199 compatible = "arm,coresight-tmc", "arm,primecell";
0200 reg = <0 0x20070000 0 0x1000>;
0201 iommus = <&smmu_etr 0>;
0202
0203 clocks = <&soc_smc50mhz>;
0204 clock-names = "apb_pclk";
0205 power-domains = <&scpi_devpd 0>;
0206 arm,scatter-gather;
0207 in-ports {
0208 port {
0209 etr_in_port: endpoint {
0210 remote-endpoint = <&replicator_out_port1>;
0211 };
0212 };
0213 };
0214 };
0215
0216 stm_sys: stm@20100000 {
0217 compatible = "arm,coresight-stm", "arm,primecell";
0218 reg = <0 0x20100000 0 0x1000>,
0219 <0 0x28000000 0 0x1000000>;
0220 reg-names = "stm-base", "stm-stimulus-base";
0221
0222 clocks = <&soc_smc50mhz>;
0223 clock-names = "apb_pclk";
0224 power-domains = <&scpi_devpd 0>;
0225 out-ports {
0226 port {
0227 stm_out_port: endpoint {
0228 };
0229 };
0230 };
0231 };
0232
0233 replicator@20120000 {
0234 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
0235 reg = <0 0x20120000 0 0x1000>;
0236
0237 clocks = <&soc_smc50mhz>;
0238 clock-names = "apb_pclk";
0239 power-domains = <&scpi_devpd 0>;
0240
0241 out-ports {
0242 #address-cells = <1>;
0243 #size-cells = <0>;
0244
0245 /* replicator output ports */
0246 port@0 {
0247 reg = <0>;
0248 replicator_out_port0: endpoint {
0249 remote-endpoint = <&tpiu_in_port>;
0250 };
0251 };
0252
0253 port@1 {
0254 reg = <1>;
0255 replicator_out_port1: endpoint {
0256 remote-endpoint = <&etr_in_port>;
0257 };
0258 };
0259 };
0260 in-ports {
0261 port {
0262 replicator_in_port0: endpoint {
0263 };
0264 };
0265 };
0266 };
0267
0268 cpu_debug0: cpu-debug@22010000 {
0269 compatible = "arm,coresight-cpu-debug", "arm,primecell";
0270 reg = <0x0 0x22010000 0x0 0x1000>;
0271
0272 clocks = <&soc_smc50mhz>;
0273 clock-names = "apb_pclk";
0274 power-domains = <&scpi_devpd 0>;
0275 };
0276
0277 etm0: etm@22040000 {
0278 compatible = "arm,coresight-etm4x", "arm,primecell";
0279 reg = <0 0x22040000 0 0x1000>;
0280
0281 clocks = <&soc_smc50mhz>;
0282 clock-names = "apb_pclk";
0283 power-domains = <&scpi_devpd 0>;
0284 out-ports {
0285 port {
0286 cluster0_etm0_out_port: endpoint {
0287 remote-endpoint = <&cluster0_funnel_in_port0>;
0288 };
0289 };
0290 };
0291 };
0292
0293 cti0: cti@22020000 {
0294 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
0295 "arm,primecell";
0296 reg = <0 0x22020000 0 0x1000>;
0297
0298 clocks = <&soc_smc50mhz>;
0299 clock-names = "apb_pclk";
0300 power-domains = <&scpi_devpd 0>;
0301
0302 arm,cs-dev-assoc = <&etm0>;
0303 };
0304
0305 funnel@220c0000 { /* cluster0 funnel */
0306 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0307 reg = <0 0x220c0000 0 0x1000>;
0308
0309 clocks = <&soc_smc50mhz>;
0310 clock-names = "apb_pclk";
0311 power-domains = <&scpi_devpd 0>;
0312 out-ports {
0313 port {
0314 cluster0_funnel_out_port: endpoint {
0315 remote-endpoint = <&main_funnel_in_port0>;
0316 };
0317 };
0318 };
0319
0320 in-ports {
0321 #address-cells = <1>;
0322 #size-cells = <0>;
0323
0324 port@0 {
0325 reg = <0>;
0326 cluster0_funnel_in_port0: endpoint {
0327 remote-endpoint = <&cluster0_etm0_out_port>;
0328 };
0329 };
0330
0331 port@1 {
0332 reg = <1>;
0333 cluster0_funnel_in_port1: endpoint {
0334 remote-endpoint = <&cluster0_etm1_out_port>;
0335 };
0336 };
0337 };
0338 };
0339
0340 cpu_debug1: cpu-debug@22110000 {
0341 compatible = "arm,coresight-cpu-debug", "arm,primecell";
0342 reg = <0x0 0x22110000 0x0 0x1000>;
0343
0344 clocks = <&soc_smc50mhz>;
0345 clock-names = "apb_pclk";
0346 power-domains = <&scpi_devpd 0>;
0347 };
0348
0349 etm1: etm@22140000 {
0350 compatible = "arm,coresight-etm4x", "arm,primecell";
0351 reg = <0 0x22140000 0 0x1000>;
0352
0353 clocks = <&soc_smc50mhz>;
0354 clock-names = "apb_pclk";
0355 power-domains = <&scpi_devpd 0>;
0356 out-ports {
0357 port {
0358 cluster0_etm1_out_port: endpoint {
0359 remote-endpoint = <&cluster0_funnel_in_port1>;
0360 };
0361 };
0362 };
0363 };
0364
0365 cti1: cti@22120000 {
0366 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
0367 "arm,primecell";
0368 reg = <0 0x22120000 0 0x1000>;
0369
0370 clocks = <&soc_smc50mhz>;
0371 clock-names = "apb_pclk";
0372 power-domains = <&scpi_devpd 0>;
0373
0374 arm,cs-dev-assoc = <&etm1>;
0375 };
0376
0377 cpu_debug2: cpu-debug@23010000 {
0378 compatible = "arm,coresight-cpu-debug", "arm,primecell";
0379 reg = <0x0 0x23010000 0x0 0x1000>;
0380
0381 clocks = <&soc_smc50mhz>;
0382 clock-names = "apb_pclk";
0383 power-domains = <&scpi_devpd 0>;
0384 };
0385
0386 etm2: etm@23040000 {
0387 compatible = "arm,coresight-etm4x", "arm,primecell";
0388 reg = <0 0x23040000 0 0x1000>;
0389
0390 clocks = <&soc_smc50mhz>;
0391 clock-names = "apb_pclk";
0392 power-domains = <&scpi_devpd 0>;
0393 out-ports {
0394 port {
0395 cluster1_etm0_out_port: endpoint {
0396 remote-endpoint = <&cluster1_funnel_in_port0>;
0397 };
0398 };
0399 };
0400 };
0401
0402 cti2: cti@23020000 {
0403 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
0404 "arm,primecell";
0405 reg = <0 0x23020000 0 0x1000>;
0406
0407 clocks = <&soc_smc50mhz>;
0408 clock-names = "apb_pclk";
0409 power-domains = <&scpi_devpd 0>;
0410
0411 arm,cs-dev-assoc = <&etm2>;
0412 };
0413
0414 funnel@230c0000 { /* cluster1 funnel */
0415 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0416 reg = <0 0x230c0000 0 0x1000>;
0417
0418 clocks = <&soc_smc50mhz>;
0419 clock-names = "apb_pclk";
0420 power-domains = <&scpi_devpd 0>;
0421 out-ports {
0422 port {
0423 cluster1_funnel_out_port: endpoint {
0424 remote-endpoint = <&main_funnel_in_port1>;
0425 };
0426 };
0427 };
0428
0429 in-ports {
0430 #address-cells = <1>;
0431 #size-cells = <0>;
0432
0433 port@0 {
0434 reg = <0>;
0435 cluster1_funnel_in_port0: endpoint {
0436 remote-endpoint = <&cluster1_etm0_out_port>;
0437 };
0438 };
0439
0440 port@1 {
0441 reg = <1>;
0442 cluster1_funnel_in_port1: endpoint {
0443 remote-endpoint = <&cluster1_etm1_out_port>;
0444 };
0445 };
0446 port@2 {
0447 reg = <2>;
0448 cluster1_funnel_in_port2: endpoint {
0449 remote-endpoint = <&cluster1_etm2_out_port>;
0450 };
0451 };
0452 port@3 {
0453 reg = <3>;
0454 cluster1_funnel_in_port3: endpoint {
0455 remote-endpoint = <&cluster1_etm3_out_port>;
0456 };
0457 };
0458 };
0459 };
0460
0461 cpu_debug3: cpu-debug@23110000 {
0462 compatible = "arm,coresight-cpu-debug", "arm,primecell";
0463 reg = <0x0 0x23110000 0x0 0x1000>;
0464
0465 clocks = <&soc_smc50mhz>;
0466 clock-names = "apb_pclk";
0467 power-domains = <&scpi_devpd 0>;
0468 };
0469
0470 etm3: etm@23140000 {
0471 compatible = "arm,coresight-etm4x", "arm,primecell";
0472 reg = <0 0x23140000 0 0x1000>;
0473
0474 clocks = <&soc_smc50mhz>;
0475 clock-names = "apb_pclk";
0476 power-domains = <&scpi_devpd 0>;
0477 out-ports {
0478 port {
0479 cluster1_etm1_out_port: endpoint {
0480 remote-endpoint = <&cluster1_funnel_in_port1>;
0481 };
0482 };
0483 };
0484 };
0485
0486 cti3: cti@23120000 {
0487 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
0488 "arm,primecell";
0489 reg = <0 0x23120000 0 0x1000>;
0490
0491 clocks = <&soc_smc50mhz>;
0492 clock-names = "apb_pclk";
0493 power-domains = <&scpi_devpd 0>;
0494
0495 arm,cs-dev-assoc = <&etm3>;
0496 };
0497
0498 cpu_debug4: cpu-debug@23210000 {
0499 compatible = "arm,coresight-cpu-debug", "arm,primecell";
0500 reg = <0x0 0x23210000 0x0 0x1000>;
0501
0502 clocks = <&soc_smc50mhz>;
0503 clock-names = "apb_pclk";
0504 power-domains = <&scpi_devpd 0>;
0505 };
0506
0507 etm4: etm@23240000 {
0508 compatible = "arm,coresight-etm4x", "arm,primecell";
0509 reg = <0 0x23240000 0 0x1000>;
0510
0511 clocks = <&soc_smc50mhz>;
0512 clock-names = "apb_pclk";
0513 power-domains = <&scpi_devpd 0>;
0514 out-ports {
0515 port {
0516 cluster1_etm2_out_port: endpoint {
0517 remote-endpoint = <&cluster1_funnel_in_port2>;
0518 };
0519 };
0520 };
0521 };
0522
0523 cti4: cti@23220000 {
0524 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
0525 "arm,primecell";
0526 reg = <0 0x23220000 0 0x1000>;
0527
0528 clocks = <&soc_smc50mhz>;
0529 clock-names = "apb_pclk";
0530 power-domains = <&scpi_devpd 0>;
0531
0532 arm,cs-dev-assoc = <&etm4>;
0533 };
0534
0535 cpu_debug5: cpu-debug@23310000 {
0536 compatible = "arm,coresight-cpu-debug", "arm,primecell";
0537 reg = <0x0 0x23310000 0x0 0x1000>;
0538
0539 clocks = <&soc_smc50mhz>;
0540 clock-names = "apb_pclk";
0541 power-domains = <&scpi_devpd 0>;
0542 };
0543
0544 etm5: etm@23340000 {
0545 compatible = "arm,coresight-etm4x", "arm,primecell";
0546 reg = <0 0x23340000 0 0x1000>;
0547
0548 clocks = <&soc_smc50mhz>;
0549 clock-names = "apb_pclk";
0550 power-domains = <&scpi_devpd 0>;
0551 out-ports {
0552 port {
0553 cluster1_etm3_out_port: endpoint {
0554 remote-endpoint = <&cluster1_funnel_in_port3>;
0555 };
0556 };
0557 };
0558 };
0559
0560 cti5: cti@23320000 {
0561 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
0562 "arm,primecell";
0563 reg = <0 0x23320000 0 0x1000>;
0564
0565 clocks = <&soc_smc50mhz>;
0566 clock-names = "apb_pclk";
0567 power-domains = <&scpi_devpd 0>;
0568
0569 arm,cs-dev-assoc = <&etm5>;
0570 };
0571
0572 cti_sys0: cti@20020000 { /* sys_cti_0 */
0573 compatible = "arm,coresight-cti", "arm,primecell";
0574 reg = <0 0x20020000 0 0x1000>;
0575
0576 clocks = <&soc_smc50mhz>;
0577 clock-names = "apb_pclk";
0578 power-domains = <&scpi_devpd 0>;
0579
0580 #address-cells = <1>;
0581 #size-cells = <0>;
0582
0583 trig-conns@0 {
0584 reg = <0>;
0585 arm,trig-in-sigs = <2 3>;
0586 arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>;
0587 arm,trig-out-sigs = <0 1>;
0588 arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>;
0589 arm,cs-dev-assoc = <&etr_sys>;
0590 };
0591
0592 trig-conns@1 {
0593 reg = <1>;
0594 arm,trig-in-sigs = <0 1>;
0595 arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>;
0596 arm,trig-out-sigs = <7 6>;
0597 arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>;
0598 arm,cs-dev-assoc = <&etf_sys0>;
0599 };
0600
0601 trig-conns@2 {
0602 reg = <2>;
0603 arm,trig-in-sigs = <4 5 6 7>;
0604 arm,trig-in-types = <STM_TOUT_SPTE STM_TOUT_SW
0605 STM_TOUT_HETE STM_ASYNCOUT>;
0606 arm,trig-out-sigs = <4 5>;
0607 arm,trig-out-types = <STM_HWEVENT STM_HWEVENT>;
0608 arm,cs-dev-assoc = <&stm_sys>;
0609 };
0610
0611 trig-conns@3 {
0612 reg = <3>;
0613 arm,trig-out-sigs = <2 3>;
0614 arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>;
0615 arm,cs-dev-assoc = <&tpiu_sys>;
0616 };
0617 };
0618
0619 cti_sys1: cti@20110000 { /* sys_cti_1 */
0620 compatible = "arm,coresight-cti", "arm,primecell";
0621 reg = <0 0x20110000 0 0x1000>;
0622
0623 clocks = <&soc_smc50mhz>;
0624 clock-names = "apb_pclk";
0625 power-domains = <&scpi_devpd 0>;
0626
0627 #address-cells = <1>;
0628 #size-cells = <0>;
0629
0630 trig-conns@0 {
0631 reg = <0>;
0632 arm,trig-in-sigs = <0>;
0633 arm,trig-in-types = <GEN_INTREQ>;
0634 arm,trig-out-sigs = <0>;
0635 arm,trig-out-types = <GEN_HALTREQ>;
0636 arm,trig-conn-name = "sys_profiler";
0637 };
0638
0639 trig-conns@1 {
0640 reg = <1>;
0641 arm,trig-out-sigs = <2 3>;
0642 arm,trig-out-types = <GEN_HALTREQ GEN_RESTARTREQ>;
0643 arm,trig-conn-name = "watchdog";
0644 };
0645
0646 trig-conns@2 {
0647 reg = <2>;
0648 arm,trig-out-sigs = <1 6>;
0649 arm,trig-out-types = <GEN_HALTREQ GEN_RESTARTREQ>;
0650 arm,trig-conn-name = "g_counter";
0651 };
0652 };
0653
0654 gpu: gpu@2d000000 {
0655 compatible = "arm,juno-mali", "arm,mali-t624";
0656 reg = <0 0x2d000000 0 0x10000>;
0657 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0658 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
0659 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0660 interrupt-names = "job", "mmu", "gpu";
0661 clocks = <&scpi_dvfs 2>;
0662 power-domains = <&scpi_devpd 1>;
0663 dma-coherent;
0664 /* The SMMU is only really of interest to bare-metal hypervisors */
0665 /* iommus = <&smmu_gpu 0>; */
0666 status = "disabled";
0667 };
0668
0669 sram: sram@2e000000 {
0670 compatible = "arm,juno-sram-ns", "mmio-sram";
0671 reg = <0x0 0x2e000000 0x0 0x8000>;
0672
0673 #address-cells = <1>;
0674 #size-cells = <1>;
0675 ranges = <0 0x0 0x2e000000 0x8000>;
0676
0677 cpu_scp_lpri: scp-sram@0 {
0678 compatible = "arm,juno-scp-shmem";
0679 reg = <0x0 0x200>;
0680 };
0681
0682 cpu_scp_hpri: scp-sram@200 {
0683 compatible = "arm,juno-scp-shmem";
0684 reg = <0x200 0x200>;
0685 };
0686 };
0687
0688 pcie_ctlr: pcie@40000000 {
0689 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
0690 device_type = "pci";
0691 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
0692 bus-range = <0 255>;
0693 linux,pci-domain = <0>;
0694 #address-cells = <3>;
0695 #size-cells = <2>;
0696 dma-coherent;
0697 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
0698 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
0699 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
0700 /* Standard AXI Translation entries as programmed by EDK2 */
0701 dma-ranges = <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>,
0702 <0x43000000 0x8 0x00000000 0x8 0x00000000 0x2 0x00000000>;
0703 #interrupt-cells = <1>;
0704 interrupt-map-mask = <0 0 0 7>;
0705 interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
0706 <0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
0707 <0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
0708 <0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
0709 msi-parent = <&v2m_0>;
0710 status = "disabled";
0711 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
0712 iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
0713 };
0714
0715 scpi {
0716 compatible = "arm,scpi";
0717 mboxes = <&mailbox 1>;
0718 shmem = <&cpu_scp_hpri>;
0719
0720 clocks {
0721 compatible = "arm,scpi-clocks";
0722
0723 scpi_dvfs: clocks-0 {
0724 compatible = "arm,scpi-dvfs-clocks";
0725 #clock-cells = <1>;
0726 clock-indices = <0>, <1>, <2>;
0727 clock-output-names = "atlclk", "aplclk","gpuclk";
0728 };
0729 scpi_clk: clocks-1 {
0730 compatible = "arm,scpi-variable-clocks";
0731 #clock-cells = <1>;
0732 clock-indices = <3>;
0733 clock-output-names = "pxlclk";
0734 };
0735 };
0736
0737 scpi_devpd: power-controller {
0738 compatible = "arm,scpi-power-domains";
0739 num-domains = <2>;
0740 #power-domain-cells = <1>;
0741 };
0742
0743 scpi_sensors0: sensors {
0744 compatible = "arm,scpi-sensors";
0745 #thermal-sensor-cells = <1>;
0746 };
0747 };
0748
0749 thermal-zones {
0750 pmic {
0751 polling-delay = <1000>;
0752 polling-delay-passive = <100>;
0753 thermal-sensors = <&scpi_sensors0 0>;
0754 };
0755
0756 soc {
0757 polling-delay = <1000>;
0758 polling-delay-passive = <100>;
0759 thermal-sensors = <&scpi_sensors0 3>;
0760 };
0761
0762 big_cluster_thermal_zone: big-cluster {
0763 polling-delay = <1000>;
0764 polling-delay-passive = <100>;
0765 thermal-sensors = <&scpi_sensors0 21>;
0766 status = "disabled";
0767 };
0768
0769 little_cluster_thermal_zone: little-cluster {
0770 polling-delay = <1000>;
0771 polling-delay-passive = <100>;
0772 thermal-sensors = <&scpi_sensors0 22>;
0773 status = "disabled";
0774 };
0775
0776 gpu0_thermal_zone: gpu0 {
0777 polling-delay = <1000>;
0778 polling-delay-passive = <100>;
0779 thermal-sensors = <&scpi_sensors0 23>;
0780 status = "disabled";
0781 };
0782
0783 gpu1_thermal_zone: gpu1 {
0784 polling-delay = <1000>;
0785 polling-delay-passive = <100>;
0786 thermal-sensors = <&scpi_sensors0 24>;
0787 status = "disabled";
0788 };
0789 };
0790
0791 smmu_dma: iommu@7fb00000 {
0792 compatible = "arm,mmu-401", "arm,smmu-v1";
0793 reg = <0x0 0x7fb00000 0x0 0x10000>;
0794 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
0795 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0796 #iommu-cells = <1>;
0797 #global-interrupts = <1>;
0798 dma-coherent;
0799 };
0800
0801 smmu_hdlcd1: iommu@7fb10000 {
0802 compatible = "arm,mmu-401", "arm,smmu-v1";
0803 reg = <0x0 0x7fb10000 0x0 0x10000>;
0804 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
0805 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0806 #iommu-cells = <1>;
0807 #global-interrupts = <1>;
0808 };
0809
0810 smmu_hdlcd0: iommu@7fb20000 {
0811 compatible = "arm,mmu-401", "arm,smmu-v1";
0812 reg = <0x0 0x7fb20000 0x0 0x10000>;
0813 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
0814 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0815 #iommu-cells = <1>;
0816 #global-interrupts = <1>;
0817 };
0818
0819 smmu_usb: iommu@7fb30000 {
0820 compatible = "arm,mmu-401", "arm,smmu-v1";
0821 reg = <0x0 0x7fb30000 0x0 0x10000>;
0822 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
0823 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
0824 #iommu-cells = <1>;
0825 #global-interrupts = <1>;
0826 dma-coherent;
0827 };
0828
0829 dma-controller@7ff00000 {
0830 compatible = "arm,pl330", "arm,primecell";
0831 reg = <0x0 0x7ff00000 0 0x1000>;
0832 #dma-cells = <1>;
0833 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
0834 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
0835 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
0836 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
0837 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
0838 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
0839 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0840 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0841 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
0842 iommus = <&smmu_dma 0>,
0843 <&smmu_dma 1>,
0844 <&smmu_dma 2>,
0845 <&smmu_dma 3>,
0846 <&smmu_dma 4>,
0847 <&smmu_dma 5>,
0848 <&smmu_dma 6>,
0849 <&smmu_dma 7>,
0850 <&smmu_dma 8>;
0851 clocks = <&soc_faxiclk>;
0852 clock-names = "apb_pclk";
0853 };
0854
0855 hdlcd@7ff50000 {
0856 compatible = "arm,hdlcd";
0857 reg = <0 0x7ff50000 0 0x1000>;
0858 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
0859 iommus = <&smmu_hdlcd1 0>;
0860 clocks = <&scpi_clk 3>;
0861 clock-names = "pxlclk";
0862
0863 port {
0864 hdlcd1_output: endpoint {
0865 remote-endpoint = <&tda998x_1_input>;
0866 };
0867 };
0868 };
0869
0870 hdlcd@7ff60000 {
0871 compatible = "arm,hdlcd";
0872 reg = <0 0x7ff60000 0 0x1000>;
0873 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0874 iommus = <&smmu_hdlcd0 0>;
0875 clocks = <&scpi_clk 3>;
0876 clock-names = "pxlclk";
0877
0878 port {
0879 hdlcd0_output: endpoint {
0880 remote-endpoint = <&tda998x_0_input>;
0881 };
0882 };
0883 };
0884
0885 soc_uart0: serial@7ff80000 {
0886 compatible = "arm,pl011", "arm,primecell";
0887 reg = <0x0 0x7ff80000 0x0 0x1000>;
0888 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0889 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
0890 clock-names = "uartclk", "apb_pclk";
0891 };
0892
0893 i2c@7ffa0000 {
0894 compatible = "snps,designware-i2c";
0895 reg = <0x0 0x7ffa0000 0x0 0x1000>;
0896 #address-cells = <1>;
0897 #size-cells = <0>;
0898 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
0899 clock-frequency = <400000>;
0900 i2c-sda-hold-time-ns = <500>;
0901 clocks = <&soc_smc50mhz>;
0902
0903 hdmi-transmitter@70 {
0904 compatible = "nxp,tda998x";
0905 reg = <0x70>;
0906 port {
0907 tda998x_0_input: endpoint {
0908 remote-endpoint = <&hdlcd0_output>;
0909 };
0910 };
0911 };
0912
0913 hdmi-transmitter@71 {
0914 compatible = "nxp,tda998x";
0915 reg = <0x71>;
0916 port {
0917 tda998x_1_input: endpoint {
0918 remote-endpoint = <&hdlcd1_output>;
0919 };
0920 };
0921 };
0922 };
0923
0924 usb@7ffb0000 {
0925 compatible = "generic-ohci";
0926 reg = <0x0 0x7ffb0000 0x0 0x10000>;
0927 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
0928 iommus = <&smmu_usb 0>;
0929 clocks = <&soc_usb48mhz>;
0930 };
0931
0932 usb@7ffc0000 {
0933 compatible = "generic-ehci";
0934 reg = <0x0 0x7ffc0000 0x0 0x10000>;
0935 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0936 iommus = <&smmu_usb 0>;
0937 clocks = <&soc_usb48mhz>;
0938 };
0939
0940 memory-controller@7ffd0000 {
0941 compatible = "arm,pl354", "arm,primecell";
0942 reg = <0 0x7ffd0000 0 0x1000>;
0943 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
0944 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0945 clocks = <&soc_smc50mhz>;
0946 clock-names = "apb_pclk";
0947 };
0948
0949 memory@80000000 {
0950 device_type = "memory";
0951 /* last 16MB of the first memory area is reserved for secure world use by firmware */
0952 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
0953 <0x00000008 0x80000000 0x1 0x80000000>;
0954 };
0955
0956 bus@8000000 {
0957 #interrupt-cells = <1>;
0958 interrupt-map-mask = <0 0 15>;
0959 interrupt-map = <0 0 0 &gic 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
0960 <0 0 1 &gic 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
0961 <0 0 2 &gic 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0962 <0 0 3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
0963 <0 0 4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
0964 <0 0 5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
0965 <0 0 6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
0966 <0 0 7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
0967 <0 0 8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
0968 <0 0 9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
0969 <0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
0970 <0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
0971 <0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
0972 };
0973
0974 site2: tlx-bus@60000000 {
0975 compatible = "simple-bus";
0976 #address-cells = <1>;
0977 #size-cells = <1>;
0978 ranges = <0 0 0x60000000 0x10000000>;
0979 #interrupt-cells = <1>;
0980 interrupt-map-mask = <0 0>;
0981 interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
0982 };
0983 };
