0001 // SPDX-License-Identifier: GPL-2.0 or MIT
0002 /*
0003 * Copyright (c) 2022, Arm Limited. All rights reserved.
0004 * Copyright (c) 2022, Linaro Limited. All rights reserved.
0005 *
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009
0010 / {
0011 interrupt-parent = <&gic>;
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014
0015 aliases {
0016 serial0 = &uart0;
0017 serial1 = &uart1;
0018 };
0019
0020 chosen {
0021 stdout-path = "serial0:115200n8";
0022 };
0023
0024 cpus {
0025 #address-cells = <1>;
0026 #size-cells = <0>;
0027
0028 cpu: cpu@0 {
0029 device_type = "cpu";
0030 compatible = "arm,cortex-a35";
0031 reg = <0>;
0032 next-level-cache = <&L2_0>;
0033 };
0034 };
0035
0036 memory@88200000 {
0037 device_type = "memory";
0038 reg = <0x88200000 0x77e00000>;
0039 };
0040
0041 gic: interrupt-controller@1c000000 {
0042 compatible = "arm,gic-400";
0043 #interrupt-cells = <3>;
0044 #address-cells = <0>;
0045 interrupt-controller;
0046 reg = <0x1c010000 0x1000>,
0047 <0x1c02f000 0x2000>,
0048 <0x1c04f000 0x1000>,
0049 <0x1c06f000 0x2000>;
0050 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
0051 IRQ_TYPE_LEVEL_LOW)>;
0052 };
0053
0054 L2_0: l2-cache0 {
0055 compatible = "cache";
0056 cache-level = <2>;
0057 cache-size = <0x80000>;
0058 cache-line-size = <64>;
0059 cache-sets = <1024>;
0060 };
0061
0062 refclk100mhz: refclk100mhz {
0063 compatible = "fixed-clock";
0064 #clock-cells = <0>;
0065 clock-frequency = <100000000>;
0066 clock-output-names = "apb_pclk";
0067 };
0068
0069 smbclk: refclk24mhzx2 {
0070 /* Reference 24MHz clock x 2 */
0071 compatible = "fixed-clock";
0072 #clock-cells = <0>;
0073 clock-frequency = <48000000>;
0074 clock-output-names = "smclk";
0075 };
0076
0077 timer {
0078 compatible = "arm,armv8-timer";
0079 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
0080 IRQ_TYPE_LEVEL_LOW)>,
0081 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
0082 IRQ_TYPE_LEVEL_LOW)>,
0083 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
0084 IRQ_TYPE_LEVEL_LOW)>,
0085 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
0086 IRQ_TYPE_LEVEL_LOW)>;
0087 };
0088
0089 uartclk: uartclk {
0090 /* UART clock - 50MHz */
0091 compatible = "fixed-clock";
0092 #clock-cells = <0>;
0093 clock-frequency = <50000000>;
0094 clock-output-names = "uartclk";
0095 };
0096
0097 psci {
0098 compatible = "arm,psci-1.0", "arm,psci-0.2";
0099 method = "smc";
0100 };
0101
0102 soc {
0103 compatible = "simple-bus";
0104 #address-cells = <1>;
0105 #size-cells = <1>;
0106 interrupt-parent = <&gic>;
0107 ranges;
0108
0109 timer@1a220000 {
0110 compatible = "arm,armv7-timer-mem";
0111 reg = <0x1a220000 0x1000>;
0112 #address-cells = <1>;
0113 #size-cells = <1>;
0114 clock-frequency = <50000000>;
0115 ranges;
0116
0117 frame@1a230000 {
0118 frame-number = <0>;
0119 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0120 reg = <0x1a230000 0x1000>;
0121 };
0122 };
0123
0124 uart0: serial@1a510000 {
0125 compatible = "arm,pl011", "arm,primecell";
0126 reg = <0x1a510000 0x1000>;
0127 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0128 clocks = <&uartclk>, <&refclk100mhz>;
0129 clock-names = "uartclk", "apb_pclk";
0130 };
0131
0132 uart1: serial@1a520000 {
0133 compatible = "arm,pl011", "arm,primecell";
0134 reg = <0x1a520000 0x1000>;
0135 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0136 clocks = <&uartclk>, <&refclk100mhz>;
0137 clock-names = "uartclk", "apb_pclk";
0138 };
0139
0140 mhu_hse1: mailbox@1b820000 {
0141 compatible = "arm,mhuv2-tx", "arm,primecell";
0142 reg = <0x1b820000 0x1000>;
0143 clocks = <&refclk100mhz>;
0144 clock-names = "apb_pclk";
0145 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0146 #mbox-cells = <2>;
0147 arm,mhuv2-protocols = <0 0>;
0148 secure-status = "okay"; /* secure-world-only */
0149 status = "disabled";
0150 };
0151
0152 mhu_seh1: mailbox@1b830000 {
0153 compatible = "arm,mhuv2-rx", "arm,primecell";
0154 reg = <0x1b830000 0x1000>;
0155 clocks = <&refclk100mhz>;
0156 clock-names = "apb_pclk";
0157 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0158 #mbox-cells = <2>;
0159 arm,mhuv2-protocols = <0 0>;
0160 secure-status = "okay"; /* secure-world-only */
0161 status = "disabled";
0162 };
0163 };
0164 };
