0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * dts file for AppliedMicro (APM) X-Gene Storm SOC
0004 *
0005 * Copyright (C) 2013, Applied Micro Circuits Corporation
0006 */
0007
0008 / {
0009 compatible = "apm,xgene-storm";
0010 interrupt-parent = <&gic>;
0011 #address-cells = <2>;
0012 #size-cells = <2>;
0013
0014 cpus {
0015 #address-cells = <2>;
0016 #size-cells = <0>;
0017
0018 cpu@0 {
0019 device_type = "cpu";
0020 compatible = "apm,potenza";
0021 reg = <0x0 0x000>;
0022 enable-method = "spin-table";
0023 cpu-release-addr = <0x1 0x0000fff8>;
0024 next-level-cache = <&xgene_L2_0>;
0025 };
0026 cpu@1 {
0027 device_type = "cpu";
0028 compatible = "apm,potenza";
0029 reg = <0x0 0x001>;
0030 enable-method = "spin-table";
0031 cpu-release-addr = <0x1 0x0000fff8>;
0032 next-level-cache = <&xgene_L2_0>;
0033 };
0034 cpu@100 {
0035 device_type = "cpu";
0036 compatible = "apm,potenza";
0037 reg = <0x0 0x100>;
0038 enable-method = "spin-table";
0039 cpu-release-addr = <0x1 0x0000fff8>;
0040 next-level-cache = <&xgene_L2_1>;
0041 };
0042 cpu@101 {
0043 device_type = "cpu";
0044 compatible = "apm,potenza";
0045 reg = <0x0 0x101>;
0046 enable-method = "spin-table";
0047 cpu-release-addr = <0x1 0x0000fff8>;
0048 next-level-cache = <&xgene_L2_1>;
0049 };
0050 cpu@200 {
0051 device_type = "cpu";
0052 compatible = "apm,potenza";
0053 reg = <0x0 0x200>;
0054 enable-method = "spin-table";
0055 cpu-release-addr = <0x1 0x0000fff8>;
0056 next-level-cache = <&xgene_L2_2>;
0057 };
0058 cpu@201 {
0059 device_type = "cpu";
0060 compatible = "apm,potenza";
0061 reg = <0x0 0x201>;
0062 enable-method = "spin-table";
0063 cpu-release-addr = <0x1 0x0000fff8>;
0064 next-level-cache = <&xgene_L2_2>;
0065 };
0066 cpu@300 {
0067 device_type = "cpu";
0068 compatible = "apm,potenza";
0069 reg = <0x0 0x300>;
0070 enable-method = "spin-table";
0071 cpu-release-addr = <0x1 0x0000fff8>;
0072 next-level-cache = <&xgene_L2_3>;
0073 };
0074 cpu@301 {
0075 device_type = "cpu";
0076 compatible = "apm,potenza";
0077 reg = <0x0 0x301>;
0078 enable-method = "spin-table";
0079 cpu-release-addr = <0x1 0x0000fff8>;
0080 next-level-cache = <&xgene_L2_3>;
0081 };
0082 xgene_L2_0: l2-cache-0 {
0083 compatible = "cache";
0084 };
0085 xgene_L2_1: l2-cache-1 {
0086 compatible = "cache";
0087 };
0088 xgene_L2_2: l2-cache-2 {
0089 compatible = "cache";
0090 };
0091 xgene_L2_3: l2-cache-3 {
0092 compatible = "cache";
0093 };
0094 };
0095
0096 gic: interrupt-controller@78010000 {
0097 compatible = "arm,cortex-a15-gic";
0098 #interrupt-cells = <3>;
0099 interrupt-controller;
0100 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
0101 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
0102 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
0103 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
0104 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
0105 };
0106
0107 timer {
0108 compatible = "arm,armv8-timer";
0109 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
0110 <1 13 0xff08>, /* Non-secure Phys IRQ */
0111 <1 14 0xff08>, /* Virt IRQ */
0112 <1 15 0xff08>; /* Hyp IRQ */
0113 clock-frequency = <50000000>;
0114 };
0115
0116 pmu {
0117 compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
0118 interrupts = <1 12 0xff04>;
0119 };
0120
0121 soc {
0122 compatible = "simple-bus";
0123 #address-cells = <2>;
0124 #size-cells = <2>;
0125 ranges;
0126 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
0127
0128 clocks {
0129 #address-cells = <2>;
0130 #size-cells = <2>;
0131 ranges;
0132 refclk: refclk {
0133 compatible = "fixed-clock";
0134 #clock-cells = <1>;
0135 clock-frequency = <100000000>;
0136 clock-output-names = "refclk";
0137 };
0138
0139 pcppll: pcppll@17000100 {
0140 compatible = "apm,xgene-pcppll-clock";
0141 #clock-cells = <1>;
0142 clocks = <&refclk 0>;
0143 clock-names = "pcppll";
0144 reg = <0x0 0x17000100 0x0 0x1000>;
0145 clock-output-names = "pcppll";
0146 type = <0>;
0147 };
0148
0149 socpll: socpll@17000120 {
0150 compatible = "apm,xgene-socpll-clock";
0151 #clock-cells = <1>;
0152 clocks = <&refclk 0>;
0153 clock-names = "socpll";
0154 reg = <0x0 0x17000120 0x0 0x1000>;
0155 clock-output-names = "socpll";
0156 type = <1>;
0157 };
0158
0159 socplldiv2: socplldiv2 {
0160 compatible = "fixed-factor-clock";
0161 #clock-cells = <1>;
0162 clocks = <&socpll 0>;
0163 clock-names = "socplldiv2";
0164 clock-mult = <1>;
0165 clock-div = <2>;
0166 clock-output-names = "socplldiv2";
0167 };
0168
0169 ahbclk: ahbclk@17000000 {
0170 compatible = "apm,xgene-device-clock";
0171 #clock-cells = <1>;
0172 clocks = <&socplldiv2 0>;
0173 reg = <0x0 0x17000000 0x0 0x2000>;
0174 reg-names = "div-reg";
0175 divider-offset = <0x164>;
0176 divider-width = <0x5>;
0177 divider-shift = <0x0>;
0178 clock-output-names = "ahbclk";
0179 };
0180
0181 sdioclk: sdioclk@1f2ac000 {
0182 compatible = "apm,xgene-device-clock";
0183 #clock-cells = <1>;
0184 clocks = <&socplldiv2 0>;
0185 reg = <0x0 0x1f2ac000 0x0 0x1000
0186 0x0 0x17000000 0x0 0x2000>;
0187 reg-names = "csr-reg", "div-reg";
0188 csr-offset = <0x0>;
0189 csr-mask = <0x2>;
0190 enable-offset = <0x8>;
0191 enable-mask = <0x2>;
0192 divider-offset = <0x178>;
0193 divider-width = <0x8>;
0194 divider-shift = <0x0>;
0195 clock-output-names = "sdioclk";
0196 };
0197
0198 ethclk: ethclk {
0199 compatible = "apm,xgene-device-clock";
0200 #clock-cells = <1>;
0201 clocks = <&socplldiv2 0>;
0202 clock-names = "ethclk";
0203 reg = <0x0 0x17000000 0x0 0x1000>;
0204 reg-names = "div-reg";
0205 divider-offset = <0x238>;
0206 divider-width = <0x9>;
0207 divider-shift = <0x0>;
0208 clock-output-names = "ethclk";
0209 };
0210
0211 menetclk: menetclk {
0212 compatible = "apm,xgene-device-clock";
0213 #clock-cells = <1>;
0214 clocks = <ðclk 0>;
0215 reg = <0x0 0x1702c000 0x0 0x1000>;
0216 reg-names = "csr-reg";
0217 clock-output-names = "menetclk";
0218 };
0219
0220 sge0clk: sge0clk@1f21c000 {
0221 compatible = "apm,xgene-device-clock";
0222 #clock-cells = <1>;
0223 clocks = <&socplldiv2 0>;
0224 reg = <0x0 0x1f21c000 0x0 0x1000>;
0225 reg-names = "csr-reg";
0226 csr-mask = <0xa>;
0227 enable-mask = <0xf>;
0228 clock-output-names = "sge0clk";
0229 };
0230
0231 xge0clk: xge0clk@1f61c000 {
0232 compatible = "apm,xgene-device-clock";
0233 #clock-cells = <1>;
0234 clocks = <&socplldiv2 0>;
0235 reg = <0x0 0x1f61c000 0x0 0x1000>;
0236 reg-names = "csr-reg";
0237 csr-mask = <0x3>;
0238 clock-output-names = "xge0clk";
0239 };
0240
0241 xge1clk: xge1clk@1f62c000 {
0242 compatible = "apm,xgene-device-clock";
0243 status = "disabled";
0244 #clock-cells = <1>;
0245 clocks = <&socplldiv2 0>;
0246 reg = <0x0 0x1f62c000 0x0 0x1000>;
0247 reg-names = "csr-reg";
0248 csr-mask = <0x3>;
0249 clock-output-names = "xge1clk";
0250 };
0251
0252 sataphy1clk: sataphy1clk@1f21c000 {
0253 compatible = "apm,xgene-device-clock";
0254 #clock-cells = <1>;
0255 clocks = <&socplldiv2 0>;
0256 reg = <0x0 0x1f21c000 0x0 0x1000>;
0257 reg-names = "csr-reg";
0258 clock-output-names = "sataphy1clk";
0259 status = "disabled";
0260 csr-offset = <0x4>;
0261 csr-mask = <0x00>;
0262 enable-offset = <0x0>;
0263 enable-mask = <0x06>;
0264 };
0265
0266 sataphy2clk: sataphy1clk@1f22c000 {
0267 compatible = "apm,xgene-device-clock";
0268 #clock-cells = <1>;
0269 clocks = <&socplldiv2 0>;
0270 reg = <0x0 0x1f22c000 0x0 0x1000>;
0271 reg-names = "csr-reg";
0272 clock-output-names = "sataphy2clk";
0273 status = "ok";
0274 csr-offset = <0x4>;
0275 csr-mask = <0x3a>;
0276 enable-offset = <0x0>;
0277 enable-mask = <0x06>;
0278 };
0279
0280 sataphy3clk: sataphy1clk@1f23c000 {
0281 compatible = "apm,xgene-device-clock";
0282 #clock-cells = <1>;
0283 clocks = <&socplldiv2 0>;
0284 reg = <0x0 0x1f23c000 0x0 0x1000>;
0285 reg-names = "csr-reg";
0286 clock-output-names = "sataphy3clk";
0287 status = "ok";
0288 csr-offset = <0x4>;
0289 csr-mask = <0x3a>;
0290 enable-offset = <0x0>;
0291 enable-mask = <0x06>;
0292 };
0293
0294 sata01clk: sata01clk@1f21c000 {
0295 compatible = "apm,xgene-device-clock";
0296 #clock-cells = <1>;
0297 clocks = <&socplldiv2 0>;
0298 reg = <0x0 0x1f21c000 0x0 0x1000>;
0299 reg-names = "csr-reg";
0300 clock-output-names = "sata01clk";
0301 csr-offset = <0x4>;
0302 csr-mask = <0x05>;
0303 enable-offset = <0x0>;
0304 enable-mask = <0x39>;
0305 };
0306
0307 sata23clk: sata23clk@1f22c000 {
0308 compatible = "apm,xgene-device-clock";
0309 #clock-cells = <1>;
0310 clocks = <&socplldiv2 0>;
0311 reg = <0x0 0x1f22c000 0x0 0x1000>;
0312 reg-names = "csr-reg";
0313 clock-output-names = "sata23clk";
0314 csr-offset = <0x4>;
0315 csr-mask = <0x05>;
0316 enable-offset = <0x0>;
0317 enable-mask = <0x39>;
0318 };
0319
0320 sata45clk: sata45clk@1f23c000 {
0321 compatible = "apm,xgene-device-clock";
0322 #clock-cells = <1>;
0323 clocks = <&socplldiv2 0>;
0324 reg = <0x0 0x1f23c000 0x0 0x1000>;
0325 reg-names = "csr-reg";
0326 clock-output-names = "sata45clk";
0327 csr-offset = <0x4>;
0328 csr-mask = <0x05>;
0329 enable-offset = <0x0>;
0330 enable-mask = <0x39>;
0331 };
0332
0333 rtcclk: rtcclk@17000000 {
0334 compatible = "apm,xgene-device-clock";
0335 #clock-cells = <1>;
0336 clocks = <&socplldiv2 0>;
0337 reg = <0x0 0x17000000 0x0 0x2000>;
0338 reg-names = "csr-reg";
0339 csr-offset = <0xc>;
0340 csr-mask = <0x2>;
0341 enable-offset = <0x10>;
0342 enable-mask = <0x2>;
0343 clock-output-names = "rtcclk";
0344 };
0345
0346 rngpkaclk: rngpkaclk@17000000 {
0347 compatible = "apm,xgene-device-clock";
0348 #clock-cells = <1>;
0349 clocks = <&socplldiv2 0>;
0350 reg = <0x0 0x17000000 0x0 0x2000>;
0351 reg-names = "csr-reg";
0352 csr-offset = <0xc>;
0353 csr-mask = <0x10>;
0354 enable-offset = <0x10>;
0355 enable-mask = <0x10>;
0356 clock-output-names = "rngpkaclk";
0357 };
0358
0359 pcie0clk: pcie0clk@1f2bc000 {
0360 status = "disabled";
0361 compatible = "apm,xgene-device-clock";
0362 #clock-cells = <1>;
0363 clocks = <&socplldiv2 0>;
0364 reg = <0x0 0x1f2bc000 0x0 0x1000>;
0365 reg-names = "csr-reg";
0366 clock-output-names = "pcie0clk";
0367 };
0368
0369 pcie1clk: pcie1clk@1f2cc000 {
0370 status = "disabled";
0371 compatible = "apm,xgene-device-clock";
0372 #clock-cells = <1>;
0373 clocks = <&socplldiv2 0>;
0374 reg = <0x0 0x1f2cc000 0x0 0x1000>;
0375 reg-names = "csr-reg";
0376 clock-output-names = "pcie1clk";
0377 };
0378
0379 pcie2clk: pcie2clk@1f2dc000 {
0380 status = "disabled";
0381 compatible = "apm,xgene-device-clock";
0382 #clock-cells = <1>;
0383 clocks = <&socplldiv2 0>;
0384 reg = <0x0 0x1f2dc000 0x0 0x1000>;
0385 reg-names = "csr-reg";
0386 clock-output-names = "pcie2clk";
0387 };
0388
0389 pcie3clk: pcie3clk@1f50c000 {
0390 status = "disabled";
0391 compatible = "apm,xgene-device-clock";
0392 #clock-cells = <1>;
0393 clocks = <&socplldiv2 0>;
0394 reg = <0x0 0x1f50c000 0x0 0x1000>;
0395 reg-names = "csr-reg";
0396 clock-output-names = "pcie3clk";
0397 };
0398
0399 pcie4clk: pcie4clk@1f51c000 {
0400 status = "disabled";
0401 compatible = "apm,xgene-device-clock";
0402 #clock-cells = <1>;
0403 clocks = <&socplldiv2 0>;
0404 reg = <0x0 0x1f51c000 0x0 0x1000>;
0405 reg-names = "csr-reg";
0406 clock-output-names = "pcie4clk";
0407 };
0408
0409 dmaclk: dmaclk@1f27c000 {
0410 compatible = "apm,xgene-device-clock";
0411 #clock-cells = <1>;
0412 clocks = <&socplldiv2 0>;
0413 reg = <0x0 0x1f27c000 0x0 0x1000>;
0414 reg-names = "csr-reg";
0415 clock-output-names = "dmaclk";
0416 };
0417 };
0418
0419 msi: msi@79000000 {
0420 compatible = "apm,xgene1-msi";
0421 msi-controller;
0422 reg = <0x00 0x79000000 0x0 0x900000>;
0423 interrupts = < 0x0 0x10 0x4
0424 0x0 0x11 0x4
0425 0x0 0x12 0x4
0426 0x0 0x13 0x4
0427 0x0 0x14 0x4
0428 0x0 0x15 0x4
0429 0x0 0x16 0x4
0430 0x0 0x17 0x4
0431 0x0 0x18 0x4
0432 0x0 0x19 0x4
0433 0x0 0x1a 0x4
0434 0x0 0x1b 0x4
0435 0x0 0x1c 0x4
0436 0x0 0x1d 0x4
0437 0x0 0x1e 0x4
0438 0x0 0x1f 0x4>;
0439 };
0440
0441 scu: system-clk-controller@17000000 {
0442 compatible = "apm,xgene-scu","syscon";
0443 reg = <0x0 0x17000000 0x0 0x400>;
0444 };
0445
0446 reboot: reboot@17000014 {
0447 compatible = "syscon-reboot";
0448 regmap = <&scu>;
0449 offset = <0x14>;
0450 mask = <0x1>;
0451 };
0452
0453 csw: csw@7e200000 {
0454 compatible = "apm,xgene-csw", "syscon";
0455 reg = <0x0 0x7e200000 0x0 0x1000>;
0456 };
0457
0458 mcba: mcba@7e700000 {
0459 compatible = "apm,xgene-mcb", "syscon";
0460 reg = <0x0 0x7e700000 0x0 0x1000>;
0461 };
0462
0463 mcbb: mcbb@7e720000 {
0464 compatible = "apm,xgene-mcb", "syscon";
0465 reg = <0x0 0x7e720000 0x0 0x1000>;
0466 };
0467
0468 efuse: efuse@1054a000 {
0469 compatible = "apm,xgene-efuse", "syscon";
0470 reg = <0x0 0x1054a000 0x0 0x20>;
0471 };
0472
0473 rb: rb@7e000000 {
0474 compatible = "apm,xgene-rb", "syscon";
0475 reg = <0x0 0x7e000000 0x0 0x10>;
0476 };
0477
0478 edac@78800000 {
0479 compatible = "apm,xgene-edac";
0480 #address-cells = <2>;
0481 #size-cells = <2>;
0482 ranges;
0483 regmap-csw = <&csw>;
0484 regmap-mcba = <&mcba>;
0485 regmap-mcbb = <&mcbb>;
0486 regmap-efuse = <&efuse>;
0487 regmap-rb = <&rb>;
0488 reg = <0x0 0x78800000 0x0 0x100>;
0489 interrupts = <0x0 0x20 0x4>,
0490 <0x0 0x21 0x4>,
0491 <0x0 0x27 0x4>;
0492
0493 edacmc@7e800000 {
0494 compatible = "apm,xgene-edac-mc";
0495 reg = <0x0 0x7e800000 0x0 0x1000>;
0496 memory-controller = <0>;
0497 };
0498
0499 edacmc@7e840000 {
0500 compatible = "apm,xgene-edac-mc";
0501 reg = <0x0 0x7e840000 0x0 0x1000>;
0502 memory-controller = <1>;
0503 };
0504
0505 edacmc@7e880000 {
0506 compatible = "apm,xgene-edac-mc";
0507 reg = <0x0 0x7e880000 0x0 0x1000>;
0508 memory-controller = <2>;
0509 };
0510
0511 edacmc@7e8c0000 {
0512 compatible = "apm,xgene-edac-mc";
0513 reg = <0x0 0x7e8c0000 0x0 0x1000>;
0514 memory-controller = <3>;
0515 };
0516
0517 edacpmd@7c000000 {
0518 compatible = "apm,xgene-edac-pmd";
0519 reg = <0x0 0x7c000000 0x0 0x200000>;
0520 pmd-controller = <0>;
0521 };
0522
0523 edacpmd@7c200000 {
0524 compatible = "apm,xgene-edac-pmd";
0525 reg = <0x0 0x7c200000 0x0 0x200000>;
0526 pmd-controller = <1>;
0527 };
0528
0529 edacpmd@7c400000 {
0530 compatible = "apm,xgene-edac-pmd";
0531 reg = <0x0 0x7c400000 0x0 0x200000>;
0532 pmd-controller = <2>;
0533 };
0534
0535 edacpmd@7c600000 {
0536 compatible = "apm,xgene-edac-pmd";
0537 reg = <0x0 0x7c600000 0x0 0x200000>;
0538 pmd-controller = <3>;
0539 };
0540
0541 edacl3@7e600000 {
0542 compatible = "apm,xgene-edac-l3";
0543 reg = <0x0 0x7e600000 0x0 0x1000>;
0544 };
0545
0546 edacsoc@7e930000 {
0547 compatible = "apm,xgene-edac-soc-v1";
0548 reg = <0x0 0x7e930000 0x0 0x1000>;
0549 };
0550 };
0551
0552 pmu: pmu@78810000 {
0553 compatible = "apm,xgene-pmu-v2";
0554 #address-cells = <2>;
0555 #size-cells = <2>;
0556 ranges;
0557 regmap-csw = <&csw>;
0558 regmap-mcba = <&mcba>;
0559 regmap-mcbb = <&mcbb>;
0560 reg = <0x0 0x78810000 0x0 0x1000>;
0561 interrupts = <0x0 0x22 0x4>;
0562
0563 pmul3c@7e610000 {
0564 compatible = "apm,xgene-pmu-l3c";
0565 reg = <0x0 0x7e610000 0x0 0x1000>;
0566 };
0567
0568 pmuiob@7e940000 {
0569 compatible = "apm,xgene-pmu-iob";
0570 reg = <0x0 0x7e940000 0x0 0x1000>;
0571 };
0572
0573 pmucmcb@7e710000 {
0574 compatible = "apm,xgene-pmu-mcb";
0575 reg = <0x0 0x7e710000 0x0 0x1000>;
0576 enable-bit-index = <0>;
0577 };
0578
0579 pmucmcb@7e730000 {
0580 compatible = "apm,xgene-pmu-mcb";
0581 reg = <0x0 0x7e730000 0x0 0x1000>;
0582 enable-bit-index = <1>;
0583 };
0584
0585 pmucmc@7e810000 {
0586 compatible = "apm,xgene-pmu-mc";
0587 reg = <0x0 0x7e810000 0x0 0x1000>;
0588 enable-bit-index = <0>;
0589 };
0590
0591 pmucmc@7e850000 {
0592 compatible = "apm,xgene-pmu-mc";
0593 reg = <0x0 0x7e850000 0x0 0x1000>;
0594 enable-bit-index = <1>;
0595 };
0596
0597 pmucmc@7e890000 {
0598 compatible = "apm,xgene-pmu-mc";
0599 reg = <0x0 0x7e890000 0x0 0x1000>;
0600 enable-bit-index = <2>;
0601 };
0602
0603 pmucmc@7e8d0000 {
0604 compatible = "apm,xgene-pmu-mc";
0605 reg = <0x0 0x7e8d0000 0x0 0x1000>;
0606 enable-bit-index = <3>;
0607 };
0608 };
0609
0610 pcie0: pcie@1f2b0000 {
0611 status = "disabled";
0612 device_type = "pci";
0613 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
0614 #interrupt-cells = <1>;
0615 #size-cells = <2>;
0616 #address-cells = <3>;
0617 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
0618 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
0619 reg-names = "csr", "cfg";
0620 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
0621 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */
0622 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
0623 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0624 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
0625 bus-range = <0x00 0xff>;
0626 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0627 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
0628 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
0629 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4
0630 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>;
0631 dma-coherent;
0632 clocks = <&pcie0clk 0>;
0633 msi-parent = <&msi>;
0634 };
0635
0636 pcie1: pcie@1f2c0000 {
0637 status = "disabled";
0638 device_type = "pci";
0639 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
0640 #interrupt-cells = <1>;
0641 #size-cells = <2>;
0642 #address-cells = <3>;
0643 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
0644 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
0645 reg-names = "csr", "cfg";
0646 ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
0647 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */
0648 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
0649 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0650 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
0651 bus-range = <0x00 0xff>;
0652 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0653 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
0654 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
0655 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4
0656 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>;
0657 dma-coherent;
0658 clocks = <&pcie1clk 0>;
0659 msi-parent = <&msi>;
0660 };
0661
0662 pcie2: pcie@1f2d0000 {
0663 status = "disabled";
0664 device_type = "pci";
0665 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
0666 #interrupt-cells = <1>;
0667 #size-cells = <2>;
0668 #address-cells = <3>;
0669 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
0670 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
0671 reg-names = "csr", "cfg";
0672 ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */
0673 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */
0674 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
0675 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0676 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
0677 bus-range = <0x00 0xff>;
0678 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0679 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
0680 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
0681 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4
0682 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>;
0683 dma-coherent;
0684 clocks = <&pcie2clk 0>;
0685 msi-parent = <&msi>;
0686 };
0687
0688 pcie3: pcie@1f500000 {
0689 status = "disabled";
0690 device_type = "pci";
0691 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
0692 #interrupt-cells = <1>;
0693 #size-cells = <2>;
0694 #address-cells = <3>;
0695 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
0696 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
0697 reg-names = "csr", "cfg";
0698 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
0699 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */
0700 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
0701 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0702 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
0703 bus-range = <0x00 0xff>;
0704 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0705 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
0706 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
0707 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4
0708 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>;
0709 dma-coherent;
0710 clocks = <&pcie3clk 0>;
0711 msi-parent = <&msi>;
0712 };
0713
0714 pcie4: pcie@1f510000 {
0715 status = "disabled";
0716 device_type = "pci";
0717 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
0718 #interrupt-cells = <1>;
0719 #size-cells = <2>;
0720 #address-cells = <3>;
0721 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
0722 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
0723 reg-names = "csr", "cfg";
0724 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
0725 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */
0726 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
0727 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0728 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
0729 bus-range = <0x00 0xff>;
0730 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0731 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
0732 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
0733 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4
0734 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>;
0735 dma-coherent;
0736 clocks = <&pcie4clk 0>;
0737 msi-parent = <&msi>;
0738 };
0739
0740 mailbox: mailbox@10540000 {
0741 compatible = "apm,xgene-slimpro-mbox";
0742 reg = <0x0 0x10540000 0x0 0xa000>;
0743 #mbox-cells = <1>;
0744 interrupts = <0x0 0x0 0x4>,
0745 <0x0 0x1 0x4>,
0746 <0x0 0x2 0x4>,
0747 <0x0 0x3 0x4>,
0748 <0x0 0x4 0x4>,
0749 <0x0 0x5 0x4>,
0750 <0x0 0x6 0x4>,
0751 <0x0 0x7 0x4>;
0752 };
0753
0754 i2cslimpro {
0755 compatible = "apm,xgene-slimpro-i2c";
0756 mboxes = <&mailbox 0>;
0757 };
0758
0759 hwmonslimpro {
0760 compatible = "apm,xgene-slimpro-hwmon";
0761 mboxes = <&mailbox 7>;
0762 };
0763
0764 serial0: serial@1c020000 {
0765 status = "disabled";
0766 device_type = "serial";
0767 compatible = "ns16550a";
0768 reg = <0 0x1c020000 0x0 0x1000>;
0769 reg-shift = <2>;
0770 clock-frequency = <10000000>; /* Updated by bootloader */
0771 interrupt-parent = <&gic>;
0772 interrupts = <0x0 0x4c 0x4>;
0773 };
0774
0775 serial1: serial@1c021000 {
0776 status = "disabled";
0777 device_type = "serial";
0778 compatible = "ns16550a";
0779 reg = <0 0x1c021000 0x0 0x1000>;
0780 reg-shift = <2>;
0781 clock-frequency = <10000000>; /* Updated by bootloader */
0782 interrupt-parent = <&gic>;
0783 interrupts = <0x0 0x4d 0x4>;
0784 };
0785
0786 serial2: serial@1c022000 {
0787 status = "disabled";
0788 device_type = "serial";
0789 compatible = "ns16550a";
0790 reg = <0 0x1c022000 0x0 0x1000>;
0791 reg-shift = <2>;
0792 clock-frequency = <10000000>; /* Updated by bootloader */
0793 interrupt-parent = <&gic>;
0794 interrupts = <0x0 0x4e 0x4>;
0795 };
0796
0797 serial3: serial@1c023000 {
0798 status = "disabled";
0799 device_type = "serial";
0800 compatible = "ns16550a";
0801 reg = <0 0x1c023000 0x0 0x1000>;
0802 reg-shift = <2>;
0803 clock-frequency = <10000000>; /* Updated by bootloader */
0804 interrupt-parent = <&gic>;
0805 interrupts = <0x0 0x4f 0x4>;
0806 };
0807
0808 mmc0: mmc@1c000000 {
0809 compatible = "arasan,sdhci-4.9a";
0810 reg = <0x0 0x1c000000 0x0 0x100>;
0811 interrupts = <0x0 0x49 0x4>;
0812 dma-coherent;
0813 no-1-8-v;
0814 clock-names = "clk_xin", "clk_ahb";
0815 clocks = <&sdioclk 0>, <&ahbclk 0>;
0816 };
0817
0818 gfcgpio: gpio0@1701c000 {
0819 compatible = "apm,xgene-gpio";
0820 reg = <0x0 0x1701c000 0x0 0x40>;
0821 gpio-controller;
0822 #gpio-cells = <2>;
0823 };
0824
0825 dwgpio: gpio@1c024000 {
0826 compatible = "snps,dw-apb-gpio";
0827 reg = <0x0 0x1c024000 0x0 0x1000>;
0828 #address-cells = <1>;
0829 #size-cells = <0>;
0830
0831 porta: gpio-controller@0 {
0832 compatible = "snps,dw-apb-gpio-port";
0833 gpio-controller;
0834 #gpio-cells = <2>;
0835 snps,nr-gpios = <32>;
0836 reg = <0>;
0837 };
0838 };
0839
0840 i2c0: i2c@10512000 {
0841 status = "disabled";
0842 #address-cells = <1>;
0843 #size-cells = <0>;
0844 compatible = "snps,designware-i2c";
0845 reg = <0x0 0x10512000 0x0 0x1000>;
0846 interrupts = <0 0x44 0x4>;
0847 #clock-cells = <1>;
0848 clocks = <&ahbclk 0>;
0849 bus_num = <0>;
0850 };
0851
0852 phy1: phy@1f21a000 {
0853 compatible = "apm,xgene-phy";
0854 reg = <0x0 0x1f21a000 0x0 0x100>;
0855 #phy-cells = <1>;
0856 clocks = <&sataphy1clk 0>;
0857 status = "disabled";
0858 apm,tx-boost-gain = <30 30 30 30 30 30>;
0859 apm,tx-eye-tuning = <2 10 10 2 10 10>;
0860 };
0861
0862 phy2: phy@1f22a000 {
0863 compatible = "apm,xgene-phy";
0864 reg = <0x0 0x1f22a000 0x0 0x100>;
0865 #phy-cells = <1>;
0866 clocks = <&sataphy2clk 0>;
0867 status = "ok";
0868 apm,tx-boost-gain = <30 30 30 30 30 30>;
0869 apm,tx-eye-tuning = <1 10 10 2 10 10>;
0870 };
0871
0872 phy3: phy@1f23a000 {
0873 compatible = "apm,xgene-phy";
0874 reg = <0x0 0x1f23a000 0x0 0x100>;
0875 #phy-cells = <1>;
0876 clocks = <&sataphy3clk 0>;
0877 status = "ok";
0878 apm,tx-boost-gain = <31 31 31 31 31 31>;
0879 apm,tx-eye-tuning = <2 10 10 2 10 10>;
0880 };
0881
0882 sata1: sata@1a000000 {
0883 compatible = "apm,xgene-ahci";
0884 reg = <0x0 0x1a000000 0x0 0x1000>,
0885 <0x0 0x1f210000 0x0 0x1000>,
0886 <0x0 0x1f21d000 0x0 0x1000>,
0887 <0x0 0x1f21e000 0x0 0x1000>,
0888 <0x0 0x1f217000 0x0 0x1000>;
0889 interrupts = <0x0 0x86 0x4>;
0890 dma-coherent;
0891 status = "disabled";
0892 clocks = <&sata01clk 0>;
0893 phys = <&phy1 0>;
0894 phy-names = "sata-phy";
0895 };
0896
0897 sata2: sata@1a400000 {
0898 compatible = "apm,xgene-ahci";
0899 reg = <0x0 0x1a400000 0x0 0x1000>,
0900 <0x0 0x1f220000 0x0 0x1000>,
0901 <0x0 0x1f22d000 0x0 0x1000>,
0902 <0x0 0x1f22e000 0x0 0x1000>,
0903 <0x0 0x1f227000 0x0 0x1000>;
0904 interrupts = <0x0 0x87 0x4>;
0905 dma-coherent;
0906 status = "ok";
0907 clocks = <&sata23clk 0>;
0908 phys = <&phy2 0>;
0909 phy-names = "sata-phy";
0910 };
0911
0912 sata3: sata@1a800000 {
0913 compatible = "apm,xgene-ahci";
0914 reg = <0x0 0x1a800000 0x0 0x1000>,
0915 <0x0 0x1f230000 0x0 0x1000>,
0916 <0x0 0x1f23d000 0x0 0x1000>,
0917 <0x0 0x1f23e000 0x0 0x1000>;
0918 interrupts = <0x0 0x88 0x4>;
0919 dma-coherent;
0920 status = "ok";
0921 clocks = <&sata45clk 0>;
0922 phys = <&phy3 0>;
0923 phy-names = "sata-phy";
0924 };
0925
0926 /* Node-name might need to be coded as dwusb for backward compatibility */
0927 usb0: usb@19000000 {
0928 status = "disabled";
0929 compatible = "snps,dwc3";
0930 reg = <0x0 0x19000000 0x0 0x100000>;
0931 interrupts = <0x0 0x89 0x4>;
0932 dma-coherent;
0933 dr_mode = "host";
0934 };
0935
0936 usb1: usb@19800000 {
0937 status = "disabled";
0938 compatible = "snps,dwc3";
0939 reg = <0x0 0x19800000 0x0 0x100000>;
0940 interrupts = <0x0 0x8a 0x4>;
0941 dma-coherent;
0942 dr_mode = "host";
0943 };
0944
0945 sbgpio: gpio@17001000{
0946 compatible = "apm,xgene-gpio-sb";
0947 reg = <0x0 0x17001000 0x0 0x400>;
0948 #gpio-cells = <2>;
0949 gpio-controller;
0950 interrupts = <0x0 0x28 0x1>,
0951 <0x0 0x29 0x1>,
0952 <0x0 0x2a 0x1>,
0953 <0x0 0x2b 0x1>,
0954 <0x0 0x2c 0x1>,
0955 <0x0 0x2d 0x1>;
0956 interrupt-parent = <&gic>;
0957 #interrupt-cells = <2>;
0958 interrupt-controller;
0959 };
0960
0961 rtc: rtc@10510000 {
0962 compatible = "apm,xgene-rtc";
0963 reg = <0x0 0x10510000 0x0 0x400>;
0964 interrupts = <0x0 0x46 0x4>;
0965 #clock-cells = <1>;
0966 clocks = <&rtcclk 0>;
0967 };
0968
0969 mdio: mdio@17020000 {
0970 compatible = "apm,xgene-mdio-rgmii";
0971 #address-cells = <1>;
0972 #size-cells = <0>;
0973 reg = <0x0 0x17020000 0x0 0xd100>;
0974 clocks = <&menetclk 0>;
0975 };
0976
0977 menet: ethernet@17020000 {
0978 compatible = "apm,xgene-enet";
0979 status = "disabled";
0980 reg = <0x0 0x17020000 0x0 0xd100>,
0981 <0x0 0x17030000 0x0 0xc300>,
0982 <0x0 0x10000000 0x0 0x200>;
0983 reg-names = "enet_csr", "ring_csr", "ring_cmd";
0984 interrupts = <0x0 0x3c 0x4>;
0985 dma-coherent;
0986 clocks = <&menetclk 0>;
0987 /* mac address will be overwritten by the bootloader */
0988 local-mac-address = [00 00 00 00 00 00];
0989 phy-connection-type = "rgmii";
0990 phy-handle = <&menetphy>,<&menet0phy>;
0991 mdio {
0992 compatible = "apm,xgene-mdio";
0993 #address-cells = <1>;
0994 #size-cells = <0>;
0995 menetphy: menetphy@3 {
0996 compatible = "ethernet-phy-id001c.c915";
0997 reg = <0x3>;
0998 };
0999
1000 };
1001 };
1002
1003 sgenet0: ethernet@1f210000 {
1004 compatible = "apm,xgene1-sgenet";
1005 status = "disabled";
1006 reg = <0x0 0x1f210000 0x0 0xd100>,
1007 <0x0 0x1f200000 0x0 0xc300>,
1008 <0x0 0x1b000000 0x0 0x200>;
1009 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1010 interrupts = <0x0 0xa0 0x4>,
1011 <0x0 0xa1 0x4>;
1012 dma-coherent;
1013 clocks = <&sge0clk 0>;
1014 local-mac-address = [00 00 00 00 00 00];
1015 phy-connection-type = "sgmii";
1016 phy-handle = <&sgenet0phy>;
1017 };
1018
1019 sgenet1: ethernet@1f210030 {
1020 compatible = "apm,xgene1-sgenet";
1021 status = "disabled";
1022 reg = <0x0 0x1f210030 0x0 0xd100>,
1023 <0x0 0x1f200000 0x0 0xc300>,
1024 <0x0 0x1b000000 0x0 0x8000>;
1025 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1026 interrupts = <0x0 0xac 0x4>,
1027 <0x0 0xad 0x4>;
1028 port-id = <1>;
1029 dma-coherent;
1030 local-mac-address = [00 00 00 00 00 00];
1031 phy-connection-type = "sgmii";
1032 phy-handle = <&sgenet1phy>;
1033 };
1034
1035 xgenet: ethernet@1f610000 {
1036 compatible = "apm,xgene1-xgenet";
1037 status = "disabled";
1038 reg = <0x0 0x1f610000 0x0 0xd100>,
1039 <0x0 0x1f600000 0x0 0xc300>,
1040 <0x0 0x18000000 0x0 0x200>;
1041 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1042 interrupts = <0x0 0x60 0x4>,
1043 <0x0 0x61 0x4>,
1044 <0x0 0x62 0x4>,
1045 <0x0 0x63 0x4>,
1046 <0x0 0x64 0x4>,
1047 <0x0 0x65 0x4>,
1048 <0x0 0x66 0x4>,
1049 <0x0 0x67 0x4>;
1050 channel = <0>;
1051 dma-coherent;
1052 clocks = <&xge0clk 0>;
1053 /* mac address will be overwritten by the bootloader */
1054 local-mac-address = [00 00 00 00 00 00];
1055 phy-connection-type = "xgmii";
1056 };
1057
1058 xgenet1: ethernet@1f620000 {
1059 compatible = "apm,xgene1-xgenet";
1060 status = "disabled";
1061 reg = <0x0 0x1f620000 0x0 0xd100>,
1062 <0x0 0x1f600000 0x0 0xc300>,
1063 <0x0 0x18000000 0x0 0x8000>;
1064 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1065 interrupts = <0x0 0x6c 0x4>,
1066 <0x0 0x6d 0x4>;
1067 port-id = <1>;
1068 dma-coherent;
1069 clocks = <&xge1clk 0>;
1070 /* mac address will be overwritten by the bootloader */
1071 local-mac-address = [00 00 00 00 00 00];
1072 phy-connection-type = "xgmii";
1073 };
1074
1075 rng: rng@10520000 {
1076 compatible = "apm,xgene-rng";
1077 reg = <0x0 0x10520000 0x0 0x100>;
1078 interrupts = <0x0 0x41 0x4>;
1079 clocks = <&rngpkaclk 0>;
1080 };
1081
1082 dma: dma@1f270000 {
1083 compatible = "apm,xgene-storm-dma";
1084 device_type = "dma";
1085 reg = <0x0 0x1f270000 0x0 0x10000>,
1086 <0x0 0x1f200000 0x0 0x10000>,
1087 <0x0 0x1b000000 0x0 0x400000>,
1088 <0x0 0x1054a000 0x0 0x100>;
1089 interrupts = <0x0 0x82 0x4>,
1090 <0x0 0xb8 0x4>,
1091 <0x0 0xb9 0x4>,
1092 <0x0 0xba 0x4>,
1093 <0x0 0xbb 0x4>;
1094 dma-coherent;
1095 clocks = <&dmaclk 0>;
1096 };
1097 };
1098 };
