0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
0004 *
0005 * Copyright (C) 2015, Applied Micro Circuits Corporation
0006 */
0007
0008 / {
0009 compatible = "apm,xgene-shadowcat";
0010 interrupt-parent = <&gic>;
0011 #address-cells = <2>;
0012 #size-cells = <2>;
0013
0014 cpus {
0015 #address-cells = <2>;
0016 #size-cells = <0>;
0017
0018 cpu@0 {
0019 device_type = "cpu";
0020 compatible = "apm,strega";
0021 reg = <0x0 0x000>;
0022 enable-method = "spin-table";
0023 cpu-release-addr = <0x1 0x0000fff8>;
0024 next-level-cache = <&xgene_L2_0>;
0025 #clock-cells = <1>;
0026 clocks = <&pmd0clk 0>;
0027 };
0028 cpu@1 {
0029 device_type = "cpu";
0030 compatible = "apm,strega";
0031 reg = <0x0 0x001>;
0032 enable-method = "spin-table";
0033 cpu-release-addr = <0x1 0x0000fff8>;
0034 next-level-cache = <&xgene_L2_0>;
0035 #clock-cells = <1>;
0036 clocks = <&pmd0clk 0>;
0037 };
0038 cpu@100 {
0039 device_type = "cpu";
0040 compatible = "apm,strega";
0041 reg = <0x0 0x100>;
0042 enable-method = "spin-table";
0043 cpu-release-addr = <0x1 0x0000fff8>;
0044 next-level-cache = <&xgene_L2_1>;
0045 #clock-cells = <1>;
0046 clocks = <&pmd1clk 0>;
0047 };
0048 cpu@101 {
0049 device_type = "cpu";
0050 compatible = "apm,strega";
0051 reg = <0x0 0x101>;
0052 enable-method = "spin-table";
0053 cpu-release-addr = <0x1 0x0000fff8>;
0054 next-level-cache = <&xgene_L2_1>;
0055 #clock-cells = <1>;
0056 clocks = <&pmd1clk 0>;
0057 };
0058 cpu@200 {
0059 device_type = "cpu";
0060 compatible = "apm,strega";
0061 reg = <0x0 0x200>;
0062 enable-method = "spin-table";
0063 cpu-release-addr = <0x1 0x0000fff8>;
0064 next-level-cache = <&xgene_L2_2>;
0065 #clock-cells = <1>;
0066 clocks = <&pmd2clk 0>;
0067 };
0068 cpu@201 {
0069 device_type = "cpu";
0070 compatible = "apm,strega";
0071 reg = <0x0 0x201>;
0072 enable-method = "spin-table";
0073 cpu-release-addr = <0x1 0x0000fff8>;
0074 next-level-cache = <&xgene_L2_2>;
0075 #clock-cells = <1>;
0076 clocks = <&pmd2clk 0>;
0077 };
0078 cpu@300 {
0079 device_type = "cpu";
0080 compatible = "apm,strega";
0081 reg = <0x0 0x300>;
0082 enable-method = "spin-table";
0083 cpu-release-addr = <0x1 0x0000fff8>;
0084 next-level-cache = <&xgene_L2_3>;
0085 #clock-cells = <1>;
0086 clocks = <&pmd3clk 0>;
0087 };
0088 cpu@301 {
0089 device_type = "cpu";
0090 compatible = "apm,strega";
0091 reg = <0x0 0x301>;
0092 enable-method = "spin-table";
0093 cpu-release-addr = <0x1 0x0000fff8>;
0094 next-level-cache = <&xgene_L2_3>;
0095 #clock-cells = <1>;
0096 clocks = <&pmd3clk 0>;
0097 };
0098 xgene_L2_0: l2-cache-0 {
0099 compatible = "cache";
0100 };
0101 xgene_L2_1: l2-cache-1 {
0102 compatible = "cache";
0103 };
0104 xgene_L2_2: l2-cache-2 {
0105 compatible = "cache";
0106 };
0107 xgene_L2_3: l2-cache-3 {
0108 compatible = "cache";
0109 };
0110 };
0111
0112 gic: interrupt-controller@78090000 {
0113 compatible = "arm,cortex-a15-gic";
0114 #interrupt-cells = <3>;
0115 #address-cells = <2>;
0116 #size-cells = <2>;
0117 interrupt-controller;
0118 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
0119 ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
0120 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
0121 <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
0122 <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
0123 <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
0124 v2m0: v2m@0 {
0125 compatible = "arm,gic-v2m-frame";
0126 msi-controller;
0127 reg = <0x0 0x0 0x0 0x1000>;
0128 };
0129 v2m1: v2m@10000 {
0130 compatible = "arm,gic-v2m-frame";
0131 msi-controller;
0132 reg = <0x0 0x10000 0x0 0x1000>;
0133 };
0134 v2m2: v2m@20000 {
0135 compatible = "arm,gic-v2m-frame";
0136 msi-controller;
0137 reg = <0x0 0x20000 0x0 0x1000>;
0138 };
0139 v2m3: v2m@30000 {
0140 compatible = "arm,gic-v2m-frame";
0141 msi-controller;
0142 reg = <0x0 0x30000 0x0 0x1000>;
0143 };
0144 v2m4: v2m@40000 {
0145 compatible = "arm,gic-v2m-frame";
0146 msi-controller;
0147 reg = <0x0 0x40000 0x0 0x1000>;
0148 };
0149 v2m5: v2m@50000 {
0150 compatible = "arm,gic-v2m-frame";
0151 msi-controller;
0152 reg = <0x0 0x50000 0x0 0x1000>;
0153 };
0154 v2m6: v2m@60000 {
0155 compatible = "arm,gic-v2m-frame";
0156 msi-controller;
0157 reg = <0x0 0x60000 0x0 0x1000>;
0158 };
0159 v2m7: v2m@70000 {
0160 compatible = "arm,gic-v2m-frame";
0161 msi-controller;
0162 reg = <0x0 0x70000 0x0 0x1000>;
0163 };
0164 v2m8: v2m@80000 {
0165 compatible = "arm,gic-v2m-frame";
0166 msi-controller;
0167 reg = <0x0 0x80000 0x0 0x1000>;
0168 };
0169 v2m9: v2m@90000 {
0170 compatible = "arm,gic-v2m-frame";
0171 msi-controller;
0172 reg = <0x0 0x90000 0x0 0x1000>;
0173 };
0174 v2m10: v2m@a0000 {
0175 compatible = "arm,gic-v2m-frame";
0176 msi-controller;
0177 reg = <0x0 0xa0000 0x0 0x1000>;
0178 };
0179 v2m11: v2m@b0000 {
0180 compatible = "arm,gic-v2m-frame";
0181 msi-controller;
0182 reg = <0x0 0xb0000 0x0 0x1000>;
0183 };
0184 v2m12: v2m@c0000 {
0185 compatible = "arm,gic-v2m-frame";
0186 msi-controller;
0187 reg = <0x0 0xc0000 0x0 0x1000>;
0188 };
0189 v2m13: v2m@d0000 {
0190 compatible = "arm,gic-v2m-frame";
0191 msi-controller;
0192 reg = <0x0 0xd0000 0x0 0x1000>;
0193 };
0194 v2m14: v2m@e0000 {
0195 compatible = "arm,gic-v2m-frame";
0196 msi-controller;
0197 reg = <0x0 0xe0000 0x0 0x1000>;
0198 };
0199 v2m15: v2m@f0000 {
0200 compatible = "arm,gic-v2m-frame";
0201 msi-controller;
0202 reg = <0x0 0xf0000 0x0 0x1000>;
0203 };
0204 };
0205
0206 pmu {
0207 compatible = "arm,armv8-pmuv3";
0208 interrupts = <1 12 0xff04>;
0209 };
0210
0211 timer {
0212 compatible = "arm,armv8-timer";
0213 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
0214 <1 13 0xff08>, /* Non-secure Phys IRQ */
0215 <1 14 0xff08>, /* Virt IRQ */
0216 <1 15 0xff08>; /* Hyp IRQ */
0217 clock-frequency = <50000000>;
0218 };
0219
0220 soc {
0221 compatible = "simple-bus";
0222 #address-cells = <2>;
0223 #size-cells = <2>;
0224 ranges;
0225
0226 clocks {
0227 #address-cells = <2>;
0228 #size-cells = <2>;
0229 ranges;
0230
0231 refclk: refclk {
0232 compatible = "fixed-clock";
0233 #clock-cells = <1>;
0234 clock-frequency = <100000000>;
0235 clock-output-names = "refclk";
0236 };
0237
0238 pmdpll: pmdpll@170000f0 {
0239 compatible = "apm,xgene-pcppll-v2-clock";
0240 #clock-cells = <1>;
0241 clocks = <&refclk 0>;
0242 reg = <0x0 0x170000f0 0x0 0x10>;
0243 clock-output-names = "pmdpll";
0244 };
0245
0246 pmd0clk: pmd0clk@7e200200 {
0247 compatible = "apm,xgene-pmd-clock";
0248 #clock-cells = <1>;
0249 clocks = <&pmdpll 0>;
0250 reg = <0x0 0x7e200200 0x0 0x10>;
0251 clock-output-names = "pmd0clk";
0252 };
0253
0254 pmd1clk: pmd1clk@7e200210 {
0255 compatible = "apm,xgene-pmd-clock";
0256 #clock-cells = <1>;
0257 clocks = <&pmdpll 0>;
0258 reg = <0x0 0x7e200210 0x0 0x10>;
0259 clock-output-names = "pmd1clk";
0260 };
0261
0262 pmd2clk: pmd2clk@7e200220 {
0263 compatible = "apm,xgene-pmd-clock";
0264 #clock-cells = <1>;
0265 clocks = <&pmdpll 0>;
0266 reg = <0x0 0x7e200220 0x0 0x10>;
0267 clock-output-names = "pmd2clk";
0268 };
0269
0270 pmd3clk: pmd3clk@7e200230 {
0271 compatible = "apm,xgene-pmd-clock";
0272 #clock-cells = <1>;
0273 clocks = <&pmdpll 0>;
0274 reg = <0x0 0x7e200230 0x0 0x10>;
0275 clock-output-names = "pmd3clk";
0276 };
0277
0278 socpll: socpll@17000120 {
0279 compatible = "apm,xgene-socpll-v2-clock";
0280 #clock-cells = <1>;
0281 clocks = <&refclk 0>;
0282 reg = <0x0 0x17000120 0x0 0x1000>;
0283 clock-output-names = "socpll";
0284 };
0285
0286 socplldiv2: socplldiv2 {
0287 compatible = "fixed-factor-clock";
0288 #clock-cells = <1>;
0289 clocks = <&socpll 0>;
0290 clock-mult = <1>;
0291 clock-div = <2>;
0292 clock-output-names = "socplldiv2";
0293 };
0294
0295 ahbclk: ahbclk@17000000 {
0296 compatible = "apm,xgene-device-clock";
0297 #clock-cells = <1>;
0298 clocks = <&socplldiv2 0>;
0299 reg = <0x0 0x17000000 0x0 0x2000>;
0300 reg-names = "div-reg";
0301 divider-offset = <0x164>;
0302 divider-width = <0x5>;
0303 divider-shift = <0x0>;
0304 clock-output-names = "ahbclk";
0305 };
0306
0307 sbapbclk: sbapbclk@1704c000 {
0308 compatible = "apm,xgene-device-clock";
0309 #clock-cells = <1>;
0310 clocks = <&ahbclk 0>;
0311 reg = <0x0 0x1704c000 0x0 0x2000>;
0312 reg-names = "div-reg";
0313 divider-offset = <0x10>;
0314 divider-width = <0x2>;
0315 divider-shift = <0x0>;
0316 clock-output-names = "sbapbclk";
0317 };
0318
0319 sdioclk: sdioclk@1f2ac000 {
0320 compatible = "apm,xgene-device-clock";
0321 #clock-cells = <1>;
0322 clocks = <&socplldiv2 0>;
0323 reg = <0x0 0x1f2ac000 0x0 0x1000
0324 0x0 0x17000000 0x0 0x2000>;
0325 reg-names = "csr-reg", "div-reg";
0326 csr-offset = <0x0>;
0327 csr-mask = <0x2>;
0328 enable-offset = <0x8>;
0329 enable-mask = <0x2>;
0330 divider-offset = <0x178>;
0331 divider-width = <0x8>;
0332 divider-shift = <0x0>;
0333 clock-output-names = "sdioclk";
0334 };
0335
0336 pcie0clk: pcie0clk@1f2bc000 {
0337 compatible = "apm,xgene-device-clock";
0338 #clock-cells = <1>;
0339 clocks = <&socplldiv2 0>;
0340 reg = <0x0 0x1f2bc000 0x0 0x1000>;
0341 reg-names = "csr-reg";
0342 clock-output-names = "pcie0clk";
0343 };
0344
0345 pcie1clk: pcie1clk@1f2cc000 {
0346 compatible = "apm,xgene-device-clock";
0347 #clock-cells = <1>;
0348 clocks = <&socplldiv2 0>;
0349 reg = <0x0 0x1f2cc000 0x0 0x1000>;
0350 reg-names = "csr-reg";
0351 clock-output-names = "pcie1clk";
0352 };
0353
0354 xge0clk: xge0clk@1f61c000 {
0355 compatible = "apm,xgene-device-clock";
0356 #clock-cells = <1>;
0357 clocks = <&socplldiv2 0>;
0358 reg = <0x0 0x1f61c000 0x0 0x1000>;
0359 reg-names = "csr-reg";
0360 enable-mask = <0x3>;
0361 csr-mask = <0x3>;
0362 clock-output-names = "xge0clk";
0363 };
0364
0365 xge1clk: xge1clk@1f62c000 {
0366 compatible = "apm,xgene-device-clock";
0367 #clock-cells = <1>;
0368 clocks = <&socplldiv2 0>;
0369 reg = <0x0 0x1f62c000 0x0 0x1000>;
0370 reg-names = "csr-reg";
0371 enable-mask = <0x3>;
0372 csr-mask = <0x3>;
0373 clock-output-names = "xge1clk";
0374 };
0375
0376 rngpkaclk: rngpkaclk@17000000 {
0377 compatible = "apm,xgene-device-clock";
0378 #clock-cells = <1>;
0379 clocks = <&socplldiv2 0>;
0380 reg = <0x0 0x17000000 0x0 0x2000>;
0381 reg-names = "csr-reg";
0382 csr-offset = <0xc>;
0383 csr-mask = <0x10>;
0384 enable-offset = <0x10>;
0385 enable-mask = <0x10>;
0386 clock-output-names = "rngpkaclk";
0387 };
0388
0389 i2c4clk: i2c4clk@1704c000 {
0390 compatible = "apm,xgene-device-clock";
0391 #clock-cells = <1>;
0392 clocks = <&sbapbclk 0>;
0393 reg = <0x0 0x1704c000 0x0 0x1000>;
0394 reg-names = "csr-reg";
0395 csr-offset = <0x0>;
0396 csr-mask = <0x40>;
0397 enable-offset = <0x8>;
0398 enable-mask = <0x40>;
0399 clock-output-names = "i2c4clk";
0400 };
0401 };
0402
0403 scu: system-clk-controller@17000000 {
0404 compatible = "apm,xgene-scu","syscon";
0405 reg = <0x0 0x17000000 0x0 0x400>;
0406 };
0407
0408 reboot: reboot@17000014 {
0409 compatible = "syscon-reboot";
0410 regmap = <&scu>;
0411 offset = <0x14>;
0412 mask = <0x1>;
0413 };
0414
0415 csw: csw@7e200000 {
0416 compatible = "apm,xgene-csw", "syscon";
0417 reg = <0x0 0x7e200000 0x0 0x1000>;
0418 };
0419
0420 mcba: mcba@7e700000 {
0421 compatible = "apm,xgene-mcb", "syscon";
0422 reg = <0x0 0x7e700000 0x0 0x1000>;
0423 };
0424
0425 mcbb: mcbb@7e720000 {
0426 compatible = "apm,xgene-mcb", "syscon";
0427 reg = <0x0 0x7e720000 0x0 0x1000>;
0428 };
0429
0430 efuse: efuse@1054a000 {
0431 compatible = "apm,xgene-efuse", "syscon";
0432 reg = <0x0 0x1054a000 0x0 0x20>;
0433 };
0434
0435 edac@78800000 {
0436 compatible = "apm,xgene-edac";
0437 #address-cells = <2>;
0438 #size-cells = <2>;
0439 ranges;
0440 regmap-csw = <&csw>;
0441 regmap-mcba = <&mcba>;
0442 regmap-mcbb = <&mcbb>;
0443 regmap-efuse = <&efuse>;
0444 reg = <0x0 0x78800000 0x0 0x100>;
0445 interrupts = <0x0 0x20 0x4>,
0446 <0x0 0x21 0x4>,
0447 <0x0 0x27 0x4>;
0448
0449 edacmc@7e800000 {
0450 compatible = "apm,xgene-edac-mc";
0451 reg = <0x0 0x7e800000 0x0 0x1000>;
0452 memory-controller = <0>;
0453 };
0454
0455 edacmc@7e840000 {
0456 compatible = "apm,xgene-edac-mc";
0457 reg = <0x0 0x7e840000 0x0 0x1000>;
0458 memory-controller = <1>;
0459 };
0460
0461 edacmc@7e880000 {
0462 compatible = "apm,xgene-edac-mc";
0463 reg = <0x0 0x7e880000 0x0 0x1000>;
0464 memory-controller = <2>;
0465 };
0466
0467 edacmc@7e8c0000 {
0468 compatible = "apm,xgene-edac-mc";
0469 reg = <0x0 0x7e8c0000 0x0 0x1000>;
0470 memory-controller = <3>;
0471 };
0472
0473 edacpmd@7c000000 {
0474 compatible = "apm,xgene-edac-pmd";
0475 reg = <0x0 0x7c000000 0x0 0x200000>;
0476 pmd-controller = <0>;
0477 };
0478
0479 edacpmd@7c200000 {
0480 compatible = "apm,xgene-edac-pmd";
0481 reg = <0x0 0x7c200000 0x0 0x200000>;
0482 pmd-controller = <1>;
0483 };
0484
0485 edacpmd@7c400000 {
0486 compatible = "apm,xgene-edac-pmd";
0487 reg = <0x0 0x7c400000 0x0 0x200000>;
0488 pmd-controller = <2>;
0489 };
0490
0491 edacpmd@7c600000 {
0492 compatible = "apm,xgene-edac-pmd";
0493 reg = <0x0 0x7c600000 0x0 0x200000>;
0494 pmd-controller = <3>;
0495 };
0496
0497 edacl3@7e600000 {
0498 compatible = "apm,xgene-edac-l3-v2";
0499 reg = <0x0 0x7e600000 0x0 0x1000>;
0500 };
0501
0502 edacsoc@7e930000 {
0503 compatible = "apm,xgene-edac-soc";
0504 reg = <0x0 0x7e930000 0x0 0x1000>;
0505 };
0506 };
0507
0508 pmu: pmu@78810000 {
0509 compatible = "apm,xgene-pmu-v2";
0510 #address-cells = <2>;
0511 #size-cells = <2>;
0512 ranges;
0513 regmap-csw = <&csw>;
0514 regmap-mcba = <&mcba>;
0515 regmap-mcbb = <&mcbb>;
0516 reg = <0x0 0x78810000 0x0 0x1000>;
0517 interrupts = <0x0 0x22 0x4>;
0518
0519 pmul3c@7e610000 {
0520 compatible = "apm,xgene-pmu-l3c";
0521 reg = <0x0 0x7e610000 0x0 0x1000>;
0522 };
0523
0524 pmuiob@7e940000 {
0525 compatible = "apm,xgene-pmu-iob";
0526 reg = <0x0 0x7e940000 0x0 0x1000>;
0527 };
0528
0529 pmucmcb@7e710000 {
0530 compatible = "apm,xgene-pmu-mcb";
0531 reg = <0x0 0x7e710000 0x0 0x1000>;
0532 enable-bit-index = <0>;
0533 };
0534
0535 pmucmcb@7e730000 {
0536 compatible = "apm,xgene-pmu-mcb";
0537 reg = <0x0 0x7e730000 0x0 0x1000>;
0538 enable-bit-index = <1>;
0539 };
0540
0541 pmucmc@7e810000 {
0542 compatible = "apm,xgene-pmu-mc";
0543 reg = <0x0 0x7e810000 0x0 0x1000>;
0544 enable-bit-index = <0>;
0545 };
0546
0547 pmucmc@7e850000 {
0548 compatible = "apm,xgene-pmu-mc";
0549 reg = <0x0 0x7e850000 0x0 0x1000>;
0550 enable-bit-index = <1>;
0551 };
0552
0553 pmucmc@7e890000 {
0554 compatible = "apm,xgene-pmu-mc";
0555 reg = <0x0 0x7e890000 0x0 0x1000>;
0556 enable-bit-index = <2>;
0557 };
0558
0559 pmucmc@7e8d0000 {
0560 compatible = "apm,xgene-pmu-mc";
0561 reg = <0x0 0x7e8d0000 0x0 0x1000>;
0562 enable-bit-index = <3>;
0563 };
0564 };
0565
0566 mailbox: mailbox@10540000 {
0567 compatible = "apm,xgene-slimpro-mbox";
0568 reg = <0x0 0x10540000 0x0 0x8000>;
0569 #mbox-cells = <1>;
0570 interrupts = <0x0 0x0 0x4
0571 0x0 0x1 0x4
0572 0x0 0x2 0x4
0573 0x0 0x3 0x4
0574 0x0 0x4 0x4
0575 0x0 0x5 0x4
0576 0x0 0x6 0x4
0577 0x0 0x7 0x4>;
0578 };
0579
0580 i2cslimpro {
0581 compatible = "apm,xgene-slimpro-i2c";
0582 mboxes = <&mailbox 0>;
0583 };
0584
0585 hwmonslimpro {
0586 compatible = "apm,xgene-slimpro-hwmon";
0587 mboxes = <&mailbox 7>;
0588 };
0589
0590 serial0: serial@10600000 {
0591 device_type = "serial";
0592 compatible = "ns16550";
0593 reg = <0 0x10600000 0x0 0x1000>;
0594 reg-shift = <2>;
0595 clock-frequency = <10000000>;
0596 interrupt-parent = <&gic>;
0597 interrupts = <0x0 0x4c 0x4>;
0598 };
0599
0600 /* Node-name might need to be coded as dwusb for backward compatibility */
0601 usb0: usb@19000000 {
0602 status = "disabled";
0603 compatible = "snps,dwc3";
0604 reg = <0x0 0x19000000 0x0 0x100000>;
0605 interrupts = <0x0 0x5d 0x4>;
0606 dma-coherent;
0607 dr_mode = "host";
0608 };
0609
0610 pcie0: pcie@1f2b0000 {
0611 status = "disabled";
0612 device_type = "pci";
0613 compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
0614 #interrupt-cells = <1>;
0615 #size-cells = <2>;
0616 #address-cells = <3>;
0617 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
0618 0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */
0619 reg-names = "csr", "cfg";
0620 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
0621 0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */
0622 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */
0623 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0624 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
0625 bus-range = <0x00 0xff>;
0626 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0627 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4
0628 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4
0629 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x4
0630 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x4>;
0631 dma-coherent;
0632 clocks = <&pcie0clk 0>;
0633 msi-parent = <&v2m0>;
0634 };
0635
0636 pcie1: pcie@1f2c0000 {
0637 status = "disabled";
0638 device_type = "pci";
0639 compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
0640 #interrupt-cells = <1>;
0641 #size-cells = <2>;
0642 #address-cells = <3>;
0643 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
0644 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
0645 reg-names = "csr", "cfg";
0646 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
0647 0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */
0648 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
0649 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0650 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
0651 bus-range = <0x00 0xff>;
0652 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0653 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4
0654 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4
0655 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x4
0656 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x4>;
0657 dma-coherent;
0658 clocks = <&pcie1clk 0>;
0659 msi-parent = <&v2m0>;
0660 };
0661
0662 sata1: sata@1a000000 {
0663 compatible = "apm,xgene-ahci-v2";
0664 reg = <0x0 0x1a000000 0x0 0x1000>,
0665 <0x0 0x1f200000 0x0 0x1000>,
0666 <0x0 0x1f20d000 0x0 0x1000>,
0667 <0x0 0x1f20e000 0x0 0x1000>;
0668 interrupts = <0x0 0x5a 0x4>;
0669 dma-coherent;
0670 };
0671
0672 sata2: sata@1a200000 {
0673 compatible = "apm,xgene-ahci-v2";
0674 reg = <0x0 0x1a200000 0x0 0x1000>,
0675 <0x0 0x1f210000 0x0 0x1000>,
0676 <0x0 0x1f21d000 0x0 0x1000>,
0677 <0x0 0x1f21e000 0x0 0x1000>;
0678 interrupts = <0x0 0x5b 0x4>;
0679 dma-coherent;
0680 };
0681
0682 sata3: sata@1a400000 {
0683 compatible = "apm,xgene-ahci-v2";
0684 reg = <0x0 0x1a400000 0x0 0x1000>,
0685 <0x0 0x1f220000 0x0 0x1000>,
0686 <0x0 0x1f22d000 0x0 0x1000>,
0687 <0x0 0x1f22e000 0x0 0x1000>;
0688 interrupts = <0x0 0x5c 0x4>;
0689 dma-coherent;
0690 };
0691
0692 mmc0: mmc@1c000000 {
0693 compatible = "arasan,sdhci-4.9a";
0694 reg = <0x0 0x1c000000 0x0 0x100>;
0695 interrupts = <0x0 0x49 0x4>;
0696 dma-coherent;
0697 no-1-8-v;
0698 clock-names = "clk_xin", "clk_ahb";
0699 clocks = <&sdioclk 0>, <&ahbclk 0>;
0700 };
0701
0702 gfcgpio: gpio@1f63c000 {
0703 compatible = "apm,xgene-gpio";
0704 reg = <0x0 0x1f63c000 0x0 0x40>;
0705 gpio-controller;
0706 #gpio-cells = <2>;
0707 };
0708
0709 dwgpio: gpio@1c024000 {
0710 compatible = "snps,dw-apb-gpio";
0711 reg = <0x0 0x1c024000 0x0 0x1000>;
0712 #address-cells = <1>;
0713 #size-cells = <0>;
0714
0715 porta: gpio-controller@0 {
0716 compatible = "snps,dw-apb-gpio-port";
0717 gpio-controller;
0718 #gpio-cells = <2>;
0719 snps,nr-gpios = <32>;
0720 reg = <0>;
0721 };
0722 };
0723
0724 sbgpio: gpio@17001000{
0725 compatible = "apm,xgene-gpio-sb";
0726 reg = <0x0 0x17001000 0x0 0x400>;
0727 #gpio-cells = <2>;
0728 gpio-controller;
0729 interrupts = <0x0 0x28 0x1>,
0730 <0x0 0x29 0x1>,
0731 <0x0 0x2a 0x1>,
0732 <0x0 0x2b 0x1>,
0733 <0x0 0x2c 0x1>,
0734 <0x0 0x2d 0x1>,
0735 <0x0 0x2e 0x1>,
0736 <0x0 0x2f 0x1>;
0737 interrupt-parent = <&gic>;
0738 #interrupt-cells = <2>;
0739 interrupt-controller;
0740 apm,nr-gpios = <22>;
0741 apm,nr-irqs = <8>;
0742 apm,irq-start = <8>;
0743 };
0744
0745 mdio: mdio@1f610000 {
0746 compatible = "apm,xgene-mdio-xfi";
0747 #address-cells = <1>;
0748 #size-cells = <0>;
0749 reg = <0x0 0x1f610000 0x0 0xd100>;
0750 clocks = <&xge0clk 0>;
0751 };
0752
0753 sgenet0: ethernet@1f610000 {
0754 compatible = "apm,xgene2-sgenet";
0755 status = "disabled";
0756 reg = <0x0 0x1f610000 0x0 0xd100>,
0757 <0x0 0x1f600000 0x0 0xd100>,
0758 <0x0 0x20000000 0x0 0x20000>;
0759 interrupts = <0 96 4>,
0760 <0 97 4>;
0761 dma-coherent;
0762 clocks = <&xge0clk 0>;
0763 local-mac-address = [00 01 73 00 00 01];
0764 phy-connection-type = "sgmii";
0765 phy-handle = <&sgenet0phy>;
0766 };
0767
0768 xgenet1: ethernet@1f620000 {
0769 compatible = "apm,xgene2-xgenet";
0770 status = "disabled";
0771 reg = <0x0 0x1f620000 0x0 0x10000>,
0772 <0x0 0x1f600000 0x0 0xd100>,
0773 <0x0 0x20000000 0x0 0x220000>;
0774 interrupts = <0 108 4>,
0775 <0 109 4>,
0776 <0 110 4>,
0777 <0 111 4>,
0778 <0 112 4>,
0779 <0 113 4>,
0780 <0 114 4>,
0781 <0 115 4>;
0782 channel = <12>;
0783 port-id = <1>;
0784 dma-coherent;
0785 clocks = <&xge1clk 0>;
0786 local-mac-address = [00 01 73 00 00 02];
0787 phy-connection-type = "xgmii";
0788 };
0789
0790 rng: rng@10520000 {
0791 compatible = "apm,xgene-rng";
0792 reg = <0x0 0x10520000 0x0 0x100>;
0793 interrupts = <0x0 0x41 0x4>;
0794 clocks = <&rngpkaclk 0>;
0795 };
0796
0797 i2c1: i2c@10511000 {
0798 #address-cells = <1>;
0799 #size-cells = <0>;
0800 compatible = "snps,designware-i2c";
0801 reg = <0x0 0x10511000 0x0 0x1000>;
0802 interrupts = <0 0x45 0x4>;
0803 #clock-cells = <1>;
0804 clocks = <&sbapbclk 0>;
0805 bus_num = <1>;
0806 };
0807
0808 i2c4: i2c@10640000 {
0809 #address-cells = <1>;
0810 #size-cells = <0>;
0811 compatible = "snps,designware-i2c";
0812 reg = <0x0 0x10640000 0x0 0x1000>;
0813 interrupts = <0 0x3a 0x4>;
0814 clocks = <&i2c4clk 0>;
0815 bus_num = <4>;
0816 };
0817 };
0818 };
