0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2019 BayLibre, SAS
0004 * Author: Neil Armstrong <narmstrong@baylibre.com>
0005 */
0006
0007 /dts-v1/;
0008
0009 #include "meson-sm1.dtsi"
0010 #include "meson-khadas-vim3.dtsi"
0011 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
0012
0013 / {
0014 compatible = "khadas,vim3l", "amlogic,sm1";
0015 model = "Khadas VIM3L";
0016
0017 vddcpu: regulator-vddcpu {
0018 /*
0019 * Silergy SY8030DEC Regulator.
0020 */
0021 compatible = "pwm-regulator";
0022
0023 regulator-name = "VDDCPU";
0024 regulator-min-microvolt = <690000>;
0025 regulator-max-microvolt = <1050000>;
0026
0027 pwm-supply = <&vsys_3v3>;
0028
0029 pwms = <&pwm_AO_cd 1 1250 0>;
0030 pwm-dutycycle-range = <100 0>;
0031
0032 regulator-boot-on;
0033 regulator-always-on;
0034 };
0035
0036 sound {
0037 model = "G12B-KHADAS-VIM3L";
0038 audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
0039 "TDMOUT_A IN 1", "FRDDR_B OUT 0",
0040 "TDMOUT_A IN 2", "FRDDR_C OUT 0",
0041 "TDM_A Playback", "TDMOUT_A OUT",
0042 "TDMIN_A IN 0", "TDM_A Capture",
0043 "TDMIN_A IN 13", "TDM_A Loopback",
0044 "TODDR_A IN 0", "TDMIN_A OUT",
0045 "TODDR_B IN 0", "TDMIN_A OUT",
0046 "TODDR_C IN 0", "TDMIN_A OUT";
0047 };
0048 };
0049
0050 &cpu0 {
0051 cpu-supply = <&vddcpu>;
0052 operating-points-v2 = <&cpu_opp_table>;
0053 clocks = <&clkc CLKID_CPU_CLK>;
0054 clock-latency = <50000>;
0055 };
0056
0057 &cpu1 {
0058 cpu-supply = <&vddcpu>;
0059 operating-points-v2 = <&cpu_opp_table>;
0060 clocks = <&clkc CLKID_CPU1_CLK>;
0061 clock-latency = <50000>;
0062 };
0063
0064 &cpu2 {
0065 cpu-supply = <&vddcpu>;
0066 operating-points-v2 = <&cpu_opp_table>;
0067 clocks = <&clkc CLKID_CPU2_CLK>;
0068 clock-latency = <50000>;
0069 };
0070
0071 &cpu3 {
0072 cpu-supply = <&vddcpu>;
0073 operating-points-v2 = <&cpu_opp_table>;
0074 clocks = <&clkc CLKID_CPU3_CLK>;
0075 clock-latency = <50000>;
0076 };
0077
0078 &pwm_AO_cd {
0079 pinctrl-0 = <&pwm_ao_d_e_pins>;
0080 pinctrl-names = "default";
0081 clocks = <&xtal>;
0082 clock-names = "clkin1";
0083 status = "okay";
0084 };
0085
0086 /*
0087 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
0088 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
0089 * an USB3.0 Type A connector and a M.2 Key M slot.
0090 * The PHY driving these differential lines is shared between
0091 * the USB3.0 controller and the PCIe Controller, thus only
0092 * a single controller can use it.
0093 * If the MCU is configured to mux the PCIe/USB3.0 differential lines
0094 * to the M.2 Key M slot, uncomment the following block to disable
0095 * USB3.0 from the USB Complex and enable the PCIe controller.
0096 * The End User is not expected to uncomment the following except for
0097 * testing purposes, but instead rely on the firmware/bootloader to
0098 * update these nodes accordingly if PCIe mode is selected by the MCU.
0099 */
0100 /*
0101 &pcie {
0102 status = "okay";
0103 };
0104
0105 &usb {
0106 phys = <&usb2_phy0>, <&usb2_phy1>;
0107 phy-names = "usb2-phy0", "usb2-phy1";
0108 };
0109 */
0110
0111 &sd_emmc_a {
0112 sd-uhs-sdr50;
0113 };
