0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/irq.h>
0007 #include <dt-bindings/interrupt-controller/arm-gic.h>
0008 #include <dt-bindings/gpio/gpio.h>
0009
0010 / {
0011 cpus {
0012 #address-cells = <2>;
0013 #size-cells = <0>;
0014
0015 cpu0: cpu@0 {
0016 device_type = "cpu";
0017 compatible = "arm,cortex-a35";
0018 reg = <0x0 0x0>;
0019 enable-method = "psci";
0020 };
0021
0022 cpu1: cpu@1 {
0023 device_type = "cpu";
0024 compatible = "arm,cortex-a35";
0025 reg = <0x0 0x1>;
0026 enable-method = "psci";
0027 };
0028
0029 cpu2: cpu@2 {
0030 device_type = "cpu";
0031 compatible = "arm,cortex-a35";
0032 reg = <0x0 0x2>;
0033 enable-method = "psci";
0034 };
0035
0036 cpu3: cpu@3 {
0037 device_type = "cpu";
0038 compatible = "arm,cortex-a35";
0039 reg = <0x0 0x3>;
0040 enable-method = "psci";
0041 };
0042 };
0043
0044 timer {
0045 compatible = "arm,armv8-timer";
0046 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0047 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0048 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0049 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0050 };
0051
0052 psci {
0053 compatible = "arm,psci-1.0";
0054 method = "smc";
0055 };
0056
0057 xtal: xtal-clk {
0058 compatible = "fixed-clock";
0059 clock-frequency = <24000000>;
0060 clock-output-names = "xtal";
0061 #clock-cells = <0>;
0062 };
0063
0064 pwrc: power-controller {
0065 compatible = "amlogic,meson-s4-pwrc";
0066 #power-domain-cells = <1>;
0067 status = "okay";
0068 };
0069
0070 soc {
0071 compatible = "simple-bus";
0072 #address-cells = <2>;
0073 #size-cells = <2>;
0074 ranges;
0075
0076 gic: interrupt-controller@fff01000 {
0077 compatible = "arm,gic-400";
0078 #interrupt-cells = <3>;
0079 #address-cells = <0>;
0080 interrupt-controller;
0081 reg = <0x0 0xfff01000 0 0x1000>,
0082 <0x0 0xfff02000 0 0x2000>,
0083 <0x0 0xfff04000 0 0x2000>,
0084 <0x0 0xfff06000 0 0x2000>;
0085 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0086 };
0087
0088 apb4: apb4@fe000000 {
0089 compatible = "simple-bus";
0090 reg = <0x0 0xfe000000 0x0 0x480000>;
0091 #address-cells = <2>;
0092 #size-cells = <2>;
0093 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
0094
0095 periphs_pinctrl: pinctrl@4000 {
0096 compatible = "amlogic,meson-s4-periphs-pinctrl";
0097 #address-cells = <2>;
0098 #size-cells = <2>;
0099 ranges;
0100
0101 gpio: bank@4000 {
0102 reg = <0x0 0x4000 0x0 0x004c>,
0103 <0x0 0x40c0 0x0 0x0220>;
0104 reg-names = "mux", "gpio";
0105 gpio-controller;
0106 #gpio-cells = <2>;
0107 gpio-ranges = <&periphs_pinctrl 0 0 82>;
0108 };
0109 };
0110
0111 gpio_intc: interrupt-controller@4080 {
0112 compatible = "amlogic,meson-s4-gpio-intc",
0113 "amlogic,meson-gpio-intc";
0114 reg = <0x0 0x4080 0x0 0x20>;
0115 interrupt-controller;
0116 #interrupt-cells = <2>;
0117 amlogic,channel-interrupts =
0118 <10 11 12 13 14 15 16 17 18 19 20 21>;
0119 };
0120
0121 uart_B: serial@7a000 {
0122 compatible = "amlogic,meson-s4-uart",
0123 "amlogic,meson-ao-uart";
0124 reg = <0x0 0x7a000 0x0 0x18>;
0125 interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
0126 status = "disabled";
0127 clocks = <&xtal>, <&xtal>, <&xtal>;
0128 clock-names = "xtal", "pclk", "baud";
0129 };
0130
0131 reset: reset-controller@2000 {
0132 compatible = "amlogic,meson-s4-reset";
0133 reg = <0x0 0x2000 0x0 0x98>;
0134 #reset-cells = <1>;
0135 };
0136 };
0137 };
0138 };
