0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2016 Endless Computers, Inc.
0004 * Author: Carlo Caione <carlo@endlessm.com>
0005 */
0006
0007 #include "meson-gx.dtsi"
0008 #include <dt-bindings/clock/gxbb-clkc.h>
0009 #include <dt-bindings/clock/gxbb-aoclkc.h>
0010 #include <dt-bindings/gpio/meson-gxl-gpio.h>
0011 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
0012
0013 / {
0014 compatible = "amlogic,meson-gxl";
0015
0016 soc {
0017 usb: usb@d0078080 {
0018 compatible = "amlogic,meson-gxl-usb-ctrl";
0019 reg = <0x0 0xd0078080 0x0 0x20>;
0020 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0021 #address-cells = <2>;
0022 #size-cells = <2>;
0023 ranges;
0024
0025 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
0026 clock-names = "usb_ctrl", "ddr";
0027 resets = <&reset RESET_USB_OTG>;
0028
0029 dr_mode = "otg";
0030
0031 phys = <&usb2_phy0>, <&usb2_phy1>;
0032 phy-names = "usb2-phy0", "usb2-phy1";
0033
0034 dwc2: usb@c9100000 {
0035 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
0036 reg = <0x0 0xc9100000 0x0 0x40000>;
0037 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0038 clocks = <&clkc CLKID_USB1>;
0039 clock-names = "otg";
0040 phys = <&usb2_phy1>;
0041 dr_mode = "peripheral";
0042 g-rx-fifo-size = <192>;
0043 g-np-tx-fifo-size = <128>;
0044 g-tx-fifo-size = <128 128 16 16 16>;
0045 };
0046
0047 dwc3: usb@c9000000 {
0048 compatible = "snps,dwc3";
0049 reg = <0x0 0xc9000000 0x0 0x100000>;
0050 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0051 dr_mode = "host";
0052 maximum-speed = "high-speed";
0053 snps,dis_u2_susphy_quirk;
0054 };
0055 };
0056
0057 acodec: audio-controller@c8832000 {
0058 compatible = "amlogic,t9015";
0059 reg = <0x0 0xc8832000 0x0 0x14>;
0060 #sound-dai-cells = <0>;
0061 sound-name-prefix = "ACODEC";
0062 clocks = <&clkc CLKID_ACODEC>;
0063 clock-names = "pclk";
0064 resets = <&reset RESET_ACODEC>;
0065 status = "disabled";
0066 };
0067
0068 crypto: crypto@c883e000 {
0069 compatible = "amlogic,gxl-crypto";
0070 reg = <0x0 0xc883e000 0x0 0x36>;
0071 interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
0072 <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
0073 clocks = <&clkc CLKID_BLKMV>;
0074 clock-names = "blkmv";
0075 status = "okay";
0076 };
0077 };
0078 };
0079
0080 &aiu {
0081 compatible = "amlogic,aiu-gxl", "amlogic,aiu";
0082 clocks = <&clkc CLKID_AIU_GLUE>,
0083 <&clkc CLKID_I2S_OUT>,
0084 <&clkc CLKID_AOCLK_GATE>,
0085 <&clkc CLKID_CTS_AMCLK>,
0086 <&clkc CLKID_MIXER_IFACE>,
0087 <&clkc CLKID_IEC958>,
0088 <&clkc CLKID_IEC958_GATE>,
0089 <&clkc CLKID_CTS_MCLK_I958>,
0090 <&clkc CLKID_CTS_I958>;
0091 clock-names = "pclk",
0092 "i2s_pclk",
0093 "i2s_aoclk",
0094 "i2s_mclk",
0095 "i2s_mixer",
0096 "spdif_pclk",
0097 "spdif_aoclk",
0098 "spdif_mclk",
0099 "spdif_mclk_sel";
0100 resets = <&reset RESET_AIU>;
0101 };
0102
0103 &apb {
0104 usb2_phy0: phy@78000 {
0105 compatible = "amlogic,meson-gxl-usb2-phy";
0106 #phy-cells = <0>;
0107 reg = <0x0 0x78000 0x0 0x20>;
0108 clocks = <&clkc CLKID_USB>;
0109 clock-names = "phy";
0110 resets = <&reset RESET_USB_OTG>;
0111 reset-names = "phy";
0112 status = "okay";
0113 };
0114
0115 usb2_phy1: phy@78020 {
0116 compatible = "amlogic,meson-gxl-usb2-phy";
0117 #phy-cells = <0>;
0118 reg = <0x0 0x78020 0x0 0x20>;
0119 clocks = <&clkc CLKID_USB>;
0120 clock-names = "phy";
0121 resets = <&reset RESET_USB_OTG>;
0122 reset-names = "phy";
0123 status = "okay";
0124 };
0125 };
0126
0127 &efuse {
0128 clocks = <&clkc CLKID_EFUSE>;
0129 };
0130
0131 ðmac {
0132 clocks = <&clkc CLKID_ETH>,
0133 <&clkc CLKID_FCLK_DIV2>,
0134 <&clkc CLKID_MPLL2>,
0135 <&clkc CLKID_FCLK_DIV2>;
0136 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
0137
0138 mdio0: mdio {
0139 #address-cells = <1>;
0140 #size-cells = <0>;
0141 compatible = "snps,dwmac-mdio";
0142 };
0143 };
0144
0145 &aobus {
0146 pinctrl_aobus: pinctrl@14 {
0147 compatible = "amlogic,meson-gxl-aobus-pinctrl";
0148 #address-cells = <2>;
0149 #size-cells = <2>;
0150 ranges;
0151
0152 gpio_ao: bank@14 {
0153 reg = <0x0 0x00014 0x0 0x8>,
0154 <0x0 0x0002c 0x0 0x4>,
0155 <0x0 0x00024 0x0 0x8>;
0156 reg-names = "mux", "pull", "gpio";
0157 gpio-controller;
0158 #gpio-cells = <2>;
0159 gpio-ranges = <&pinctrl_aobus 0 0 14>;
0160 };
0161
0162 uart_ao_a_pins: uart_ao_a {
0163 mux {
0164 groups = "uart_tx_ao_a", "uart_rx_ao_a";
0165 function = "uart_ao";
0166 bias-disable;
0167 };
0168 };
0169
0170 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
0171 mux {
0172 groups = "uart_cts_ao_a",
0173 "uart_rts_ao_a";
0174 function = "uart_ao";
0175 bias-disable;
0176 };
0177 };
0178
0179 uart_ao_b_pins: uart_ao_b {
0180 mux {
0181 groups = "uart_tx_ao_b", "uart_rx_ao_b";
0182 function = "uart_ao_b";
0183 bias-disable;
0184 };
0185 };
0186
0187 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
0188 mux {
0189 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
0190 function = "uart_ao_b";
0191 bias-disable;
0192 };
0193 };
0194
0195 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
0196 mux {
0197 groups = "uart_cts_ao_b",
0198 "uart_rts_ao_b";
0199 function = "uart_ao_b";
0200 bias-disable;
0201 };
0202 };
0203
0204 remote_input_ao_pins: remote_input_ao {
0205 mux {
0206 groups = "remote_input_ao";
0207 function = "remote_input_ao";
0208 bias-disable;
0209 };
0210 };
0211
0212 i2c_ao_pins: i2c_ao {
0213 mux {
0214 groups = "i2c_sck_ao",
0215 "i2c_sda_ao";
0216 function = "i2c_ao";
0217 bias-disable;
0218 };
0219 };
0220
0221 pwm_ao_a_3_pins: pwm_ao_a_3 {
0222 mux {
0223 groups = "pwm_ao_a_3";
0224 function = "pwm_ao_a";
0225 bias-disable;
0226 };
0227 };
0228
0229 pwm_ao_a_8_pins: pwm_ao_a_8 {
0230 mux {
0231 groups = "pwm_ao_a_8";
0232 function = "pwm_ao_a";
0233 bias-disable;
0234 };
0235 };
0236
0237 pwm_ao_b_pins: pwm_ao_b {
0238 mux {
0239 groups = "pwm_ao_b";
0240 function = "pwm_ao_b";
0241 bias-disable;
0242 };
0243 };
0244
0245 pwm_ao_b_6_pins: pwm_ao_b_6 {
0246 mux {
0247 groups = "pwm_ao_b_6";
0248 function = "pwm_ao_b";
0249 bias-disable;
0250 };
0251 };
0252
0253 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
0254 mux {
0255 groups = "i2s_out_ch23_ao";
0256 function = "i2s_out_ao";
0257 bias-disable;
0258 };
0259 };
0260
0261 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
0262 mux {
0263 groups = "i2s_out_ch45_ao";
0264 function = "i2s_out_ao";
0265 bias-disable;
0266 };
0267 };
0268
0269 spdif_out_ao_6_pins: spdif_out_ao_6 {
0270 mux {
0271 groups = "spdif_out_ao_6";
0272 function = "spdif_out_ao";
0273 bias-disable;
0274 };
0275 };
0276
0277 spdif_out_ao_9_pins: spdif_out_ao_9 {
0278 mux {
0279 groups = "spdif_out_ao_9";
0280 function = "spdif_out_ao";
0281 bias-disable;
0282 };
0283 };
0284
0285 ao_cec_pins: ao_cec {
0286 mux {
0287 groups = "ao_cec";
0288 function = "cec_ao";
0289 bias-disable;
0290 };
0291 };
0292
0293 ee_cec_pins: ee_cec {
0294 mux {
0295 groups = "ee_cec";
0296 function = "cec_ao";
0297 bias-disable;
0298 };
0299 };
0300 };
0301 };
0302
0303 &cec_AO {
0304 clocks = <&clkc_AO CLKID_AO_CEC_32K>;
0305 clock-names = "core";
0306 };
0307
0308 &clkc_AO {
0309 compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
0310 clocks = <&xtal>, <&clkc CLKID_CLK81>;
0311 clock-names = "xtal", "mpeg-clk";
0312 };
0313
0314 &gpio_intc {
0315 compatible = "amlogic,meson-gpio-intc",
0316 "amlogic,meson-gxl-gpio-intc";
0317 status = "okay";
0318 };
0319
0320 &hdmi_tx {
0321 compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
0322 resets = <&reset RESET_HDMITX_CAPB3>,
0323 <&reset RESET_HDMI_SYSTEM_RESET>,
0324 <&reset RESET_HDMI_TX>;
0325 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
0326 clocks = <&clkc CLKID_HDMI_PCLK>,
0327 <&clkc CLKID_CLK81>,
0328 <&clkc CLKID_GCLK_VENCI_INT0>;
0329 clock-names = "isfr", "iahb", "venci";
0330 };
0331
0332 &sysctrl {
0333 clkc: clock-controller {
0334 compatible = "amlogic,gxl-clkc";
0335 #clock-cells = <1>;
0336 clocks = <&xtal>;
0337 clock-names = "xtal";
0338 };
0339 };
0340
0341 &hwrng {
0342 clocks = <&clkc CLKID_RNG0>;
0343 clock-names = "core";
0344 };
0345
0346 &i2c_A {
0347 clocks = <&clkc CLKID_I2C>;
0348 };
0349
0350 &i2c_AO {
0351 clocks = <&clkc CLKID_AO_I2C>;
0352 };
0353
0354 &i2c_B {
0355 clocks = <&clkc CLKID_I2C>;
0356 };
0357
0358 &i2c_C {
0359 clocks = <&clkc CLKID_I2C>;
0360 };
0361
0362 &periphs {
0363 pinctrl_periphs: pinctrl@4b0 {
0364 compatible = "amlogic,meson-gxl-periphs-pinctrl";
0365 #address-cells = <2>;
0366 #size-cells = <2>;
0367 ranges;
0368
0369 gpio: bank@4b0 {
0370 reg = <0x0 0x004b0 0x0 0x28>,
0371 <0x0 0x004e8 0x0 0x14>,
0372 <0x0 0x00520 0x0 0x14>,
0373 <0x0 0x00430 0x0 0x40>;
0374 reg-names = "mux", "pull", "pull-enable", "gpio";
0375 gpio-controller;
0376 #gpio-cells = <2>;
0377 gpio-ranges = <&pinctrl_periphs 0 0 100>;
0378 };
0379
0380 emmc_pins: emmc {
0381 mux-0 {
0382 groups = "emmc_nand_d07",
0383 "emmc_cmd";
0384 function = "emmc";
0385 bias-pull-up;
0386 };
0387
0388 mux-1 {
0389 groups = "emmc_clk";
0390 function = "emmc";
0391 bias-disable;
0392 };
0393 };
0394
0395 emmc_ds_pins: emmc-ds {
0396 mux {
0397 groups = "emmc_ds";
0398 function = "emmc";
0399 bias-pull-down;
0400 };
0401 };
0402
0403 emmc_clk_gate_pins: emmc_clk_gate {
0404 mux {
0405 groups = "BOOT_8";
0406 function = "gpio_periphs";
0407 bias-pull-down;
0408 };
0409 };
0410
0411 nor_pins: nor {
0412 mux {
0413 groups = "nor_d",
0414 "nor_q",
0415 "nor_c",
0416 "nor_cs";
0417 function = "nor";
0418 bias-disable;
0419 };
0420 };
0421
0422 spi_pins: spi-pins {
0423 mux {
0424 groups = "spi_miso",
0425 "spi_mosi",
0426 "spi_sclk";
0427 function = "spi";
0428 bias-disable;
0429 };
0430 };
0431
0432 spi_ss0_pins: spi-ss0 {
0433 mux {
0434 groups = "spi_ss0";
0435 function = "spi";
0436 bias-disable;
0437 };
0438 };
0439
0440 sdcard_pins: sdcard {
0441 mux-0 {
0442 groups = "sdcard_d0",
0443 "sdcard_d1",
0444 "sdcard_d2",
0445 "sdcard_d3",
0446 "sdcard_cmd";
0447 function = "sdcard";
0448 bias-pull-up;
0449 };
0450
0451 mux-1 {
0452 groups = "sdcard_clk";
0453 function = "sdcard";
0454 bias-disable;
0455 };
0456 };
0457
0458 sdcard_clk_gate_pins: sdcard_clk_gate {
0459 mux {
0460 groups = "CARD_2";
0461 function = "gpio_periphs";
0462 bias-pull-down;
0463 };
0464 };
0465
0466 sdio_pins: sdio {
0467 mux-0 {
0468 groups = "sdio_d0",
0469 "sdio_d1",
0470 "sdio_d2",
0471 "sdio_d3",
0472 "sdio_cmd";
0473 function = "sdio";
0474 bias-pull-up;
0475 };
0476
0477 mux-1 {
0478 groups = "sdio_clk";
0479 function = "sdio";
0480 bias-disable;
0481 };
0482 };
0483
0484 sdio_clk_gate_pins: sdio_clk_gate {
0485 mux {
0486 groups = "GPIOX_4";
0487 function = "gpio_periphs";
0488 bias-pull-down;
0489 };
0490 };
0491
0492 sdio_irq_pins: sdio_irq {
0493 mux {
0494 groups = "sdio_irq";
0495 function = "sdio";
0496 bias-disable;
0497 };
0498 };
0499
0500 uart_a_pins: uart_a {
0501 mux {
0502 groups = "uart_tx_a",
0503 "uart_rx_a";
0504 function = "uart_a";
0505 bias-disable;
0506 };
0507 };
0508
0509 uart_a_cts_rts_pins: uart_a_cts_rts {
0510 mux {
0511 groups = "uart_cts_a",
0512 "uart_rts_a";
0513 function = "uart_a";
0514 bias-disable;
0515 };
0516 };
0517
0518 uart_b_pins: uart_b {
0519 mux {
0520 groups = "uart_tx_b",
0521 "uart_rx_b";
0522 function = "uart_b";
0523 bias-disable;
0524 };
0525 };
0526
0527 uart_b_cts_rts_pins: uart_b_cts_rts {
0528 mux {
0529 groups = "uart_cts_b",
0530 "uart_rts_b";
0531 function = "uart_b";
0532 bias-disable;
0533 };
0534 };
0535
0536 uart_c_pins: uart_c {
0537 mux {
0538 groups = "uart_tx_c",
0539 "uart_rx_c";
0540 function = "uart_c";
0541 bias-disable;
0542 };
0543 };
0544
0545 uart_c_cts_rts_pins: uart_c_cts_rts {
0546 mux {
0547 groups = "uart_cts_c",
0548 "uart_rts_c";
0549 function = "uart_c";
0550 bias-disable;
0551 };
0552 };
0553
0554 i2c_a_pins: i2c_a {
0555 mux {
0556 groups = "i2c_sck_a",
0557 "i2c_sda_a";
0558 function = "i2c_a";
0559 bias-disable;
0560 };
0561 };
0562
0563 i2c_b_pins: i2c_b {
0564 mux {
0565 groups = "i2c_sck_b",
0566 "i2c_sda_b";
0567 function = "i2c_b";
0568 bias-disable;
0569 };
0570 };
0571
0572 i2c_c_pins: i2c_c {
0573 mux {
0574 groups = "i2c_sck_c",
0575 "i2c_sda_c";
0576 function = "i2c_c";
0577 bias-disable;
0578 };
0579 };
0580
0581 i2c_c_dv18_pins: i2c_c_dv18 {
0582 mux {
0583 groups = "i2c_sck_c_dv19",
0584 "i2c_sda_c_dv18";
0585 function = "i2c_c";
0586 bias-disable;
0587 };
0588 };
0589
0590 eth_pins: eth_c {
0591 mux {
0592 groups = "eth_mdio",
0593 "eth_mdc",
0594 "eth_clk_rx_clk",
0595 "eth_rx_dv",
0596 "eth_rxd0",
0597 "eth_rxd1",
0598 "eth_rxd2",
0599 "eth_rxd3",
0600 "eth_rgmii_tx_clk",
0601 "eth_tx_en",
0602 "eth_txd0",
0603 "eth_txd1",
0604 "eth_txd2",
0605 "eth_txd3";
0606 function = "eth";
0607 bias-disable;
0608 };
0609 };
0610
0611 eth_link_led_pins: eth_link_led {
0612 mux {
0613 groups = "eth_link_led";
0614 function = "eth_led";
0615 bias-disable;
0616 };
0617 };
0618
0619 eth_act_led_pins: eth_act_led {
0620 mux {
0621 groups = "eth_act_led";
0622 function = "eth_led";
0623 };
0624 };
0625
0626 pwm_a_pins: pwm_a {
0627 mux {
0628 groups = "pwm_a";
0629 function = "pwm_a";
0630 bias-disable;
0631 };
0632 };
0633
0634 pwm_b_pins: pwm_b {
0635 mux {
0636 groups = "pwm_b";
0637 function = "pwm_b";
0638 bias-disable;
0639 };
0640 };
0641
0642 pwm_c_pins: pwm_c {
0643 mux {
0644 groups = "pwm_c";
0645 function = "pwm_c";
0646 bias-disable;
0647 };
0648 };
0649
0650 pwm_d_pins: pwm_d {
0651 mux {
0652 groups = "pwm_d";
0653 function = "pwm_d";
0654 bias-disable;
0655 };
0656 };
0657
0658 pwm_e_pins: pwm_e {
0659 mux {
0660 groups = "pwm_e";
0661 function = "pwm_e";
0662 bias-disable;
0663 };
0664 };
0665
0666 pwm_f_clk_pins: pwm_f_clk {
0667 mux {
0668 groups = "pwm_f_clk";
0669 function = "pwm_f";
0670 bias-disable;
0671 };
0672 };
0673
0674 pwm_f_x_pins: pwm_f_x {
0675 mux {
0676 groups = "pwm_f_x";
0677 function = "pwm_f";
0678 bias-disable;
0679 };
0680 };
0681
0682 hdmi_hpd_pins: hdmi_hpd {
0683 mux {
0684 groups = "hdmi_hpd";
0685 function = "hdmi_hpd";
0686 bias-disable;
0687 };
0688 };
0689
0690 hdmi_i2c_pins: hdmi_i2c {
0691 mux {
0692 groups = "hdmi_sda", "hdmi_scl";
0693 function = "hdmi_i2c";
0694 bias-disable;
0695 };
0696 };
0697
0698 i2s_am_clk_pins: i2s_am_clk {
0699 mux {
0700 groups = "i2s_am_clk";
0701 function = "i2s_out";
0702 bias-disable;
0703 };
0704 };
0705
0706 i2s_out_ao_clk_pins: i2s_out_ao_clk {
0707 mux {
0708 groups = "i2s_out_ao_clk";
0709 function = "i2s_out";
0710 bias-disable;
0711 };
0712 };
0713
0714 i2s_out_lr_clk_pins: i2s_out_lr_clk {
0715 mux {
0716 groups = "i2s_out_lr_clk";
0717 function = "i2s_out";
0718 bias-disable;
0719 };
0720 };
0721
0722 i2s_out_ch01_pins: i2s_out_ch01 {
0723 mux {
0724 groups = "i2s_out_ch01";
0725 function = "i2s_out";
0726 bias-disable;
0727 };
0728 };
0729 i2sout_ch23_z_pins: i2sout_ch23_z {
0730 mux {
0731 groups = "i2sout_ch23_z";
0732 function = "i2s_out";
0733 bias-disable;
0734 };
0735 };
0736
0737 i2sout_ch45_z_pins: i2sout_ch45_z {
0738 mux {
0739 groups = "i2sout_ch45_z";
0740 function = "i2s_out";
0741 bias-disable;
0742 };
0743 };
0744
0745 i2sout_ch67_z_pins: i2sout_ch67_z {
0746 mux {
0747 groups = "i2sout_ch67_z";
0748 function = "i2s_out";
0749 bias-disable;
0750 };
0751 };
0752
0753 spdif_out_h_pins: spdif_out_ao_h {
0754 mux {
0755 groups = "spdif_out_h";
0756 function = "spdif_out";
0757 bias-disable;
0758 };
0759 };
0760 };
0761
0762 eth-phy-mux {
0763 compatible = "mdio-mux-mmioreg", "mdio-mux";
0764 #address-cells = <1>;
0765 #size-cells = <0>;
0766 reg = <0x0 0x55c 0x0 0x4>;
0767 mux-mask = <0xffffffff>;
0768 mdio-parent-bus = <&mdio0>;
0769
0770 internal_mdio: mdio@e40908ff {
0771 reg = <0xe40908ff>;
0772 #address-cells = <1>;
0773 #size-cells = <0>;
0774
0775 internal_phy: ethernet-phy@8 {
0776 compatible = "ethernet-phy-id0181.4400";
0777 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0778 reg = <8>;
0779 max-speed = <100>;
0780 };
0781 };
0782
0783 external_mdio: mdio@2009087f {
0784 reg = <0x2009087f>;
0785 #address-cells = <1>;
0786 #size-cells = <0>;
0787 };
0788 };
0789 };
0790
0791 &pwrc {
0792 resets = <&reset RESET_VIU>,
0793 <&reset RESET_VENC>,
0794 <&reset RESET_VCBUS>,
0795 <&reset RESET_BT656>,
0796 <&reset RESET_DVIN_RESET>,
0797 <&reset RESET_RDMA>,
0798 <&reset RESET_VENCI>,
0799 <&reset RESET_VENCP>,
0800 <&reset RESET_VDAC>,
0801 <&reset RESET_VDI6>,
0802 <&reset RESET_VENCL>,
0803 <&reset RESET_VID_LOCK>;
0804 reset-names = "viu", "venc", "vcbus", "bt656",
0805 "dvin", "rdma", "venci", "vencp",
0806 "vdac", "vdi6", "vencl", "vid_lock";
0807 clocks = <&clkc CLKID_VPU>,
0808 <&clkc CLKID_VAPB>;
0809 clock-names = "vpu", "vapb";
0810 /*
0811 * VPU clocking is provided by two identical clock paths
0812 * VPU_0 and VPU_1 muxed to a single clock by a glitch
0813 * free mux to safely change frequency while running.
0814 * Same for VAPB but with a final gate after the glitch free mux.
0815 */
0816 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
0817 <&clkc CLKID_VPU_0>,
0818 <&clkc CLKID_VPU>, /* Glitch free mux */
0819 <&clkc CLKID_VAPB_0_SEL>,
0820 <&clkc CLKID_VAPB_0>,
0821 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
0822 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
0823 <0>, /* Do Nothing */
0824 <&clkc CLKID_VPU_0>,
0825 <&clkc CLKID_FCLK_DIV4>,
0826 <0>, /* Do Nothing */
0827 <&clkc CLKID_VAPB_0>;
0828 assigned-clock-rates = <0>, /* Do Nothing */
0829 <666666666>,
0830 <0>, /* Do Nothing */
0831 <0>, /* Do Nothing */
0832 <250000000>,
0833 <0>; /* Do Nothing */
0834 };
0835
0836 &saradc {
0837 compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
0838 clocks = <&xtal>,
0839 <&clkc CLKID_SAR_ADC>,
0840 <&clkc CLKID_SAR_ADC_CLK>,
0841 <&clkc CLKID_SAR_ADC_SEL>;
0842 clock-names = "clkin", "core", "adc_clk", "adc_sel";
0843 };
0844
0845 &sd_emmc_a {
0846 clocks = <&clkc CLKID_SD_EMMC_A>,
0847 <&clkc CLKID_SD_EMMC_A_CLK0>,
0848 <&clkc CLKID_FCLK_DIV2>;
0849 clock-names = "core", "clkin0", "clkin1";
0850 resets = <&reset RESET_SD_EMMC_A>;
0851 };
0852
0853 &sd_emmc_b {
0854 clocks = <&clkc CLKID_SD_EMMC_B>,
0855 <&clkc CLKID_SD_EMMC_B_CLK0>,
0856 <&clkc CLKID_FCLK_DIV2>;
0857 clock-names = "core", "clkin0", "clkin1";
0858 resets = <&reset RESET_SD_EMMC_B>;
0859 };
0860
0861 &sd_emmc_c {
0862 clocks = <&clkc CLKID_SD_EMMC_C>,
0863 <&clkc CLKID_SD_EMMC_C_CLK0>,
0864 <&clkc CLKID_FCLK_DIV2>;
0865 clock-names = "core", "clkin0", "clkin1";
0866 resets = <&reset RESET_SD_EMMC_C>;
0867 };
0868
0869 &simplefb_hdmi {
0870 clocks = <&clkc CLKID_HDMI_PCLK>,
0871 <&clkc CLKID_CLK81>,
0872 <&clkc CLKID_GCLK_VENCI_INT0>;
0873 };
0874
0875 &spicc {
0876 clocks = <&clkc CLKID_SPICC>;
0877 clock-names = "core";
0878 resets = <&reset RESET_PERIPHS_SPICC>;
0879 num-cs = <1>;
0880 };
0881
0882 &spifc {
0883 clocks = <&clkc CLKID_SPI>;
0884 };
0885
0886 &uart_A {
0887 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
0888 clock-names = "xtal", "pclk", "baud";
0889 };
0890
0891 &uart_AO {
0892 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
0893 clock-names = "xtal", "pclk", "baud";
0894 };
0895
0896 &uart_AO_B {
0897 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
0898 clock-names = "xtal", "pclk", "baud";
0899 };
0900
0901 &uart_B {
0902 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
0903 clock-names = "xtal", "pclk", "baud";
0904 };
0905
0906 &uart_C {
0907 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
0908 clock-names = "xtal", "pclk", "baud";
0909 };
0910
0911 &vpu {
0912 compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
0913 power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
0914 };
0915
0916 &vdec {
0917 compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
0918 clocks = <&clkc CLKID_DOS_PARSER>,
0919 <&clkc CLKID_DOS>,
0920 <&clkc CLKID_VDEC_1>,
0921 <&clkc CLKID_VDEC_HEVC>;
0922 clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
0923 resets = <&reset RESET_PARSER>;
0924 reset-names = "esparser";
0925 };
