0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2016 Andreas Färber
0004 */
0005
0006 #include "meson-gx.dtsi"
0007 #include "meson-gx-mali450.dtsi"
0008 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
0009 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
0010 #include <dt-bindings/clock/gxbb-clkc.h>
0011 #include <dt-bindings/clock/gxbb-aoclkc.h>
0012 #include <dt-bindings/reset/gxbb-aoclkc.h>
0013
0014 / {
0015 compatible = "amlogic,meson-gxbb";
0016
0017 soc {
0018 usb0_phy: phy@c0000000 {
0019 compatible = "amlogic,meson-gxbb-usb2-phy";
0020 #phy-cells = <0>;
0021 reg = <0x0 0xc0000000 0x0 0x20>;
0022 resets = <&reset RESET_USB_OTG>;
0023 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
0024 clock-names = "usb_general", "usb";
0025 status = "disabled";
0026 };
0027
0028 usb1_phy: phy@c0000020 {
0029 compatible = "amlogic,meson-gxbb-usb2-phy";
0030 #phy-cells = <0>;
0031 reg = <0x0 0xc0000020 0x0 0x20>;
0032 resets = <&reset RESET_USB_OTG>;
0033 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
0034 clock-names = "usb_general", "usb";
0035 status = "disabled";
0036 };
0037
0038 usb0: usb@c9000000 {
0039 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
0040 reg = <0x0 0xc9000000 0x0 0x40000>;
0041 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0042 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
0043 clock-names = "otg";
0044 phys = <&usb0_phy>;
0045 phy-names = "usb2-phy";
0046 dr_mode = "host";
0047 status = "disabled";
0048 };
0049
0050 usb1: usb@c9100000 {
0051 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
0052 reg = <0x0 0xc9100000 0x0 0x40000>;
0053 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0054 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
0055 clock-names = "otg";
0056 phys = <&usb1_phy>;
0057 phy-names = "usb2-phy";
0058 dr_mode = "host";
0059 status = "disabled";
0060 };
0061 };
0062 };
0063
0064 &aiu {
0065 compatible = "amlogic,aiu-gxbb", "amlogic,aiu";
0066 clocks = <&clkc CLKID_AIU_GLUE>,
0067 <&clkc CLKID_I2S_OUT>,
0068 <&clkc CLKID_AOCLK_GATE>,
0069 <&clkc CLKID_CTS_AMCLK>,
0070 <&clkc CLKID_MIXER_IFACE>,
0071 <&clkc CLKID_IEC958>,
0072 <&clkc CLKID_IEC958_GATE>,
0073 <&clkc CLKID_CTS_MCLK_I958>,
0074 <&clkc CLKID_CTS_I958>;
0075 clock-names = "pclk",
0076 "i2s_pclk",
0077 "i2s_aoclk",
0078 "i2s_mclk",
0079 "i2s_mixer",
0080 "spdif_pclk",
0081 "spdif_aoclk",
0082 "spdif_mclk",
0083 "spdif_mclk_sel";
0084 resets = <&reset RESET_AIU>;
0085 };
0086
0087 &aobus {
0088 pinctrl_aobus: pinctrl@14 {
0089 compatible = "amlogic,meson-gxbb-aobus-pinctrl";
0090 #address-cells = <2>;
0091 #size-cells = <2>;
0092 ranges;
0093
0094 gpio_ao: bank@14 {
0095 reg = <0x0 0x00014 0x0 0x8>,
0096 <0x0 0x0002c 0x0 0x4>,
0097 <0x0 0x00024 0x0 0x8>;
0098 reg-names = "mux", "pull", "gpio";
0099 gpio-controller;
0100 #gpio-cells = <2>;
0101 gpio-ranges = <&pinctrl_aobus 0 0 14>;
0102 };
0103
0104 uart_ao_a_pins: uart_ao_a {
0105 mux {
0106 groups = "uart_tx_ao_a", "uart_rx_ao_a";
0107 function = "uart_ao";
0108 bias-disable;
0109 };
0110 };
0111
0112 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
0113 mux {
0114 groups = "uart_cts_ao_a",
0115 "uart_rts_ao_a";
0116 function = "uart_ao";
0117 bias-disable;
0118 };
0119 };
0120
0121 uart_ao_b_pins: uart_ao_b {
0122 mux {
0123 groups = "uart_tx_ao_b", "uart_rx_ao_b";
0124 function = "uart_ao_b";
0125 bias-disable;
0126 };
0127 };
0128
0129 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
0130 mux {
0131 groups = "uart_cts_ao_b",
0132 "uart_rts_ao_b";
0133 function = "uart_ao_b";
0134 bias-disable;
0135 };
0136 };
0137
0138 remote_input_ao_pins: remote_input_ao {
0139 mux {
0140 groups = "remote_input_ao";
0141 function = "remote_input_ao";
0142 bias-disable;
0143 };
0144 };
0145
0146 i2c_ao_pins: i2c_ao {
0147 mux {
0148 groups = "i2c_sck_ao",
0149 "i2c_sda_ao";
0150 function = "i2c_ao";
0151 bias-disable;
0152 };
0153 };
0154
0155 pwm_ao_a_3_pins: pwm_ao_a_3 {
0156 mux {
0157 groups = "pwm_ao_a_3";
0158 function = "pwm_ao_a_3";
0159 bias-disable;
0160 };
0161 };
0162
0163 pwm_ao_a_6_pins: pwm_ao_a_6 {
0164 mux {
0165 groups = "pwm_ao_a_6";
0166 function = "pwm_ao_a_6";
0167 bias-disable;
0168 };
0169 };
0170
0171 pwm_ao_a_12_pins: pwm_ao_a_12 {
0172 mux {
0173 groups = "pwm_ao_a_12";
0174 function = "pwm_ao_a_12";
0175 bias-disable;
0176 };
0177 };
0178
0179 pwm_ao_b_pins: pwm_ao_b {
0180 mux {
0181 groups = "pwm_ao_b";
0182 function = "pwm_ao_b";
0183 bias-disable;
0184 };
0185 };
0186
0187 i2s_am_clk_pins: i2s_am_clk {
0188 mux {
0189 groups = "i2s_am_clk";
0190 function = "i2s_out_ao";
0191 bias-disable;
0192 };
0193 };
0194
0195 i2s_out_ao_clk_pins: i2s_out_ao_clk {
0196 mux {
0197 groups = "i2s_out_ao_clk";
0198 function = "i2s_out_ao";
0199 bias-disable;
0200 };
0201 };
0202
0203 i2s_out_lr_clk_pins: i2s_out_lr_clk {
0204 mux {
0205 groups = "i2s_out_lr_clk";
0206 function = "i2s_out_ao";
0207 bias-disable;
0208 };
0209 };
0210
0211 i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
0212 mux {
0213 groups = "i2s_out_ch01_ao";
0214 function = "i2s_out_ao";
0215 bias-disable;
0216 };
0217 };
0218
0219 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
0220 mux {
0221 groups = "i2s_out_ch23_ao";
0222 function = "i2s_out_ao";
0223 bias-disable;
0224 };
0225 };
0226
0227 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
0228 mux {
0229 groups = "i2s_out_ch45_ao";
0230 function = "i2s_out_ao";
0231 bias-disable;
0232 };
0233 };
0234
0235 spdif_out_ao_6_pins: spdif_out_ao_6 {
0236 mux {
0237 groups = "spdif_out_ao_6";
0238 function = "spdif_out_ao";
0239 };
0240 };
0241
0242 spdif_out_ao_13_pins: spdif_out_ao_13 {
0243 mux {
0244 groups = "spdif_out_ao_13";
0245 function = "spdif_out_ao";
0246 bias-disable;
0247 };
0248 };
0249
0250 ao_cec_pins: ao_cec {
0251 mux {
0252 groups = "ao_cec";
0253 function = "cec_ao";
0254 bias-disable;
0255 };
0256 };
0257
0258 ee_cec_pins: ee_cec {
0259 mux {
0260 groups = "ee_cec";
0261 function = "cec_ao";
0262 bias-disable;
0263 };
0264 };
0265 };
0266 };
0267
0268 &cbus {
0269 spifc: spi@8c80 {
0270 compatible = "amlogic,meson-gxbb-spifc";
0271 reg = <0x0 0x08c80 0x0 0x80>;
0272 #address-cells = <1>;
0273 #size-cells = <0>;
0274 clocks = <&clkc CLKID_SPI>;
0275 status = "disabled";
0276 };
0277 };
0278
0279 &cec_AO {
0280 clocks = <&clkc_AO CLKID_AO_CEC_32K>;
0281 clock-names = "core";
0282 };
0283
0284 &clkc_AO {
0285 compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
0286 clocks = <&xtal>, <&clkc CLKID_CLK81>;
0287 clock-names = "xtal", "mpeg-clk";
0288 };
0289
0290 &efuse {
0291 clocks = <&clkc CLKID_EFUSE>;
0292 };
0293
0294 ðmac {
0295 clocks = <&clkc CLKID_ETH>,
0296 <&clkc CLKID_FCLK_DIV2>,
0297 <&clkc CLKID_MPLL2>,
0298 <&clkc CLKID_FCLK_DIV2>;
0299 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
0300 };
0301
0302 &gpio_intc {
0303 compatible = "amlogic,meson-gpio-intc",
0304 "amlogic,meson-gxbb-gpio-intc";
0305 status = "okay";
0306 };
0307
0308 &hdmi_tx {
0309 compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
0310 resets = <&reset RESET_HDMITX_CAPB3>,
0311 <&reset RESET_HDMI_SYSTEM_RESET>,
0312 <&reset RESET_HDMI_TX>;
0313 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
0314 clocks = <&clkc CLKID_HDMI_PCLK>,
0315 <&clkc CLKID_CLK81>,
0316 <&clkc CLKID_GCLK_VENCI_INT0>;
0317 clock-names = "isfr", "iahb", "venci";
0318 };
0319
0320 &sysctrl {
0321 clkc: clock-controller {
0322 compatible = "amlogic,gxbb-clkc";
0323 #clock-cells = <1>;
0324 clocks = <&xtal>;
0325 clock-names = "xtal";
0326 };
0327 };
0328
0329 &hwrng {
0330 clocks = <&clkc CLKID_RNG0>;
0331 clock-names = "core";
0332 };
0333
0334 &i2c_A {
0335 clocks = <&clkc CLKID_I2C>;
0336 };
0337
0338 &i2c_AO {
0339 clocks = <&clkc CLKID_AO_I2C>;
0340 };
0341
0342 &i2c_B {
0343 clocks = <&clkc CLKID_I2C>;
0344 };
0345
0346 &i2c_C {
0347 clocks = <&clkc CLKID_I2C>;
0348 };
0349
0350 &mali {
0351 compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
0352
0353 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
0354 clock-names = "bus", "core";
0355
0356 assigned-clocks = <&clkc CLKID_GP0_PLL>;
0357 assigned-clock-rates = <744000000>;
0358 };
0359
0360 &periphs {
0361 pinctrl_periphs: pinctrl@4b0 {
0362 compatible = "amlogic,meson-gxbb-periphs-pinctrl";
0363 #address-cells = <2>;
0364 #size-cells = <2>;
0365 ranges;
0366
0367 gpio: bank@4b0 {
0368 reg = <0x0 0x004b0 0x0 0x28>,
0369 <0x0 0x004e8 0x0 0x14>,
0370 <0x0 0x00520 0x0 0x14>,
0371 <0x0 0x00430 0x0 0x40>;
0372 reg-names = "mux", "pull", "pull-enable", "gpio";
0373 gpio-controller;
0374 #gpio-cells = <2>;
0375 gpio-ranges = <&pinctrl_periphs 0 0 119>;
0376 };
0377
0378 emmc_pins: emmc {
0379 mux-0 {
0380 groups = "emmc_nand_d07",
0381 "emmc_cmd";
0382 function = "emmc";
0383 bias-pull-up;
0384 };
0385
0386 mux-1 {
0387 groups = "emmc_clk";
0388 function = "emmc";
0389 bias-disable;
0390 };
0391 };
0392
0393 emmc_ds_pins: emmc-ds {
0394 mux {
0395 groups = "emmc_ds";
0396 function = "emmc";
0397 bias-pull-down;
0398 };
0399 };
0400
0401 emmc_clk_gate_pins: emmc_clk_gate {
0402 mux {
0403 groups = "BOOT_8";
0404 function = "gpio_periphs";
0405 bias-pull-down;
0406 };
0407 };
0408
0409 nor_pins: nor {
0410 mux {
0411 groups = "nor_d",
0412 "nor_q",
0413 "nor_c",
0414 "nor_cs";
0415 function = "nor";
0416 bias-disable;
0417 };
0418 };
0419
0420 spi_pins: spi-pins {
0421 mux {
0422 groups = "spi_miso",
0423 "spi_mosi",
0424 "spi_sclk";
0425 function = "spi";
0426 bias-disable;
0427 };
0428 };
0429
0430 spi_ss0_pins: spi-ss0 {
0431 mux {
0432 groups = "spi_ss0";
0433 function = "spi";
0434 bias-disable;
0435 };
0436 };
0437
0438 sdcard_pins: sdcard {
0439 mux-0 {
0440 groups = "sdcard_d0",
0441 "sdcard_d1",
0442 "sdcard_d2",
0443 "sdcard_d3",
0444 "sdcard_cmd";
0445 function = "sdcard";
0446 bias-pull-up;
0447 };
0448
0449 mux-1 {
0450 groups = "sdcard_clk";
0451 function = "sdcard";
0452 bias-disable;
0453 };
0454 };
0455
0456 sdcard_clk_gate_pins: sdcard_clk_gate {
0457 mux {
0458 groups = "CARD_2";
0459 function = "gpio_periphs";
0460 bias-pull-down;
0461 };
0462 };
0463
0464 sdio_pins: sdio {
0465 mux-0 {
0466 groups = "sdio_d0",
0467 "sdio_d1",
0468 "sdio_d2",
0469 "sdio_d3",
0470 "sdio_cmd";
0471 function = "sdio";
0472 bias-pull-up;
0473 };
0474
0475 mux-1 {
0476 groups = "sdio_clk";
0477 function = "sdio";
0478 bias-disable;
0479 };
0480 };
0481
0482 sdio_clk_gate_pins: sdio_clk_gate {
0483 mux {
0484 groups = "GPIOX_4";
0485 function = "gpio_periphs";
0486 bias-pull-down;
0487 };
0488 };
0489
0490 sdio_irq_pins: sdio_irq {
0491 mux {
0492 groups = "sdio_irq";
0493 function = "sdio";
0494 bias-disable;
0495 };
0496 };
0497
0498 uart_a_pins: uart_a {
0499 mux {
0500 groups = "uart_tx_a",
0501 "uart_rx_a";
0502 function = "uart_a";
0503 bias-disable;
0504 };
0505 };
0506
0507 uart_a_cts_rts_pins: uart_a_cts_rts {
0508 mux {
0509 groups = "uart_cts_a",
0510 "uart_rts_a";
0511 function = "uart_a";
0512 bias-disable;
0513 };
0514 };
0515
0516 uart_b_pins: uart_b {
0517 mux {
0518 groups = "uart_tx_b",
0519 "uart_rx_b";
0520 function = "uart_b";
0521 bias-disable;
0522 };
0523 };
0524
0525 uart_b_cts_rts_pins: uart_b_cts_rts {
0526 mux {
0527 groups = "uart_cts_b",
0528 "uart_rts_b";
0529 function = "uart_b";
0530 bias-disable;
0531 };
0532 };
0533
0534 uart_c_pins: uart_c {
0535 mux {
0536 groups = "uart_tx_c",
0537 "uart_rx_c";
0538 function = "uart_c";
0539 bias-disable;
0540 };
0541 };
0542
0543 uart_c_cts_rts_pins: uart_c_cts_rts {
0544 mux {
0545 groups = "uart_cts_c",
0546 "uart_rts_c";
0547 function = "uart_c";
0548 bias-disable;
0549 };
0550 };
0551
0552 i2c_a_pins: i2c_a {
0553 mux {
0554 groups = "i2c_sck_a",
0555 "i2c_sda_a";
0556 function = "i2c_a";
0557 bias-disable;
0558 };
0559 };
0560
0561 i2c_b_pins: i2c_b {
0562 mux {
0563 groups = "i2c_sck_b",
0564 "i2c_sda_b";
0565 function = "i2c_b";
0566 bias-disable;
0567 };
0568 };
0569
0570 i2c_c_pins: i2c_c {
0571 mux {
0572 groups = "i2c_sck_c",
0573 "i2c_sda_c";
0574 function = "i2c_c";
0575 bias-disable;
0576 };
0577 };
0578
0579 eth_rgmii_pins: eth-rgmii {
0580 mux {
0581 groups = "eth_mdio",
0582 "eth_mdc",
0583 "eth_clk_rx_clk",
0584 "eth_rx_dv",
0585 "eth_rxd0",
0586 "eth_rxd1",
0587 "eth_rxd2",
0588 "eth_rxd3",
0589 "eth_rgmii_tx_clk",
0590 "eth_tx_en",
0591 "eth_txd0",
0592 "eth_txd1",
0593 "eth_txd2",
0594 "eth_txd3";
0595 function = "eth";
0596 bias-disable;
0597 };
0598 };
0599
0600 eth_rmii_pins: eth-rmii {
0601 mux {
0602 groups = "eth_mdio",
0603 "eth_mdc",
0604 "eth_clk_rx_clk",
0605 "eth_rx_dv",
0606 "eth_rxd0",
0607 "eth_rxd1",
0608 "eth_tx_en",
0609 "eth_txd0",
0610 "eth_txd1";
0611 function = "eth";
0612 bias-disable;
0613 };
0614 };
0615
0616 pwm_a_x_pins: pwm_a_x {
0617 mux {
0618 groups = "pwm_a_x";
0619 function = "pwm_a_x";
0620 bias-disable;
0621 };
0622 };
0623
0624 pwm_a_y_pins: pwm_a_y {
0625 mux {
0626 groups = "pwm_a_y";
0627 function = "pwm_a_y";
0628 bias-disable;
0629 };
0630 };
0631
0632 pwm_b_pins: pwm_b {
0633 mux {
0634 groups = "pwm_b";
0635 function = "pwm_b";
0636 bias-disable;
0637 };
0638 };
0639
0640 pwm_d_pins: pwm_d {
0641 mux {
0642 groups = "pwm_d";
0643 function = "pwm_d";
0644 bias-disable;
0645 };
0646 };
0647
0648 pwm_e_pins: pwm_e {
0649 mux {
0650 groups = "pwm_e";
0651 function = "pwm_e";
0652 bias-disable;
0653 };
0654 };
0655
0656 pwm_f_x_pins: pwm_f_x {
0657 mux {
0658 groups = "pwm_f_x";
0659 function = "pwm_f_x";
0660 bias-disable;
0661 };
0662 };
0663
0664 pwm_f_y_pins: pwm_f_y {
0665 mux {
0666 groups = "pwm_f_y";
0667 function = "pwm_f_y";
0668 bias-disable;
0669 };
0670 };
0671
0672 hdmi_hpd_pins: hdmi_hpd {
0673 mux {
0674 groups = "hdmi_hpd";
0675 function = "hdmi_hpd";
0676 bias-disable;
0677 };
0678 };
0679
0680 hdmi_i2c_pins: hdmi_i2c {
0681 mux {
0682 groups = "hdmi_sda", "hdmi_scl";
0683 function = "hdmi_i2c";
0684 bias-disable;
0685 };
0686 };
0687
0688 i2sout_ch23_y_pins: i2sout_ch23_y {
0689 mux {
0690 groups = "i2sout_ch23_y";
0691 function = "i2s_out";
0692 bias-disable;
0693 };
0694 };
0695
0696 i2sout_ch45_y_pins: i2sout_ch45_y {
0697 mux {
0698 groups = "i2sout_ch45_y";
0699 function = "i2s_out";
0700 bias-disable;
0701 };
0702 };
0703
0704 i2sout_ch67_y_pins: i2sout_ch67_y {
0705 mux {
0706 groups = "i2sout_ch67_y";
0707 function = "i2s_out";
0708 bias-disable;
0709 };
0710 };
0711
0712 spdif_out_y_pins: spdif_out_y {
0713 mux {
0714 groups = "spdif_out_y";
0715 function = "spdif_out";
0716 bias-disable;
0717 };
0718 };
0719 };
0720 };
0721
0722 &pwrc {
0723 resets = <&reset RESET_VIU>,
0724 <&reset RESET_VENC>,
0725 <&reset RESET_VCBUS>,
0726 <&reset RESET_BT656>,
0727 <&reset RESET_DVIN_RESET>,
0728 <&reset RESET_RDMA>,
0729 <&reset RESET_VENCI>,
0730 <&reset RESET_VENCP>,
0731 <&reset RESET_VDAC>,
0732 <&reset RESET_VDI6>,
0733 <&reset RESET_VENCL>,
0734 <&reset RESET_VID_LOCK>;
0735 reset-names = "viu", "venc", "vcbus", "bt656",
0736 "dvin", "rdma", "venci", "vencp",
0737 "vdac", "vdi6", "vencl", "vid_lock";
0738 clocks = <&clkc CLKID_VPU>,
0739 <&clkc CLKID_VAPB>;
0740 clock-names = "vpu", "vapb";
0741 /*
0742 * VPU clocking is provided by two identical clock paths
0743 * VPU_0 and VPU_1 muxed to a single clock by a glitch
0744 * free mux to safely change frequency while running.
0745 * Same for VAPB but with a final gate after the glitch free mux.
0746 */
0747 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
0748 <&clkc CLKID_VPU_0>,
0749 <&clkc CLKID_VPU>, /* Glitch free mux */
0750 <&clkc CLKID_VAPB_0_SEL>,
0751 <&clkc CLKID_VAPB_0>,
0752 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
0753 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
0754 <0>, /* Do Nothing */
0755 <&clkc CLKID_VPU_0>,
0756 <&clkc CLKID_FCLK_DIV4>,
0757 <0>, /* Do Nothing */
0758 <&clkc CLKID_VAPB_0>;
0759 assigned-clock-rates = <0>, /* Do Nothing */
0760 <666666666>,
0761 <0>, /* Do Nothing */
0762 <0>, /* Do Nothing */
0763 <250000000>,
0764 <0>; /* Do Nothing */
0765 };
0766
0767 &saradc {
0768 compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
0769 clocks = <&xtal>,
0770 <&clkc CLKID_SAR_ADC>,
0771 <&clkc CLKID_SAR_ADC_CLK>,
0772 <&clkc CLKID_SAR_ADC_SEL>;
0773 clock-names = "clkin", "core", "adc_clk", "adc_sel";
0774 };
0775
0776 &sd_emmc_a {
0777 clocks = <&clkc CLKID_SD_EMMC_A>,
0778 <&clkc CLKID_SD_EMMC_A_CLK0>,
0779 <&clkc CLKID_FCLK_DIV2>;
0780 clock-names = "core", "clkin0", "clkin1";
0781 resets = <&reset RESET_SD_EMMC_A>;
0782 };
0783
0784 &sd_emmc_b {
0785 clocks = <&clkc CLKID_SD_EMMC_B>,
0786 <&clkc CLKID_SD_EMMC_B_CLK0>,
0787 <&clkc CLKID_FCLK_DIV2>;
0788 clock-names = "core", "clkin0", "clkin1";
0789 resets = <&reset RESET_SD_EMMC_B>;
0790 };
0791
0792 &sd_emmc_c {
0793 clocks = <&clkc CLKID_SD_EMMC_C>,
0794 <&clkc CLKID_SD_EMMC_C_CLK0>,
0795 <&clkc CLKID_FCLK_DIV2>;
0796 clock-names = "core", "clkin0", "clkin1";
0797 resets = <&reset RESET_SD_EMMC_C>;
0798 };
0799
0800 &simplefb_hdmi {
0801 clocks = <&clkc CLKID_HDMI_PCLK>,
0802 <&clkc CLKID_CLK81>,
0803 <&clkc CLKID_GCLK_VENCI_INT0>;
0804 };
0805
0806 &spicc {
0807 clocks = <&clkc CLKID_SPICC>;
0808 clock-names = "core";
0809 resets = <&reset RESET_PERIPHS_SPICC>;
0810 num-cs = <1>;
0811 };
0812
0813 &spifc {
0814 clocks = <&clkc CLKID_SPI>;
0815 };
0816
0817 &uart_A {
0818 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
0819 clock-names = "xtal", "pclk", "baud";
0820 };
0821
0822 &uart_AO {
0823 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
0824 clock-names = "xtal", "pclk", "baud";
0825 };
0826
0827 &uart_AO_B {
0828 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
0829 clock-names = "xtal", "pclk", "baud";
0830 };
0831
0832 &uart_B {
0833 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
0834 clock-names = "xtal", "pclk", "baud";
0835 };
0836
0837 &uart_C {
0838 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
0839 clock-names = "xtal", "pclk", "baud";
0840 };
0841
0842 &vpu {
0843 compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
0844 power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
0845 };
0846
0847 &vdec {
0848 compatible = "amlogic,gxbb-vdec", "amlogic,gx-vdec";
0849 clocks = <&clkc CLKID_DOS_PARSER>,
0850 <&clkc CLKID_DOS>,
0851 <&clkc CLKID_VDEC_1>,
0852 <&clkc CLKID_VDEC_HEVC>;
0853 clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
0854 resets = <&reset RESET_PARSER>;
0855 reset-names = "esparser";
0856 };
