0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2019 BayLibre, SAS
0004 * Author: Neil Armstrong <narmstrong@baylibre.com>
0005 * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
0006 */
0007
0008 / {
0009 model = "Khadas VIM3";
0010
0011 vddcpu_a: regulator-vddcpu-a {
0012 /*
0013 * MP8756GD Regulator.
0014 */
0015 compatible = "pwm-regulator";
0016
0017 regulator-name = "VDDCPU_A";
0018 regulator-min-microvolt = <690000>;
0019 regulator-max-microvolt = <1050000>;
0020
0021 pwm-supply = <&dc_in>;
0022
0023 pwms = <&pwm_ab 0 1250 0>;
0024 pwm-dutycycle-range = <100 0>;
0025
0026 regulator-boot-on;
0027 regulator-always-on;
0028 };
0029
0030 vddcpu_b: regulator-vddcpu-b {
0031 /*
0032 * Silergy SY8030DEC Regulator.
0033 */
0034 compatible = "pwm-regulator";
0035
0036 regulator-name = "VDDCPU_B";
0037 regulator-min-microvolt = <690000>;
0038 regulator-max-microvolt = <1050000>;
0039
0040 pwm-supply = <&vsys_3v3>;
0041
0042 pwms = <&pwm_AO_cd 1 1250 0>;
0043 pwm-dutycycle-range = <100 0>;
0044
0045 regulator-boot-on;
0046 regulator-always-on;
0047 };
0048 };
0049
0050 &cpu0 {
0051 cpu-supply = <&vddcpu_b>;
0052 operating-points-v2 = <&cpu_opp_table_0>;
0053 clocks = <&clkc CLKID_CPU_CLK>;
0054 clock-latency = <50000>;
0055 };
0056
0057 &cpu1 {
0058 cpu-supply = <&vddcpu_b>;
0059 operating-points-v2 = <&cpu_opp_table_0>;
0060 clocks = <&clkc CLKID_CPU_CLK>;
0061 clock-latency = <50000>;
0062 };
0063
0064 &cpu100 {
0065 cpu-supply = <&vddcpu_a>;
0066 operating-points-v2 = <&cpub_opp_table_1>;
0067 clocks = <&clkc CLKID_CPUB_CLK>;
0068 clock-latency = <50000>;
0069 };
0070
0071 &cpu101 {
0072 cpu-supply = <&vddcpu_a>;
0073 operating-points-v2 = <&cpub_opp_table_1>;
0074 clocks = <&clkc CLKID_CPUB_CLK>;
0075 clock-latency = <50000>;
0076 };
0077
0078 &cpu102 {
0079 cpu-supply = <&vddcpu_a>;
0080 operating-points-v2 = <&cpub_opp_table_1>;
0081 clocks = <&clkc CLKID_CPUB_CLK>;
0082 clock-latency = <50000>;
0083 };
0084
0085 &cpu103 {
0086 cpu-supply = <&vddcpu_a>;
0087 operating-points-v2 = <&cpub_opp_table_1>;
0088 clocks = <&clkc CLKID_CPUB_CLK>;
0089 clock-latency = <50000>;
0090 };
0091
0092 &pwm_ab {
0093 pinctrl-0 = <&pwm_a_e_pins>;
0094 pinctrl-names = "default";
0095 clocks = <&xtal>;
0096 clock-names = "clkin0";
0097 status = "okay";
0098 };
0099
0100 &pwm_AO_cd {
0101 pinctrl-0 = <&pwm_ao_d_e_pins>;
0102 pinctrl-names = "default";
0103 clocks = <&xtal>;
0104 clock-names = "clkin1";
0105 status = "okay";
0106 };
0107
