0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
0004 */
0005
0006 #include "meson-g12.dtsi"
0007
0008 / {
0009 compatible = "amlogic,g12a";
0010
0011 cpus {
0012 #address-cells = <0x2>;
0013 #size-cells = <0x0>;
0014
0015 cpu0: cpu@0 {
0016 device_type = "cpu";
0017 compatible = "arm,cortex-a53";
0018 reg = <0x0 0x0>;
0019 enable-method = "psci";
0020 next-level-cache = <&l2>;
0021 #cooling-cells = <2>;
0022 };
0023
0024 cpu1: cpu@1 {
0025 device_type = "cpu";
0026 compatible = "arm,cortex-a53";
0027 reg = <0x0 0x1>;
0028 enable-method = "psci";
0029 next-level-cache = <&l2>;
0030 #cooling-cells = <2>;
0031 };
0032
0033 cpu2: cpu@2 {
0034 device_type = "cpu";
0035 compatible = "arm,cortex-a53";
0036 reg = <0x0 0x2>;
0037 enable-method = "psci";
0038 next-level-cache = <&l2>;
0039 #cooling-cells = <2>;
0040 };
0041
0042 cpu3: cpu@3 {
0043 device_type = "cpu";
0044 compatible = "arm,cortex-a53";
0045 reg = <0x0 0x3>;
0046 enable-method = "psci";
0047 next-level-cache = <&l2>;
0048 #cooling-cells = <2>;
0049 };
0050
0051 l2: l2-cache0 {
0052 compatible = "cache";
0053 };
0054 };
0055
0056 cpu_opp_table: opp-table {
0057 compatible = "operating-points-v2";
0058 opp-shared;
0059
0060 opp-100000000 {
0061 opp-hz = /bits/ 64 <100000000>;
0062 opp-microvolt = <731000>;
0063 };
0064
0065 opp-250000000 {
0066 opp-hz = /bits/ 64 <250000000>;
0067 opp-microvolt = <731000>;
0068 };
0069
0070 opp-500000000 {
0071 opp-hz = /bits/ 64 <500000000>;
0072 opp-microvolt = <731000>;
0073 };
0074
0075 opp-667000000 {
0076 opp-hz = /bits/ 64 <666666666>;
0077 opp-microvolt = <731000>;
0078 };
0079
0080 opp-1000000000 {
0081 opp-hz = /bits/ 64 <1000000000>;
0082 opp-microvolt = <731000>;
0083 };
0084
0085 opp-1200000000 {
0086 opp-hz = /bits/ 64 <1200000000>;
0087 opp-microvolt = <731000>;
0088 };
0089
0090 opp-1398000000 {
0091 opp-hz = /bits/ 64 <1398000000>;
0092 opp-microvolt = <761000>;
0093 };
0094
0095 opp-1512000000 {
0096 opp-hz = /bits/ 64 <1512000000>;
0097 opp-microvolt = <791000>;
0098 };
0099
0100 opp-1608000000 {
0101 opp-hz = /bits/ 64 <1608000000>;
0102 opp-microvolt = <831000>;
0103 };
0104
0105 opp-1704000000 {
0106 opp-hz = /bits/ 64 <1704000000>;
0107 opp-microvolt = <861000>;
0108 };
0109
0110 opp-1800000000 {
0111 opp-hz = /bits/ 64 <1800000000>;
0112 opp-microvolt = <981000>;
0113 };
0114 };
0115 };
0116
0117 &cpu_thermal {
0118 cooling-maps {
0119 map0 {
0120 trip = <&cpu_passive>;
0121 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0122 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0123 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0124 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0125 };
0126
0127 map1 {
0128 trip = <&cpu_hot>;
0129 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0130 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0131 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0132 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0133 };
0134 };
0135 };
