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0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
0004 */
0005
0006 #include <dt-bindings/phy/phy.h>
0007 #include <dt-bindings/gpio/gpio.h>
0008 #include <dt-bindings/clock/g12a-clkc.h>
0009 #include <dt-bindings/clock/g12a-aoclkc.h>
0010 #include <dt-bindings/interrupt-controller/irq.h>
0011 #include <dt-bindings/interrupt-controller/arm-gic.h>
0012 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
0013 #include <dt-bindings/thermal/thermal.h>
0014
0015 / {
0016 interrupt-parent = <&gic>;
0017 #address-cells = <2>;
0018 #size-cells = <2>;
0019
0020 aliases {
0021 mmc0 = &sd_emmc_b; /* SD card */
0022 mmc1 = &sd_emmc_c; /* eMMC */
0023 mmc2 = &sd_emmc_a; /* SDIO */
0024 };
0025
0026 chosen {
0027 #address-cells = <2>;
0028 #size-cells = <2>;
0029 ranges;
0030
0031 simplefb_cvbs: framebuffer-cvbs {
0032 compatible = "amlogic,simple-framebuffer",
0033 "simple-framebuffer";
0034 amlogic,pipeline = "vpu-cvbs";
0035 clocks = <&clkc CLKID_HDMI>,
0036 <&clkc CLKID_HTX_PCLK>,
0037 <&clkc CLKID_VPU_INTR>;
0038 status = "disabled";
0039 };
0040
0041 simplefb_hdmi: framebuffer-hdmi {
0042 compatible = "amlogic,simple-framebuffer",
0043 "simple-framebuffer";
0044 amlogic,pipeline = "vpu-hdmi";
0045 clocks = <&clkc CLKID_HDMI>,
0046 <&clkc CLKID_HTX_PCLK>,
0047 <&clkc CLKID_VPU_INTR>;
0048 status = "disabled";
0049 };
0050 };
0051
0052 efuse: efuse {
0053 compatible = "amlogic,meson-gxbb-efuse";
0054 clocks = <&clkc CLKID_EFUSE>;
0055 #address-cells = <1>;
0056 #size-cells = <1>;
0057 read-only;
0058 secure-monitor = <&sm>;
0059 };
0060
0061 gpu_opp_table: opp-table-gpu {
0062 compatible = "operating-points-v2";
0063
0064 opp-124999998 {
0065 opp-hz = /bits/ 64 <124999998>;
0066 opp-microvolt = <800000>;
0067 };
0068 opp-249999996 {
0069 opp-hz = /bits/ 64 <249999996>;
0070 opp-microvolt = <800000>;
0071 };
0072 opp-285714281 {
0073 opp-hz = /bits/ 64 <285714281>;
0074 opp-microvolt = <800000>;
0075 };
0076 opp-399999994 {
0077 opp-hz = /bits/ 64 <399999994>;
0078 opp-microvolt = <800000>;
0079 };
0080 opp-499999992 {
0081 opp-hz = /bits/ 64 <499999992>;
0082 opp-microvolt = <800000>;
0083 };
0084 opp-666666656 {
0085 opp-hz = /bits/ 64 <666666656>;
0086 opp-microvolt = <800000>;
0087 };
0088 opp-799999987 {
0089 opp-hz = /bits/ 64 <799999987>;
0090 opp-microvolt = <800000>;
0091 };
0092 };
0093
0094 psci {
0095 compatible = "arm,psci-1.0";
0096 method = "smc";
0097 };
0098
0099 reserved-memory {
0100 #address-cells = <2>;
0101 #size-cells = <2>;
0102 ranges;
0103
0104 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
0105 secmon_reserved: secmon@5000000 {
0106 reg = <0x0 0x05000000 0x0 0x300000>;
0107 no-map;
0108 };
0109
0110 /* 32 MiB reserved for ARM Trusted Firmware (BL32) */
0111 secmon_reserved_bl32: secmon@5300000 {
0112 reg = <0x0 0x05300000 0x0 0x2000000>;
0113 no-map;
0114 };
0115
0116 linux,cma {
0117 compatible = "shared-dma-pool";
0118 reusable;
0119 size = <0x0 0x10000000>;
0120 alignment = <0x0 0x400000>;
0121 linux,cma-default;
0122 };
0123 };
0124
0125 sm: secure-monitor {
0126 compatible = "amlogic,meson-gxbb-sm";
0127 };
0128
0129 soc {
0130 compatible = "simple-bus";
0131 #address-cells = <2>;
0132 #size-cells = <2>;
0133 ranges;
0134
0135 pcie: pcie@fc000000 {
0136 compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
0137 reg = <0x0 0xfc000000 0x0 0x400000>,
0138 <0x0 0xff648000 0x0 0x2000>,
0139 <0x0 0xfc400000 0x0 0x200000>;
0140 reg-names = "elbi", "cfg", "config";
0141 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
0142 #interrupt-cells = <1>;
0143 interrupt-map-mask = <0 0 0 0>;
0144 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
0145 bus-range = <0x0 0xff>;
0146 #address-cells = <3>;
0147 #size-cells = <2>;
0148 device_type = "pci";
0149 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>,
0150 <0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
0151
0152 clocks = <&clkc CLKID_PCIE_PHY
0153 &clkc CLKID_PCIE_COMB
0154 &clkc CLKID_PCIE_PLL>;
0155 clock-names = "general",
0156 "pclk",
0157 "port";
0158 resets = <&reset RESET_PCIE_CTRL_A>,
0159 <&reset RESET_PCIE_APB>;
0160 reset-names = "port",
0161 "apb";
0162 num-lanes = <1>;
0163 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>;
0164 phy-names = "pcie";
0165 status = "disabled";
0166 };
0167
0168 ethmac: ethernet@ff3f0000 {
0169 compatible = "amlogic,meson-g12a-dwmac",
0170 "snps,dwmac-3.70a",
0171 "snps,dwmac";
0172 reg = <0x0 0xff3f0000 0x0 0x10000>,
0173 <0x0 0xff634540 0x0 0x8>;
0174 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0175 interrupt-names = "macirq";
0176 clocks = <&clkc CLKID_ETH>,
0177 <&clkc CLKID_FCLK_DIV2>,
0178 <&clkc CLKID_MPLL2>,
0179 <&clkc CLKID_FCLK_DIV2>;
0180 clock-names = "stmmaceth", "clkin0", "clkin1",
0181 "timing-adjustment";
0182 rx-fifo-depth = <4096>;
0183 tx-fifo-depth = <2048>;
0184 status = "disabled";
0185
0186 mdio0: mdio {
0187 #address-cells = <1>;
0188 #size-cells = <0>;
0189 compatible = "snps,dwmac-mdio";
0190 };
0191 };
0192
0193 apb: bus@ff600000 {
0194 compatible = "simple-bus";
0195 reg = <0x0 0xff600000 0x0 0x200000>;
0196 #address-cells = <2>;
0197 #size-cells = <2>;
0198 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
0199
0200 hdmi_tx: hdmi-tx@0 {
0201 compatible = "amlogic,meson-g12a-dw-hdmi";
0202 reg = <0x0 0x0 0x0 0x10000>;
0203 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
0204 resets = <&reset RESET_HDMITX_CAPB3>,
0205 <&reset RESET_HDMITX_PHY>,
0206 <&reset RESET_HDMITX>;
0207 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
0208 clocks = <&clkc CLKID_HDMI>,
0209 <&clkc CLKID_HTX_PCLK>,
0210 <&clkc CLKID_VPU_INTR>;
0211 clock-names = "isfr", "iahb", "venci";
0212 #address-cells = <1>;
0213 #size-cells = <0>;
0214 #sound-dai-cells = <0>;
0215 status = "disabled";
0216
0217 /* VPU VENC Input */
0218 hdmi_tx_venc_port: port@0 {
0219 reg = <0>;
0220
0221 hdmi_tx_in: endpoint {
0222 remote-endpoint = <&hdmi_tx_out>;
0223 };
0224 };
0225
0226 /* TMDS Output */
0227 hdmi_tx_tmds_port: port@1 {
0228 reg = <1>;
0229 };
0230 };
0231
0232 apb_efuse: bus@30000 {
0233 compatible = "simple-bus";
0234 reg = <0x0 0x30000 0x0 0x2000>;
0235 #address-cells = <2>;
0236 #size-cells = <2>;
0237 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
0238
0239 hwrng: rng@218 {
0240 compatible = "amlogic,meson-rng";
0241 reg = <0x0 0x218 0x0 0x4>;
0242 clocks = <&clkc CLKID_RNG0>;
0243 clock-names = "core";
0244 };
0245 };
0246
0247 acodec: audio-controller@32000 {
0248 compatible = "amlogic,t9015";
0249 reg = <0x0 0x32000 0x0 0x14>;
0250 #sound-dai-cells = <0>;
0251 sound-name-prefix = "ACODEC";
0252 clocks = <&clkc CLKID_AUDIO_CODEC>;
0253 clock-names = "pclk";
0254 resets = <&reset RESET_AUDIO_CODEC>;
0255 status = "disabled";
0256 };
0257
0258 periphs: bus@34400 {
0259 compatible = "simple-bus";
0260 reg = <0x0 0x34400 0x0 0x400>;
0261 #address-cells = <2>;
0262 #size-cells = <2>;
0263 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
0264
0265 periphs_pinctrl: pinctrl@40 {
0266 compatible = "amlogic,meson-g12a-periphs-pinctrl";
0267 #address-cells = <2>;
0268 #size-cells = <2>;
0269 ranges;
0270
0271 gpio: bank@40 {
0272 reg = <0x0 0x40 0x0 0x4c>,
0273 <0x0 0xe8 0x0 0x18>,
0274 <0x0 0x120 0x0 0x18>,
0275 <0x0 0x2c0 0x0 0x40>,
0276 <0x0 0x340 0x0 0x1c>;
0277 reg-names = "gpio",
0278 "pull",
0279 "pull-enable",
0280 "mux",
0281 "ds";
0282 gpio-controller;
0283 #gpio-cells = <2>;
0284 gpio-ranges = <&periphs_pinctrl 0 0 86>;
0285 };
0286
0287 cec_ao_a_h_pins: cec_ao_a_h {
0288 mux {
0289 groups = "cec_ao_a_h";
0290 function = "cec_ao_a_h";
0291 bias-disable;
0292 };
0293 };
0294
0295 cec_ao_b_h_pins: cec_ao_b_h {
0296 mux {
0297 groups = "cec_ao_b_h";
0298 function = "cec_ao_b_h";
0299 bias-disable;
0300 };
0301 };
0302
0303 emmc_ctrl_pins: emmc-ctrl {
0304 mux-0 {
0305 groups = "emmc_cmd";
0306 function = "emmc";
0307 bias-pull-up;
0308 drive-strength-microamp = <4000>;
0309 };
0310
0311 mux-1 {
0312 groups = "emmc_clk";
0313 function = "emmc";
0314 bias-disable;
0315 drive-strength-microamp = <4000>;
0316 };
0317 };
0318
0319 emmc_data_4b_pins: emmc-data-4b {
0320 mux-0 {
0321 groups = "emmc_nand_d0",
0322 "emmc_nand_d1",
0323 "emmc_nand_d2",
0324 "emmc_nand_d3";
0325 function = "emmc";
0326 bias-pull-up;
0327 drive-strength-microamp = <4000>;
0328 };
0329 };
0330
0331 emmc_data_8b_pins: emmc-data-8b {
0332 mux-0 {
0333 groups = "emmc_nand_d0",
0334 "emmc_nand_d1",
0335 "emmc_nand_d2",
0336 "emmc_nand_d3",
0337 "emmc_nand_d4",
0338 "emmc_nand_d5",
0339 "emmc_nand_d6",
0340 "emmc_nand_d7";
0341 function = "emmc";
0342 bias-pull-up;
0343 drive-strength-microamp = <4000>;
0344 };
0345 };
0346
0347 emmc_ds_pins: emmc-ds {
0348 mux {
0349 groups = "emmc_nand_ds";
0350 function = "emmc";
0351 bias-pull-down;
0352 drive-strength-microamp = <4000>;
0353 };
0354 };
0355
0356 emmc_clk_gate_pins: emmc_clk_gate {
0357 mux {
0358 groups = "BOOT_8";
0359 function = "gpio_periphs";
0360 bias-pull-down;
0361 drive-strength-microamp = <4000>;
0362 };
0363 };
0364
0365 hdmitx_ddc_pins: hdmitx_ddc {
0366 mux {
0367 groups = "hdmitx_sda",
0368 "hdmitx_sck";
0369 function = "hdmitx";
0370 bias-disable;
0371 drive-strength-microamp = <4000>;
0372 };
0373 };
0374
0375 hdmitx_hpd_pins: hdmitx_hpd {
0376 mux {
0377 groups = "hdmitx_hpd_in";
0378 function = "hdmitx";
0379 bias-disable;
0380 };
0381 };
0382
0383
0384 i2c0_sda_c_pins: i2c0-sda-c {
0385 mux {
0386 groups = "i2c0_sda_c";
0387 function = "i2c0";
0388 bias-disable;
0389 drive-strength-microamp = <3000>;
0390
0391 };
0392 };
0393
0394 i2c0_sck_c_pins: i2c0-sck-c {
0395 mux {
0396 groups = "i2c0_sck_c";
0397 function = "i2c0";
0398 bias-disable;
0399 drive-strength-microamp = <3000>;
0400 };
0401 };
0402
0403 i2c0_sda_z0_pins: i2c0-sda-z0 {
0404 mux {
0405 groups = "i2c0_sda_z0";
0406 function = "i2c0";
0407 bias-disable;
0408 drive-strength-microamp = <3000>;
0409 };
0410 };
0411
0412 i2c0_sck_z1_pins: i2c0-sck-z1 {
0413 mux {
0414 groups = "i2c0_sck_z1";
0415 function = "i2c0";
0416 bias-disable;
0417 drive-strength-microamp = <3000>;
0418 };
0419 };
0420
0421 i2c0_sda_z7_pins: i2c0-sda-z7 {
0422 mux {
0423 groups = "i2c0_sda_z7";
0424 function = "i2c0";
0425 bias-disable;
0426 drive-strength-microamp = <3000>;
0427 };
0428 };
0429
0430 i2c0_sda_z8_pins: i2c0-sda-z8 {
0431 mux {
0432 groups = "i2c0_sda_z8";
0433 function = "i2c0";
0434 bias-disable;
0435 drive-strength-microamp = <3000>;
0436 };
0437 };
0438
0439 i2c1_sda_x_pins: i2c1-sda-x {
0440 mux {
0441 groups = "i2c1_sda_x";
0442 function = "i2c1";
0443 bias-disable;
0444 drive-strength-microamp = <3000>;
0445 };
0446 };
0447
0448 i2c1_sck_x_pins: i2c1-sck-x {
0449 mux {
0450 groups = "i2c1_sck_x";
0451 function = "i2c1";
0452 bias-disable;
0453 drive-strength-microamp = <3000>;
0454 };
0455 };
0456
0457 i2c1_sda_h2_pins: i2c1-sda-h2 {
0458 mux {
0459 groups = "i2c1_sda_h2";
0460 function = "i2c1";
0461 bias-disable;
0462 drive-strength-microamp = <3000>;
0463 };
0464 };
0465
0466 i2c1_sck_h3_pins: i2c1-sck-h3 {
0467 mux {
0468 groups = "i2c1_sck_h3";
0469 function = "i2c1";
0470 bias-disable;
0471 drive-strength-microamp = <3000>;
0472 };
0473 };
0474
0475 i2c1_sda_h6_pins: i2c1-sda-h6 {
0476 mux {
0477 groups = "i2c1_sda_h6";
0478 function = "i2c1";
0479 bias-disable;
0480 drive-strength-microamp = <3000>;
0481 };
0482 };
0483
0484 i2c1_sck_h7_pins: i2c1-sck-h7 {
0485 mux {
0486 groups = "i2c1_sck_h7";
0487 function = "i2c1";
0488 bias-disable;
0489 drive-strength-microamp = <3000>;
0490 };
0491 };
0492
0493 i2c2_sda_x_pins: i2c2-sda-x {
0494 mux {
0495 groups = "i2c2_sda_x";
0496 function = "i2c2";
0497 bias-disable;
0498 drive-strength-microamp = <3000>;
0499 };
0500 };
0501
0502 i2c2_sck_x_pins: i2c2-sck-x {
0503 mux {
0504 groups = "i2c2_sck_x";
0505 function = "i2c2";
0506 bias-disable;
0507 drive-strength-microamp = <3000>;
0508 };
0509 };
0510
0511 i2c2_sda_z_pins: i2c2-sda-z {
0512 mux {
0513 groups = "i2c2_sda_z";
0514 function = "i2c2";
0515 bias-disable;
0516 drive-strength-microamp = <3000>;
0517 };
0518 };
0519
0520 i2c2_sck_z_pins: i2c2-sck-z {
0521 mux {
0522 groups = "i2c2_sck_z";
0523 function = "i2c2";
0524 bias-disable;
0525 drive-strength-microamp = <3000>;
0526 };
0527 };
0528
0529 i2c3_sda_h_pins: i2c3-sda-h {
0530 mux {
0531 groups = "i2c3_sda_h";
0532 function = "i2c3";
0533 bias-disable;
0534 drive-strength-microamp = <3000>;
0535 };
0536 };
0537
0538 i2c3_sck_h_pins: i2c3-sck-h {
0539 mux {
0540 groups = "i2c3_sck_h";
0541 function = "i2c3";
0542 bias-disable;
0543 drive-strength-microamp = <3000>;
0544 };
0545 };
0546
0547 i2c3_sda_a_pins: i2c3-sda-a {
0548 mux {
0549 groups = "i2c3_sda_a";
0550 function = "i2c3";
0551 bias-disable;
0552 drive-strength-microamp = <3000>;
0553 };
0554 };
0555
0556 i2c3_sck_a_pins: i2c3-sck-a {
0557 mux {
0558 groups = "i2c3_sck_a";
0559 function = "i2c3";
0560 bias-disable;
0561 drive-strength-microamp = <3000>;
0562 };
0563 };
0564
0565 mclk0_a_pins: mclk0-a {
0566 mux {
0567 groups = "mclk0_a";
0568 function = "mclk0";
0569 bias-disable;
0570 drive-strength-microamp = <3000>;
0571 };
0572 };
0573
0574 mclk1_a_pins: mclk1-a {
0575 mux {
0576 groups = "mclk1_a";
0577 function = "mclk1";
0578 bias-disable;
0579 drive-strength-microamp = <3000>;
0580 };
0581 };
0582
0583 mclk1_x_pins: mclk1-x {
0584 mux {
0585 groups = "mclk1_x";
0586 function = "mclk1";
0587 bias-disable;
0588 drive-strength-microamp = <3000>;
0589 };
0590 };
0591
0592 mclk1_z_pins: mclk1-z {
0593 mux {
0594 groups = "mclk1_z";
0595 function = "mclk1";
0596 bias-disable;
0597 drive-strength-microamp = <3000>;
0598 };
0599 };
0600
0601 nor_pins: nor {
0602 mux {
0603 groups = "nor_d",
0604 "nor_q",
0605 "nor_c",
0606 "nor_cs";
0607 function = "nor";
0608 bias-disable;
0609 };
0610 };
0611
0612 pdm_din0_a_pins: pdm-din0-a {
0613 mux {
0614 groups = "pdm_din0_a";
0615 function = "pdm";
0616 bias-disable;
0617 };
0618 };
0619
0620 pdm_din0_c_pins: pdm-din0-c {
0621 mux {
0622 groups = "pdm_din0_c";
0623 function = "pdm";
0624 bias-disable;
0625 };
0626 };
0627
0628 pdm_din0_x_pins: pdm-din0-x {
0629 mux {
0630 groups = "pdm_din0_x";
0631 function = "pdm";
0632 bias-disable;
0633 };
0634 };
0635
0636 pdm_din0_z_pins: pdm-din0-z {
0637 mux {
0638 groups = "pdm_din0_z";
0639 function = "pdm";
0640 bias-disable;
0641 };
0642 };
0643
0644 pdm_din1_a_pins: pdm-din1-a {
0645 mux {
0646 groups = "pdm_din1_a";
0647 function = "pdm";
0648 bias-disable;
0649 };
0650 };
0651
0652 pdm_din1_c_pins: pdm-din1-c {
0653 mux {
0654 groups = "pdm_din1_c";
0655 function = "pdm";
0656 bias-disable;
0657 };
0658 };
0659
0660 pdm_din1_x_pins: pdm-din1-x {
0661 mux {
0662 groups = "pdm_din1_x";
0663 function = "pdm";
0664 bias-disable;
0665 };
0666 };
0667
0668 pdm_din1_z_pins: pdm-din1-z {
0669 mux {
0670 groups = "pdm_din1_z";
0671 function = "pdm";
0672 bias-disable;
0673 };
0674 };
0675
0676 pdm_din2_a_pins: pdm-din2-a {
0677 mux {
0678 groups = "pdm_din2_a";
0679 function = "pdm";
0680 bias-disable;
0681 };
0682 };
0683
0684 pdm_din2_c_pins: pdm-din2-c {
0685 mux {
0686 groups = "pdm_din2_c";
0687 function = "pdm";
0688 bias-disable;
0689 };
0690 };
0691
0692 pdm_din2_x_pins: pdm-din2-x {
0693 mux {
0694 groups = "pdm_din2_x";
0695 function = "pdm";
0696 bias-disable;
0697 };
0698 };
0699
0700 pdm_din2_z_pins: pdm-din2-z {
0701 mux {
0702 groups = "pdm_din2_z";
0703 function = "pdm";
0704 bias-disable;
0705 };
0706 };
0707
0708 pdm_din3_a_pins: pdm-din3-a {
0709 mux {
0710 groups = "pdm_din3_a";
0711 function = "pdm";
0712 bias-disable;
0713 };
0714 };
0715
0716 pdm_din3_c_pins: pdm-din3-c {
0717 mux {
0718 groups = "pdm_din3_c";
0719 function = "pdm";
0720 bias-disable;
0721 };
0722 };
0723
0724 pdm_din3_x_pins: pdm-din3-x {
0725 mux {
0726 groups = "pdm_din3_x";
0727 function = "pdm";
0728 bias-disable;
0729 };
0730 };
0731
0732 pdm_din3_z_pins: pdm-din3-z {
0733 mux {
0734 groups = "pdm_din3_z";
0735 function = "pdm";
0736 bias-disable;
0737 };
0738 };
0739
0740 pdm_dclk_a_pins: pdm-dclk-a {
0741 mux {
0742 groups = "pdm_dclk_a";
0743 function = "pdm";
0744 bias-disable;
0745 drive-strength-microamp = <500>;
0746 };
0747 };
0748
0749 pdm_dclk_c_pins: pdm-dclk-c {
0750 mux {
0751 groups = "pdm_dclk_c";
0752 function = "pdm";
0753 bias-disable;
0754 drive-strength-microamp = <500>;
0755 };
0756 };
0757
0758 pdm_dclk_x_pins: pdm-dclk-x {
0759 mux {
0760 groups = "pdm_dclk_x";
0761 function = "pdm";
0762 bias-disable;
0763 drive-strength-microamp = <500>;
0764 };
0765 };
0766
0767 pdm_dclk_z_pins: pdm-dclk-z {
0768 mux {
0769 groups = "pdm_dclk_z";
0770 function = "pdm";
0771 bias-disable;
0772 drive-strength-microamp = <500>;
0773 };
0774 };
0775
0776 pwm_a_pins: pwm-a {
0777 mux {
0778 groups = "pwm_a";
0779 function = "pwm_a";
0780 bias-disable;
0781 };
0782 };
0783
0784 pwm_b_x7_pins: pwm-b-x7 {
0785 mux {
0786 groups = "pwm_b_x7";
0787 function = "pwm_b";
0788 bias-disable;
0789 };
0790 };
0791
0792 pwm_b_x19_pins: pwm-b-x19 {
0793 mux {
0794 groups = "pwm_b_x19";
0795 function = "pwm_b";
0796 bias-disable;
0797 };
0798 };
0799
0800 pwm_c_c_pins: pwm-c-c {
0801 mux {
0802 groups = "pwm_c_c";
0803 function = "pwm_c";
0804 bias-disable;
0805 };
0806 };
0807
0808 pwm_c_x5_pins: pwm-c-x5 {
0809 mux {
0810 groups = "pwm_c_x5";
0811 function = "pwm_c";
0812 bias-disable;
0813 };
0814 };
0815
0816 pwm_c_x8_pins: pwm-c-x8 {
0817 mux {
0818 groups = "pwm_c_x8";
0819 function = "pwm_c";
0820 bias-disable;
0821 };
0822 };
0823
0824 pwm_d_x3_pins: pwm-d-x3 {
0825 mux {
0826 groups = "pwm_d_x3";
0827 function = "pwm_d";
0828 bias-disable;
0829 };
0830 };
0831
0832 pwm_d_x6_pins: pwm-d-x6 {
0833 mux {
0834 groups = "pwm_d_x6";
0835 function = "pwm_d";
0836 bias-disable;
0837 };
0838 };
0839
0840 pwm_e_pins: pwm-e {
0841 mux {
0842 groups = "pwm_e";
0843 function = "pwm_e";
0844 bias-disable;
0845 };
0846 };
0847
0848 pwm_f_z_pins: pwm-f-z {
0849 mux {
0850 groups = "pwm_f_z";
0851 function = "pwm_f";
0852 bias-disable;
0853 };
0854 };
0855
0856 pwm_f_a_pins: pwm-f-a {
0857 mux {
0858 groups = "pwm_f_a";
0859 function = "pwm_f";
0860 bias-disable;
0861 };
0862 };
0863
0864 pwm_f_x_pins: pwm-f-x {
0865 mux {
0866 groups = "pwm_f_x";
0867 function = "pwm_f";
0868 bias-disable;
0869 };
0870 };
0871
0872 pwm_f_h_pins: pwm-f-h {
0873 mux {
0874 groups = "pwm_f_h";
0875 function = "pwm_f";
0876 bias-disable;
0877 };
0878 };
0879
0880 sdcard_c_pins: sdcard_c {
0881 mux-0 {
0882 groups = "sdcard_d0_c",
0883 "sdcard_d1_c",
0884 "sdcard_d2_c",
0885 "sdcard_d3_c",
0886 "sdcard_cmd_c";
0887 function = "sdcard";
0888 bias-pull-up;
0889 drive-strength-microamp = <4000>;
0890 };
0891
0892 mux-1 {
0893 groups = "sdcard_clk_c";
0894 function = "sdcard";
0895 bias-disable;
0896 drive-strength-microamp = <4000>;
0897 };
0898 };
0899
0900 sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
0901 mux {
0902 groups = "GPIOC_4";
0903 function = "gpio_periphs";
0904 bias-pull-down;
0905 drive-strength-microamp = <4000>;
0906 };
0907 };
0908
0909 sdcard_z_pins: sdcard_z {
0910 mux-0 {
0911 groups = "sdcard_d0_z",
0912 "sdcard_d1_z",
0913 "sdcard_d2_z",
0914 "sdcard_d3_z",
0915 "sdcard_cmd_z";
0916 function = "sdcard";
0917 bias-pull-up;
0918 drive-strength-microamp = <4000>;
0919 };
0920
0921 mux-1 {
0922 groups = "sdcard_clk_z";
0923 function = "sdcard";
0924 bias-disable;
0925 drive-strength-microamp = <4000>;
0926 };
0927 };
0928
0929 sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
0930 mux {
0931 groups = "GPIOZ_6";
0932 function = "gpio_periphs";
0933 bias-pull-down;
0934 drive-strength-microamp = <4000>;
0935 };
0936 };
0937
0938 sdio_pins: sdio {
0939 mux {
0940 groups = "sdio_d0",
0941 "sdio_d1",
0942 "sdio_d2",
0943 "sdio_d3",
0944 "sdio_clk",
0945 "sdio_cmd";
0946 function = "sdio";
0947 bias-disable;
0948 drive-strength-microamp = <4000>;
0949 };
0950 };
0951
0952 sdio_clk_gate_pins: sdio_clk_gate {
0953 mux {
0954 groups = "GPIOX_4";
0955 function = "gpio_periphs";
0956 bias-pull-down;
0957 drive-strength-microamp = <4000>;
0958 };
0959 };
0960
0961 spdif_in_a10_pins: spdif-in-a10 {
0962 mux {
0963 groups = "spdif_in_a10";
0964 function = "spdif_in";
0965 bias-disable;
0966 };
0967 };
0968
0969 spdif_in_a12_pins: spdif-in-a12 {
0970 mux {
0971 groups = "spdif_in_a12";
0972 function = "spdif_in";
0973 bias-disable;
0974 };
0975 };
0976
0977 spdif_in_h_pins: spdif-in-h {
0978 mux {
0979 groups = "spdif_in_h";
0980 function = "spdif_in";
0981 bias-disable;
0982 };
0983 };
0984
0985 spdif_out_h_pins: spdif-out-h {
0986 mux {
0987 groups = "spdif_out_h";
0988 function = "spdif_out";
0989 drive-strength-microamp = <500>;
0990 bias-disable;
0991 };
0992 };
0993
0994 spdif_out_a11_pins: spdif-out-a11 {
0995 mux {
0996 groups = "spdif_out_a11";
0997 function = "spdif_out";
0998 drive-strength-microamp = <500>;
0999 bias-disable;
1000 };
1001 };
1002
1003 spdif_out_a13_pins: spdif-out-a13 {
1004 mux {
1005 groups = "spdif_out_a13";
1006 function = "spdif_out";
1007 drive-strength-microamp = <500>;
1008 bias-disable;
1009 };
1010 };
1011
1012 spicc0_x_pins: spicc0-x {
1013 mux {
1014 groups = "spi0_mosi_x",
1015 "spi0_miso_x",
1016 "spi0_clk_x";
1017 function = "spi0";
1018 drive-strength-microamp = <4000>;
1019 bias-disable;
1020 };
1021 };
1022
1023 spicc0_ss0_x_pins: spicc0-ss0-x {
1024 mux {
1025 groups = "spi0_ss0_x";
1026 function = "spi0";
1027 drive-strength-microamp = <4000>;
1028 bias-disable;
1029 };
1030 };
1031
1032 spicc0_c_pins: spicc0-c {
1033 mux {
1034 groups = "spi0_mosi_c",
1035 "spi0_miso_c",
1036 "spi0_ss0_c",
1037 "spi0_clk_c";
1038 function = "spi0";
1039 drive-strength-microamp = <4000>;
1040 bias-disable;
1041 };
1042 };
1043
1044 spicc1_pins: spicc1 {
1045 mux {
1046 groups = "spi1_mosi",
1047 "spi1_miso",
1048 "spi1_clk";
1049 function = "spi1";
1050 drive-strength-microamp = <4000>;
1051 };
1052 };
1053
1054 spicc1_ss0_pins: spicc1-ss0 {
1055 mux {
1056 groups = "spi1_ss0";
1057 function = "spi1";
1058 drive-strength-microamp = <4000>;
1059 bias-disable;
1060 };
1061 };
1062
1063 tdm_a_din0_pins: tdm-a-din0 {
1064 mux {
1065 groups = "tdm_a_din0";
1066 function = "tdm_a";
1067 bias-disable;
1068 };
1069 };
1070
1071
1072 tdm_a_din1_pins: tdm-a-din1 {
1073 mux {
1074 groups = "tdm_a_din1";
1075 function = "tdm_a";
1076 bias-disable;
1077 };
1078 };
1079
1080 tdm_a_dout0_pins: tdm-a-dout0 {
1081 mux {
1082 groups = "tdm_a_dout0";
1083 function = "tdm_a";
1084 bias-disable;
1085 drive-strength-microamp = <3000>;
1086 };
1087 };
1088
1089 tdm_a_dout1_pins: tdm-a-dout1 {
1090 mux {
1091 groups = "tdm_a_dout1";
1092 function = "tdm_a";
1093 bias-disable;
1094 drive-strength-microamp = <3000>;
1095 };
1096 };
1097
1098 tdm_a_fs_pins: tdm-a-fs {
1099 mux {
1100 groups = "tdm_a_fs";
1101 function = "tdm_a";
1102 bias-disable;
1103 drive-strength-microamp = <3000>;
1104 };
1105 };
1106
1107 tdm_a_sclk_pins: tdm-a-sclk {
1108 mux {
1109 groups = "tdm_a_sclk";
1110 function = "tdm_a";
1111 bias-disable;
1112 drive-strength-microamp = <3000>;
1113 };
1114 };
1115
1116 tdm_a_slv_fs_pins: tdm-a-slv-fs {
1117 mux {
1118 groups = "tdm_a_slv_fs";
1119 function = "tdm_a";
1120 bias-disable;
1121 };
1122 };
1123
1124
1125 tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
1126 mux {
1127 groups = "tdm_a_slv_sclk";
1128 function = "tdm_a";
1129 bias-disable;
1130 };
1131 };
1132
1133 tdm_b_din0_pins: tdm-b-din0 {
1134 mux {
1135 groups = "tdm_b_din0";
1136 function = "tdm_b";
1137 bias-disable;
1138 };
1139 };
1140
1141 tdm_b_din1_pins: tdm-b-din1 {
1142 mux {
1143 groups = "tdm_b_din1";
1144 function = "tdm_b";
1145 bias-disable;
1146 };
1147 };
1148
1149 tdm_b_din2_pins: tdm-b-din2 {
1150 mux {
1151 groups = "tdm_b_din2";
1152 function = "tdm_b";
1153 bias-disable;
1154 };
1155 };
1156
1157 tdm_b_din3_a_pins: tdm-b-din3-a {
1158 mux {
1159 groups = "tdm_b_din3_a";
1160 function = "tdm_b";
1161 bias-disable;
1162 };
1163 };
1164
1165 tdm_b_din3_h_pins: tdm-b-din3-h {
1166 mux {
1167 groups = "tdm_b_din3_h";
1168 function = "tdm_b";
1169 bias-disable;
1170 };
1171 };
1172
1173 tdm_b_dout0_pins: tdm-b-dout0 {
1174 mux {
1175 groups = "tdm_b_dout0";
1176 function = "tdm_b";
1177 bias-disable;
1178 drive-strength-microamp = <3000>;
1179 };
1180 };
1181
1182 tdm_b_dout1_pins: tdm-b-dout1 {
1183 mux {
1184 groups = "tdm_b_dout1";
1185 function = "tdm_b";
1186 bias-disable;
1187 drive-strength-microamp = <3000>;
1188 };
1189 };
1190
1191 tdm_b_dout2_pins: tdm-b-dout2 {
1192 mux {
1193 groups = "tdm_b_dout2";
1194 function = "tdm_b";
1195 bias-disable;
1196 drive-strength-microamp = <3000>;
1197 };
1198 };
1199
1200 tdm_b_dout3_a_pins: tdm-b-dout3-a {
1201 mux {
1202 groups = "tdm_b_dout3_a";
1203 function = "tdm_b";
1204 bias-disable;
1205 drive-strength-microamp = <3000>;
1206 };
1207 };
1208
1209 tdm_b_dout3_h_pins: tdm-b-dout3-h {
1210 mux {
1211 groups = "tdm_b_dout3_h";
1212 function = "tdm_b";
1213 bias-disable;
1214 drive-strength-microamp = <3000>;
1215 };
1216 };
1217
1218 tdm_b_fs_pins: tdm-b-fs {
1219 mux {
1220 groups = "tdm_b_fs";
1221 function = "tdm_b";
1222 bias-disable;
1223 drive-strength-microamp = <3000>;
1224 };
1225 };
1226
1227 tdm_b_sclk_pins: tdm-b-sclk {
1228 mux {
1229 groups = "tdm_b_sclk";
1230 function = "tdm_b";
1231 bias-disable;
1232 drive-strength-microamp = <3000>;
1233 };
1234 };
1235
1236 tdm_b_slv_fs_pins: tdm-b-slv-fs {
1237 mux {
1238 groups = "tdm_b_slv_fs";
1239 function = "tdm_b";
1240 bias-disable;
1241 };
1242 };
1243
1244 tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
1245 mux {
1246 groups = "tdm_b_slv_sclk";
1247 function = "tdm_b";
1248 bias-disable;
1249 };
1250 };
1251
1252 tdm_c_din0_a_pins: tdm-c-din0-a {
1253 mux {
1254 groups = "tdm_c_din0_a";
1255 function = "tdm_c";
1256 bias-disable;
1257 };
1258 };
1259
1260 tdm_c_din0_z_pins: tdm-c-din0-z {
1261 mux {
1262 groups = "tdm_c_din0_z";
1263 function = "tdm_c";
1264 bias-disable;
1265 };
1266 };
1267
1268 tdm_c_din1_a_pins: tdm-c-din1-a {
1269 mux {
1270 groups = "tdm_c_din1_a";
1271 function = "tdm_c";
1272 bias-disable;
1273 };
1274 };
1275
1276 tdm_c_din1_z_pins: tdm-c-din1-z {
1277 mux {
1278 groups = "tdm_c_din1_z";
1279 function = "tdm_c";
1280 bias-disable;
1281 };
1282 };
1283
1284 tdm_c_din2_a_pins: tdm-c-din2-a {
1285 mux {
1286 groups = "tdm_c_din2_a";
1287 function = "tdm_c";
1288 bias-disable;
1289 };
1290 };
1291
1292 eth_leds_pins: eth-leds {
1293 mux {
1294 groups = "eth_link_led",
1295 "eth_act_led";
1296 function = "eth";
1297 bias-disable;
1298 };
1299 };
1300
1301 eth_pins: eth {
1302 mux {
1303 groups = "eth_mdio",
1304 "eth_mdc",
1305 "eth_rgmii_rx_clk",
1306 "eth_rx_dv",
1307 "eth_rxd0",
1308 "eth_rxd1",
1309 "eth_txen",
1310 "eth_txd0",
1311 "eth_txd1";
1312 function = "eth";
1313 drive-strength-microamp = <4000>;
1314 bias-disable;
1315 };
1316 };
1317
1318 eth_rgmii_pins: eth-rgmii {
1319 mux {
1320 groups = "eth_rxd2_rgmii",
1321 "eth_rxd3_rgmii",
1322 "eth_rgmii_tx_clk",
1323 "eth_txd2_rgmii",
1324 "eth_txd3_rgmii";
1325 function = "eth";
1326 drive-strength-microamp = <4000>;
1327 bias-disable;
1328 };
1329 };
1330
1331 tdm_c_din2_z_pins: tdm-c-din2-z {
1332 mux {
1333 groups = "tdm_c_din2_z";
1334 function = "tdm_c";
1335 bias-disable;
1336 };
1337 };
1338
1339 tdm_c_din3_a_pins: tdm-c-din3-a {
1340 mux {
1341 groups = "tdm_c_din3_a";
1342 function = "tdm_c";
1343 bias-disable;
1344 };
1345 };
1346
1347 tdm_c_din3_z_pins: tdm-c-din3-z {
1348 mux {
1349 groups = "tdm_c_din3_z";
1350 function = "tdm_c";
1351 bias-disable;
1352 };
1353 };
1354
1355 tdm_c_dout0_a_pins: tdm-c-dout0-a {
1356 mux {
1357 groups = "tdm_c_dout0_a";
1358 function = "tdm_c";
1359 bias-disable;
1360 drive-strength-microamp = <3000>;
1361 };
1362 };
1363
1364 tdm_c_dout0_z_pins: tdm-c-dout0-z {
1365 mux {
1366 groups = "tdm_c_dout0_z";
1367 function = "tdm_c";
1368 bias-disable;
1369 drive-strength-microamp = <3000>;
1370 };
1371 };
1372
1373 tdm_c_dout1_a_pins: tdm-c-dout1-a {
1374 mux {
1375 groups = "tdm_c_dout1_a";
1376 function = "tdm_c";
1377 bias-disable;
1378 drive-strength-microamp = <3000>;
1379 };
1380 };
1381
1382 tdm_c_dout1_z_pins: tdm-c-dout1-z {
1383 mux {
1384 groups = "tdm_c_dout1_z";
1385 function = "tdm_c";
1386 bias-disable;
1387 drive-strength-microamp = <3000>;
1388 };
1389 };
1390
1391 tdm_c_dout2_a_pins: tdm-c-dout2-a {
1392 mux {
1393 groups = "tdm_c_dout2_a";
1394 function = "tdm_c";
1395 bias-disable;
1396 drive-strength-microamp = <3000>;
1397 };
1398 };
1399
1400 tdm_c_dout2_z_pins: tdm-c-dout2-z {
1401 mux {
1402 groups = "tdm_c_dout2_z";
1403 function = "tdm_c";
1404 bias-disable;
1405 drive-strength-microamp = <3000>;
1406 };
1407 };
1408
1409 tdm_c_dout3_a_pins: tdm-c-dout3-a {
1410 mux {
1411 groups = "tdm_c_dout3_a";
1412 function = "tdm_c";
1413 bias-disable;
1414 drive-strength-microamp = <3000>;
1415 };
1416 };
1417
1418 tdm_c_dout3_z_pins: tdm-c-dout3-z {
1419 mux {
1420 groups = "tdm_c_dout3_z";
1421 function = "tdm_c";
1422 bias-disable;
1423 drive-strength-microamp = <3000>;
1424 };
1425 };
1426
1427 tdm_c_fs_a_pins: tdm-c-fs-a {
1428 mux {
1429 groups = "tdm_c_fs_a";
1430 function = "tdm_c";
1431 bias-disable;
1432 drive-strength-microamp = <3000>;
1433 };
1434 };
1435
1436 tdm_c_fs_z_pins: tdm-c-fs-z {
1437 mux {
1438 groups = "tdm_c_fs_z";
1439 function = "tdm_c";
1440 bias-disable;
1441 drive-strength-microamp = <3000>;
1442 };
1443 };
1444
1445 tdm_c_sclk_a_pins: tdm-c-sclk-a {
1446 mux {
1447 groups = "tdm_c_sclk_a";
1448 function = "tdm_c";
1449 bias-disable;
1450 drive-strength-microamp = <3000>;
1451 };
1452 };
1453
1454 tdm_c_sclk_z_pins: tdm-c-sclk-z {
1455 mux {
1456 groups = "tdm_c_sclk_z";
1457 function = "tdm_c";
1458 bias-disable;
1459 drive-strength-microamp = <3000>;
1460 };
1461 };
1462
1463 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
1464 mux {
1465 groups = "tdm_c_slv_fs_a";
1466 function = "tdm_c";
1467 bias-disable;
1468 };
1469 };
1470
1471 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
1472 mux {
1473 groups = "tdm_c_slv_fs_z";
1474 function = "tdm_c";
1475 bias-disable;
1476 };
1477 };
1478
1479 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
1480 mux {
1481 groups = "tdm_c_slv_sclk_a";
1482 function = "tdm_c";
1483 bias-disable;
1484 };
1485 };
1486
1487 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
1488 mux {
1489 groups = "tdm_c_slv_sclk_z";
1490 function = "tdm_c";
1491 bias-disable;
1492 };
1493 };
1494
1495 uart_a_pins: uart-a {
1496 mux {
1497 groups = "uart_a_tx",
1498 "uart_a_rx";
1499 function = "uart_a";
1500 bias-disable;
1501 };
1502 };
1503
1504 uart_a_cts_rts_pins: uart-a-cts-rts {
1505 mux {
1506 groups = "uart_a_cts",
1507 "uart_a_rts";
1508 function = "uart_a";
1509 bias-disable;
1510 };
1511 };
1512
1513 uart_b_pins: uart-b {
1514 mux {
1515 groups = "uart_b_tx",
1516 "uart_b_rx";
1517 function = "uart_b";
1518 bias-disable;
1519 };
1520 };
1521
1522 uart_c_pins: uart-c {
1523 mux {
1524 groups = "uart_c_tx",
1525 "uart_c_rx";
1526 function = "uart_c";
1527 bias-disable;
1528 };
1529 };
1530
1531 uart_c_cts_rts_pins: uart-c-cts-rts {
1532 mux {
1533 groups = "uart_c_cts",
1534 "uart_c_rts";
1535 function = "uart_c";
1536 bias-disable;
1537 };
1538 };
1539 };
1540 };
1541
1542 cpu_temp: temperature-sensor@34800 {
1543 compatible = "amlogic,g12a-cpu-thermal",
1544 "amlogic,g12a-thermal";
1545 reg = <0x0 0x34800 0x0 0x50>;
1546 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
1547 clocks = <&clkc CLKID_TS>;
1548 #thermal-sensor-cells = <0>;
1549 amlogic,ao-secure = <&sec_AO>;
1550 };
1551
1552 ddr_temp: temperature-sensor@34c00 {
1553 compatible = "amlogic,g12a-ddr-thermal",
1554 "amlogic,g12a-thermal";
1555 reg = <0x0 0x34c00 0x0 0x50>;
1556 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
1557 clocks = <&clkc CLKID_TS>;
1558 #thermal-sensor-cells = <0>;
1559 amlogic,ao-secure = <&sec_AO>;
1560 };
1561
1562 usb2_phy0: phy@36000 {
1563 compatible = "amlogic,g12a-usb2-phy";
1564 reg = <0x0 0x36000 0x0 0x2000>;
1565 clocks = <&xtal>;
1566 clock-names = "xtal";
1567 resets = <&reset RESET_USB_PHY20>;
1568 reset-names = "phy";
1569 #phy-cells = <0>;
1570 };
1571
1572 dmc: bus@38000 {
1573 compatible = "simple-bus";
1574 reg = <0x0 0x38000 0x0 0x400>;
1575 #address-cells = <2>;
1576 #size-cells = <2>;
1577 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
1578
1579 canvas: video-lut@48 {
1580 compatible = "amlogic,canvas";
1581 reg = <0x0 0x48 0x0 0x14>;
1582 };
1583 };
1584
1585 usb2_phy1: phy@3a000 {
1586 compatible = "amlogic,g12a-usb2-phy";
1587 reg = <0x0 0x3a000 0x0 0x2000>;
1588 clocks = <&xtal>;
1589 clock-names = "xtal";
1590 resets = <&reset RESET_USB_PHY21>;
1591 reset-names = "phy";
1592 #phy-cells = <0>;
1593 };
1594
1595 hiu: bus@3c000 {
1596 compatible = "simple-bus";
1597 reg = <0x0 0x3c000 0x0 0x1400>;
1598 #address-cells = <2>;
1599 #size-cells = <2>;
1600 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
1601
1602 hhi: system-controller@0 {
1603 compatible = "amlogic,meson-gx-hhi-sysctrl",
1604 "simple-mfd", "syscon";
1605 reg = <0 0 0 0x400>;
1606
1607 clkc: clock-controller {
1608 compatible = "amlogic,g12a-clkc";
1609 #clock-cells = <1>;
1610 clocks = <&xtal>;
1611 clock-names = "xtal";
1612 };
1613
1614 pwrc: power-controller {
1615 compatible = "amlogic,meson-g12a-pwrc";
1616 #power-domain-cells = <1>;
1617 amlogic,ao-sysctrl = <&rti>;
1618 resets = <&reset RESET_VIU>,
1619 <&reset RESET_VENC>,
1620 <&reset RESET_VCBUS>,
1621 <&reset RESET_BT656>,
1622 <&reset RESET_RDMA>,
1623 <&reset RESET_VENCI>,
1624 <&reset RESET_VENCP>,
1625 <&reset RESET_VDAC>,
1626 <&reset RESET_VDI6>,
1627 <&reset RESET_VENCL>,
1628 <&reset RESET_VID_LOCK>;
1629 reset-names = "viu", "venc", "vcbus", "bt656",
1630 "rdma", "venci", "vencp", "vdac",
1631 "vdi6", "vencl", "vid_lock";
1632 clocks = <&clkc CLKID_VPU>,
1633 <&clkc CLKID_VAPB>;
1634 clock-names = "vpu", "vapb";
1635 /*
1636 * VPU clocking is provided by two identical clock paths
1637 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1638 * free mux to safely change frequency while running.
1639 * Same for VAPB but with a final gate after the glitch free mux.
1640 */
1641 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1642 <&clkc CLKID_VPU_0>,
1643 <&clkc CLKID_VPU>, /* Glitch free mux */
1644 <&clkc CLKID_VAPB_0_SEL>,
1645 <&clkc CLKID_VAPB_0>,
1646 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1647 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
1648 <0>, /* Do Nothing */
1649 <&clkc CLKID_VPU_0>,
1650 <&clkc CLKID_FCLK_DIV4>,
1651 <0>, /* Do Nothing */
1652 <&clkc CLKID_VAPB_0>;
1653 assigned-clock-rates = <0>, /* Do Nothing */
1654 <666666666>,
1655 <0>, /* Do Nothing */
1656 <0>, /* Do Nothing */
1657 <250000000>,
1658 <0>; /* Do Nothing */
1659 };
1660 };
1661 };
1662
1663 usb3_pcie_phy: phy@46000 {
1664 compatible = "amlogic,g12a-usb3-pcie-phy";
1665 reg = <0x0 0x46000 0x0 0x2000>;
1666 clocks = <&clkc CLKID_PCIE_PLL>;
1667 clock-names = "ref_clk";
1668 resets = <&reset RESET_PCIE_PHY>;
1669 reset-names = "phy";
1670 assigned-clocks = <&clkc CLKID_PCIE_PLL>;
1671 assigned-clock-rates = <100000000>;
1672 #phy-cells = <1>;
1673 };
1674
1675 eth_phy: mdio-multiplexer@4c000 {
1676 compatible = "amlogic,g12a-mdio-mux";
1677 reg = <0x0 0x4c000 0x0 0xa4>;
1678 clocks = <&clkc CLKID_ETH_PHY>,
1679 <&xtal>,
1680 <&clkc CLKID_MPLL_50M>;
1681 clock-names = "pclk", "clkin0", "clkin1";
1682 mdio-parent-bus = <&mdio0>;
1683 #address-cells = <1>;
1684 #size-cells = <0>;
1685
1686 ext_mdio: mdio@0 {
1687 reg = <0>;
1688 #address-cells = <1>;
1689 #size-cells = <0>;
1690 };
1691
1692 int_mdio: mdio@1 {
1693 reg = <1>;
1694 #address-cells = <1>;
1695 #size-cells = <0>;
1696
1697 internal_ephy: ethernet_phy@8 {
1698 compatible = "ethernet-phy-id0180.3301",
1699 "ethernet-phy-ieee802.3-c22";
1700 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1701 reg = <8>;
1702 max-speed = <100>;
1703 };
1704 };
1705 };
1706 };
1707
1708 aobus: bus@ff800000 {
1709 compatible = "simple-bus";
1710 reg = <0x0 0xff800000 0x0 0x100000>;
1711 #address-cells = <2>;
1712 #size-cells = <2>;
1713 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1714
1715 rti: sys-ctrl@0 {
1716 compatible = "amlogic,meson-gx-ao-sysctrl",
1717 "simple-mfd", "syscon";
1718 reg = <0x0 0x0 0x0 0x100>;
1719 #address-cells = <2>;
1720 #size-cells = <2>;
1721 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
1722
1723 clkc_AO: clock-controller {
1724 compatible = "amlogic,meson-g12a-aoclkc";
1725 #clock-cells = <1>;
1726 #reset-cells = <1>;
1727 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1728 clock-names = "xtal", "mpeg-clk";
1729 };
1730
1731 ao_pinctrl: pinctrl@14 {
1732 compatible = "amlogic,meson-g12a-aobus-pinctrl";
1733 #address-cells = <2>;
1734 #size-cells = <2>;
1735 ranges;
1736
1737 gpio_ao: bank@14 {
1738 reg = <0x0 0x14 0x0 0x8>,
1739 <0x0 0x1c 0x0 0x8>,
1740 <0x0 0x24 0x0 0x14>;
1741 reg-names = "mux",
1742 "ds",
1743 "gpio";
1744 gpio-controller;
1745 #gpio-cells = <2>;
1746 gpio-ranges = <&ao_pinctrl 0 0 15>;
1747 };
1748
1749 i2c_ao_sck_pins: i2c_ao_sck_pins {
1750 mux {
1751 groups = "i2c_ao_sck";
1752 function = "i2c_ao";
1753 bias-disable;
1754 drive-strength-microamp = <3000>;
1755 };
1756 };
1757
1758 i2c_ao_sda_pins: i2c_ao_sda {
1759 mux {
1760 groups = "i2c_ao_sda";
1761 function = "i2c_ao";
1762 bias-disable;
1763 drive-strength-microamp = <3000>;
1764 };
1765 };
1766
1767 i2c_ao_sck_e_pins: i2c_ao_sck_e {
1768 mux {
1769 groups = "i2c_ao_sck_e";
1770 function = "i2c_ao";
1771 bias-disable;
1772 drive-strength-microamp = <3000>;
1773 };
1774 };
1775
1776 i2c_ao_sda_e_pins: i2c_ao_sda_e {
1777 mux {
1778 groups = "i2c_ao_sda_e";
1779 function = "i2c_ao";
1780 bias-disable;
1781 drive-strength-microamp = <3000>;
1782 };
1783 };
1784
1785 mclk0_ao_pins: mclk0-ao {
1786 mux {
1787 groups = "mclk0_ao";
1788 function = "mclk0_ao";
1789 bias-disable;
1790 drive-strength-microamp = <3000>;
1791 };
1792 };
1793
1794 tdm_ao_b_din0_pins: tdm-ao-b-din0 {
1795 mux {
1796 groups = "tdm_ao_b_din0";
1797 function = "tdm_ao_b";
1798 bias-disable;
1799 };
1800 };
1801
1802 spdif_ao_out_pins: spdif-ao-out {
1803 mux {
1804 groups = "spdif_ao_out";
1805 function = "spdif_ao_out";
1806 drive-strength-microamp = <500>;
1807 bias-disable;
1808 };
1809 };
1810
1811 tdm_ao_b_din1_pins: tdm-ao-b-din1 {
1812 mux {
1813 groups = "tdm_ao_b_din1";
1814 function = "tdm_ao_b";
1815 bias-disable;
1816 };
1817 };
1818
1819 tdm_ao_b_din2_pins: tdm-ao-b-din2 {
1820 mux {
1821 groups = "tdm_ao_b_din2";
1822 function = "tdm_ao_b";
1823 bias-disable;
1824 };
1825 };
1826
1827 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
1828 mux {
1829 groups = "tdm_ao_b_dout0";
1830 function = "tdm_ao_b";
1831 bias-disable;
1832 drive-strength-microamp = <3000>;
1833 };
1834 };
1835
1836 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
1837 mux {
1838 groups = "tdm_ao_b_dout1";
1839 function = "tdm_ao_b";
1840 bias-disable;
1841 drive-strength-microamp = <3000>;
1842 };
1843 };
1844
1845 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
1846 mux {
1847 groups = "tdm_ao_b_dout2";
1848 function = "tdm_ao_b";
1849 bias-disable;
1850 drive-strength-microamp = <3000>;
1851 };
1852 };
1853
1854 tdm_ao_b_fs_pins: tdm-ao-b-fs {
1855 mux {
1856 groups = "tdm_ao_b_fs";
1857 function = "tdm_ao_b";
1858 bias-disable;
1859 drive-strength-microamp = <3000>;
1860 };
1861 };
1862
1863 tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
1864 mux {
1865 groups = "tdm_ao_b_sclk";
1866 function = "tdm_ao_b";
1867 bias-disable;
1868 drive-strength-microamp = <3000>;
1869 };
1870 };
1871
1872 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
1873 mux {
1874 groups = "tdm_ao_b_slv_fs";
1875 function = "tdm_ao_b";
1876 bias-disable;
1877 };
1878 };
1879
1880 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
1881 mux {
1882 groups = "tdm_ao_b_slv_sclk";
1883 function = "tdm_ao_b";
1884 bias-disable;
1885 };
1886 };
1887
1888 uart_ao_a_pins: uart-a-ao {
1889 mux {
1890 groups = "uart_ao_a_tx",
1891 "uart_ao_a_rx";
1892 function = "uart_ao_a";
1893 bias-disable;
1894 };
1895 };
1896
1897 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
1898 mux {
1899 groups = "uart_ao_a_cts",
1900 "uart_ao_a_rts";
1901 function = "uart_ao_a";
1902 bias-disable;
1903 };
1904 };
1905
1906 uart_ao_b_2_3_pins: uart-ao-b-2-3 {
1907 mux {
1908 groups = "uart_ao_b_tx_2",
1909 "uart_ao_b_rx_3";
1910 function = "uart_ao_b";
1911 bias-disable;
1912 };
1913 };
1914
1915 uart_ao_b_8_9_pins: uart-ao-b-8-9 {
1916 mux {
1917 groups = "uart_ao_b_tx_8",
1918 "uart_ao_b_rx_9";
1919 function = "uart_ao_b";
1920 bias-disable;
1921 };
1922 };
1923
1924 uart_ao_b_cts_rts_pins: uart-ao-b-cts-rts {
1925 mux {
1926 groups = "uart_ao_b_cts",
1927 "uart_ao_b_rts";
1928 function = "uart_ao_b";
1929 bias-disable;
1930 };
1931 };
1932
1933 pwm_a_e_pins: pwm-a-e {
1934 mux {
1935 groups = "pwm_a_e";
1936 function = "pwm_a_e";
1937 bias-disable;
1938 };
1939 };
1940
1941 pwm_ao_a_pins: pwm-ao-a {
1942 mux {
1943 groups = "pwm_ao_a";
1944 function = "pwm_ao_a";
1945 bias-disable;
1946 };
1947 };
1948
1949 pwm_ao_b_pins: pwm-ao-b {
1950 mux {
1951 groups = "pwm_ao_b";
1952 function = "pwm_ao_b";
1953 bias-disable;
1954 };
1955 };
1956
1957 pwm_ao_c_4_pins: pwm-ao-c-4 {
1958 mux {
1959 groups = "pwm_ao_c_4";
1960 function = "pwm_ao_c";
1961 bias-disable;
1962 };
1963 };
1964
1965 pwm_ao_c_6_pins: pwm-ao-c-6 {
1966 mux {
1967 groups = "pwm_ao_c_6";
1968 function = "pwm_ao_c";
1969 bias-disable;
1970 };
1971 };
1972
1973 pwm_ao_d_5_pins: pwm-ao-d-5 {
1974 mux {
1975 groups = "pwm_ao_d_5";
1976 function = "pwm_ao_d";
1977 bias-disable;
1978 };
1979 };
1980
1981 pwm_ao_d_10_pins: pwm-ao-d-10 {
1982 mux {
1983 groups = "pwm_ao_d_10";
1984 function = "pwm_ao_d";
1985 bias-disable;
1986 };
1987 };
1988
1989 pwm_ao_d_e_pins: pwm-ao-d-e {
1990 mux {
1991 groups = "pwm_ao_d_e";
1992 function = "pwm_ao_d";
1993 };
1994 };
1995
1996 remote_input_ao_pins: remote-input-ao {
1997 mux {
1998 groups = "remote_ao_input";
1999 function = "remote_ao_input";
2000 bias-disable;
2001 };
2002 };
2003 };
2004 };
2005
2006 vrtc: rtc@a8 {
2007 compatible = "amlogic,meson-vrtc";
2008 reg = <0x0 0x000a8 0x0 0x4>;
2009 };
2010
2011 cec_AO: cec@100 {
2012 compatible = "amlogic,meson-gx-ao-cec";
2013 reg = <0x0 0x00100 0x0 0x14>;
2014 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
2015 clocks = <&clkc_AO CLKID_AO_CEC>;
2016 clock-names = "core";
2017 status = "disabled";
2018 };
2019
2020 sec_AO: ao-secure@140 {
2021 compatible = "amlogic,meson-gx-ao-secure", "syscon";
2022 reg = <0x0 0x140 0x0 0x140>;
2023 amlogic,has-chip-id;
2024 };
2025
2026 cecb_AO: cec@280 {
2027 compatible = "amlogic,meson-g12a-ao-cec";
2028 reg = <0x0 0x00280 0x0 0x1c>;
2029 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
2030 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
2031 clock-names = "oscin";
2032 status = "disabled";
2033 };
2034
2035 pwm_AO_cd: pwm@2000 {
2036 compatible = "amlogic,meson-g12a-ao-pwm-cd";
2037 reg = <0x0 0x2000 0x0 0x20>;
2038 #pwm-cells = <3>;
2039 status = "disabled";
2040 };
2041
2042 uart_AO: serial@3000 {
2043 compatible = "amlogic,meson-gx-uart",
2044 "amlogic,meson-ao-uart";
2045 reg = <0x0 0x3000 0x0 0x18>;
2046 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
2047 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
2048 clock-names = "xtal", "pclk", "baud";
2049 status = "disabled";
2050 };
2051
2052 uart_AO_B: serial@4000 {
2053 compatible = "amlogic,meson-gx-uart",
2054 "amlogic,meson-ao-uart";
2055 reg = <0x0 0x4000 0x0 0x18>;
2056 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
2057 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
2058 clock-names = "xtal", "pclk", "baud";
2059 status = "disabled";
2060 };
2061
2062 i2c_AO: i2c@5000 {
2063 compatible = "amlogic,meson-axg-i2c";
2064 status = "disabled";
2065 reg = <0x0 0x05000 0x0 0x20>;
2066 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
2067 #address-cells = <1>;
2068 #size-cells = <0>;
2069 clocks = <&clkc CLKID_I2C>;
2070 };
2071
2072 pwm_AO_ab: pwm@7000 {
2073 compatible = "amlogic,meson-g12a-ao-pwm-ab";
2074 reg = <0x0 0x7000 0x0 0x20>;
2075 #pwm-cells = <3>;
2076 status = "disabled";
2077 };
2078
2079 ir: ir@8000 {
2080 compatible = "amlogic,meson-gxbb-ir";
2081 reg = <0x0 0x8000 0x0 0x20>;
2082 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
2083 status = "disabled";
2084 };
2085
2086 saradc: adc@9000 {
2087 compatible = "amlogic,meson-g12a-saradc",
2088 "amlogic,meson-saradc";
2089 reg = <0x0 0x9000 0x0 0x48>;
2090 #io-channel-cells = <1>;
2091 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
2092 clocks = <&xtal>,
2093 <&clkc_AO CLKID_AO_SAR_ADC>,
2094 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
2095 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
2096 clock-names = "clkin", "core", "adc_clk", "adc_sel";
2097 status = "disabled";
2098 };
2099 };
2100
2101 vdec: video-decoder@ff620000 {
2102 compatible = "amlogic,g12a-vdec";
2103 reg = <0x0 0xff620000 0x0 0x10000>,
2104 <0x0 0xffd0e180 0x0 0xe4>;
2105 reg-names = "dos", "esparser";
2106 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
2107 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
2108 interrupt-names = "vdec", "esparser";
2109
2110 amlogic,ao-sysctrl = <&rti>;
2111 amlogic,canvas = <&canvas>;
2112
2113 clocks = <&clkc CLKID_PARSER>,
2114 <&clkc CLKID_DOS>,
2115 <&clkc CLKID_VDEC_1>,
2116 <&clkc CLKID_VDEC_HEVC>,
2117 <&clkc CLKID_VDEC_HEVCF>;
2118 clock-names = "dos_parser", "dos", "vdec_1",
2119 "vdec_hevc", "vdec_hevcf";
2120 resets = <&reset RESET_PARSER>;
2121 reset-names = "esparser";
2122 };
2123
2124 vpu: vpu@ff900000 {
2125 compatible = "amlogic,meson-g12a-vpu";
2126 reg = <0x0 0xff900000 0x0 0x100000>,
2127 <0x0 0xff63c000 0x0 0x1000>;
2128 reg-names = "vpu", "hhi";
2129 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
2130 #address-cells = <1>;
2131 #size-cells = <0>;
2132 amlogic,canvas = <&canvas>;
2133
2134 /* CVBS VDAC output port */
2135 cvbs_vdac_port: port@0 {
2136 reg = <0>;
2137 };
2138
2139 /* HDMI-TX output port */
2140 hdmi_tx_port: port@1 {
2141 reg = <1>;
2142
2143 hdmi_tx_out: endpoint {
2144 remote-endpoint = <&hdmi_tx_in>;
2145 };
2146 };
2147 };
2148
2149 gic: interrupt-controller@ffc01000 {
2150 compatible = "arm,gic-400";
2151 reg = <0x0 0xffc01000 0 0x1000>,
2152 <0x0 0xffc02000 0 0x2000>,
2153 <0x0 0xffc04000 0 0x2000>,
2154 <0x0 0xffc06000 0 0x2000>;
2155 interrupt-controller;
2156 interrupts = <GIC_PPI 9
2157 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2158 #interrupt-cells = <3>;
2159 #address-cells = <0>;
2160 };
2161
2162 cbus: bus@ffd00000 {
2163 compatible = "simple-bus";
2164 reg = <0x0 0xffd00000 0x0 0x100000>;
2165 #address-cells = <2>;
2166 #size-cells = <2>;
2167 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
2168
2169 reset: reset-controller@1004 {
2170 compatible = "amlogic,meson-axg-reset";
2171 reg = <0x0 0x1004 0x0 0x9c>;
2172 #reset-cells = <1>;
2173 };
2174
2175 gpio_intc: interrupt-controller@f080 {
2176 compatible = "amlogic,meson-g12a-gpio-intc",
2177 "amlogic,meson-gpio-intc";
2178 reg = <0x0 0xf080 0x0 0x10>;
2179 interrupt-controller;
2180 #interrupt-cells = <2>;
2181 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
2182 };
2183
2184 watchdog: watchdog@f0d0 {
2185 compatible = "amlogic,meson-gxbb-wdt";
2186 reg = <0x0 0xf0d0 0x0 0x10>;
2187 clocks = <&xtal>;
2188 };
2189
2190 spicc0: spi@13000 {
2191 compatible = "amlogic,meson-g12a-spicc";
2192 reg = <0x0 0x13000 0x0 0x44>;
2193 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2194 clocks = <&clkc CLKID_SPICC0>,
2195 <&clkc CLKID_SPICC0_SCLK>;
2196 clock-names = "core", "pclk";
2197 #address-cells = <1>;
2198 #size-cells = <0>;
2199 status = "disabled";
2200 };
2201
2202 spicc1: spi@15000 {
2203 compatible = "amlogic,meson-g12a-spicc";
2204 reg = <0x0 0x15000 0x0 0x44>;
2205 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
2206 clocks = <&clkc CLKID_SPICC1>,
2207 <&clkc CLKID_SPICC1_SCLK>;
2208 clock-names = "core", "pclk";
2209 #address-cells = <1>;
2210 #size-cells = <0>;
2211 status = "disabled";
2212 };
2213
2214 spifc: spi@14000 {
2215 compatible = "amlogic,meson-gxbb-spifc";
2216 status = "disabled";
2217 reg = <0x0 0x14000 0x0 0x80>;
2218 #address-cells = <1>;
2219 #size-cells = <0>;
2220 clocks = <&clkc CLKID_CLK81>;
2221 };
2222
2223 pwm_ef: pwm@19000 {
2224 compatible = "amlogic,meson-g12a-ee-pwm";
2225 reg = <0x0 0x19000 0x0 0x20>;
2226 #pwm-cells = <3>;
2227 status = "disabled";
2228 };
2229
2230 pwm_cd: pwm@1a000 {
2231 compatible = "amlogic,meson-g12a-ee-pwm";
2232 reg = <0x0 0x1a000 0x0 0x20>;
2233 #pwm-cells = <3>;
2234 status = "disabled";
2235 };
2236
2237 pwm_ab: pwm@1b000 {
2238 compatible = "amlogic,meson-g12a-ee-pwm";
2239 reg = <0x0 0x1b000 0x0 0x20>;
2240 #pwm-cells = <3>;
2241 status = "disabled";
2242 };
2243
2244 i2c3: i2c@1c000 {
2245 compatible = "amlogic,meson-axg-i2c";
2246 status = "disabled";
2247 reg = <0x0 0x1c000 0x0 0x20>;
2248 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
2249 #address-cells = <1>;
2250 #size-cells = <0>;
2251 clocks = <&clkc CLKID_I2C>;
2252 };
2253
2254 i2c2: i2c@1d000 {
2255 compatible = "amlogic,meson-axg-i2c";
2256 status = "disabled";
2257 reg = <0x0 0x1d000 0x0 0x20>;
2258 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
2259 #address-cells = <1>;
2260 #size-cells = <0>;
2261 clocks = <&clkc CLKID_I2C>;
2262 };
2263
2264 i2c1: i2c@1e000 {
2265 compatible = "amlogic,meson-axg-i2c";
2266 status = "disabled";
2267 reg = <0x0 0x1e000 0x0 0x20>;
2268 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
2269 #address-cells = <1>;
2270 #size-cells = <0>;
2271 clocks = <&clkc CLKID_I2C>;
2272 };
2273
2274 i2c0: i2c@1f000 {
2275 compatible = "amlogic,meson-axg-i2c";
2276 status = "disabled";
2277 reg = <0x0 0x1f000 0x0 0x20>;
2278 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
2279 #address-cells = <1>;
2280 #size-cells = <0>;
2281 clocks = <&clkc CLKID_I2C>;
2282 };
2283
2284 clk_msr: clock-measure@18000 {
2285 compatible = "amlogic,meson-g12a-clk-measure";
2286 reg = <0x0 0x18000 0x0 0x10>;
2287 };
2288
2289 uart_C: serial@22000 {
2290 compatible = "amlogic,meson-gx-uart";
2291 reg = <0x0 0x22000 0x0 0x18>;
2292 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
2293 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
2294 clock-names = "xtal", "pclk", "baud";
2295 status = "disabled";
2296 };
2297
2298 uart_B: serial@23000 {
2299 compatible = "amlogic,meson-gx-uart";
2300 reg = <0x0 0x23000 0x0 0x18>;
2301 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
2302 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
2303 clock-names = "xtal", "pclk", "baud";
2304 status = "disabled";
2305 };
2306
2307 uart_A: serial@24000 {
2308 compatible = "amlogic,meson-gx-uart";
2309 reg = <0x0 0x24000 0x0 0x18>;
2310 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
2311 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
2312 clock-names = "xtal", "pclk", "baud";
2313 status = "disabled";
2314 fifo-size = <128>;
2315 };
2316 };
2317
2318 sd_emmc_a: sd@ffe03000 {
2319 compatible = "amlogic,meson-axg-mmc";
2320 reg = <0x0 0xffe03000 0x0 0x800>;
2321 interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
2322 status = "disabled";
2323 clocks = <&clkc CLKID_SD_EMMC_A>,
2324 <&clkc CLKID_SD_EMMC_A_CLK0>,
2325 <&clkc CLKID_FCLK_DIV2>;
2326 clock-names = "core", "clkin0", "clkin1";
2327 resets = <&reset RESET_SD_EMMC_A>;
2328 };
2329
2330 sd_emmc_b: sd@ffe05000 {
2331 compatible = "amlogic,meson-axg-mmc";
2332 reg = <0x0 0xffe05000 0x0 0x800>;
2333 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
2334 status = "disabled";
2335 clocks = <&clkc CLKID_SD_EMMC_B>,
2336 <&clkc CLKID_SD_EMMC_B_CLK0>,
2337 <&clkc CLKID_FCLK_DIV2>;
2338 clock-names = "core", "clkin0", "clkin1";
2339 resets = <&reset RESET_SD_EMMC_B>;
2340 };
2341
2342 sd_emmc_c: mmc@ffe07000 {
2343 compatible = "amlogic,meson-axg-mmc";
2344 reg = <0x0 0xffe07000 0x0 0x800>;
2345 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
2346 status = "disabled";
2347 clocks = <&clkc CLKID_SD_EMMC_C>,
2348 <&clkc CLKID_SD_EMMC_C_CLK0>,
2349 <&clkc CLKID_FCLK_DIV2>;
2350 clock-names = "core", "clkin0", "clkin1";
2351 resets = <&reset RESET_SD_EMMC_C>;
2352 };
2353
2354 usb: usb@ffe09000 {
2355 status = "disabled";
2356 compatible = "amlogic,meson-g12a-usb-ctrl";
2357 reg = <0x0 0xffe09000 0x0 0xa0>;
2358 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2359 #address-cells = <2>;
2360 #size-cells = <2>;
2361 ranges;
2362
2363 clocks = <&clkc CLKID_USB>;
2364 resets = <&reset RESET_USB>;
2365
2366 dr_mode = "otg";
2367
2368 phys = <&usb2_phy0>, <&usb2_phy1>,
2369 <&usb3_pcie_phy PHY_TYPE_USB3>;
2370 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
2371
2372 dwc2: usb@ff400000 {
2373 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
2374 reg = <0x0 0xff400000 0x0 0x40000>;
2375 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
2376 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
2377 clock-names = "otg";
2378 phys = <&usb2_phy1>;
2379 phy-names = "usb2-phy";
2380 dr_mode = "peripheral";
2381 g-rx-fifo-size = <192>;
2382 g-np-tx-fifo-size = <128>;
2383 g-tx-fifo-size = <128 128 16 16 16>;
2384 };
2385
2386 dwc3: usb@ff500000 {
2387 compatible = "snps,dwc3";
2388 reg = <0x0 0xff500000 0x0 0x100000>;
2389 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2390 dr_mode = "host";
2391 snps,dis_u2_susphy_quirk;
2392 snps,quirk-frame-length-adjustment = <0x20>;
2393 snps,parkmode-disable-ss-quirk;
2394 };
2395 };
2396
2397 mali: gpu@ffe40000 {
2398 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
2399 reg = <0x0 0xffe40000 0x0 0x40000>;
2400 interrupt-parent = <&gic>;
2401 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
2402 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2403 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2404 interrupt-names = "job", "mmu", "gpu";
2405 clocks = <&clkc CLKID_MALI>;
2406 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
2407 operating-points-v2 = <&gpu_opp_table>;
2408 #cooling-cells = <2>;
2409 };
2410 };
2411
2412 thermal-zones {
2413 cpu_thermal: cpu-thermal {
2414 polling-delay = <1000>;
2415 polling-delay-passive = <100>;
2416 thermal-sensors = <&cpu_temp>;
2417
2418 trips {
2419 cpu_passive: cpu-passive {
2420 temperature = <85000>; /* millicelsius */
2421 hysteresis = <2000>; /* millicelsius */
2422 type = "passive";
2423 };
2424
2425 cpu_hot: cpu-hot {
2426 temperature = <95000>; /* millicelsius */
2427 hysteresis = <2000>; /* millicelsius */
2428 type = "hot";
2429 };
2430
2431 cpu_critical: cpu-critical {
2432 temperature = <110000>; /* millicelsius */
2433 hysteresis = <2000>; /* millicelsius */
2434 type = "critical";
2435 };
2436 };
2437 };
2438
2439 ddr_thermal: ddr-thermal {
2440 polling-delay = <1000>;
2441 polling-delay-passive = <100>;
2442 thermal-sensors = <&ddr_temp>;
2443
2444 trips {
2445 ddr_passive: ddr-passive {
2446 temperature = <85000>; /* millicelsius */
2447 hysteresis = <2000>; /* millicelsius */
2448 type = "passive";
2449 };
2450
2451 ddr_critical: ddr-critical {
2452 temperature = <110000>; /* millicelsius */
2453 hysteresis = <2000>; /* millicelsius */
2454 type = "critical";
2455 };
2456 };
2457
2458 cooling-maps {
2459 map {
2460 trip = <&ddr_passive>;
2461 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2462 };
2463 };
2464 };
2465 };
2466
2467 timer {
2468 compatible = "arm,armv8-timer";
2469 interrupts = <GIC_PPI 13
2470 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2471 <GIC_PPI 14
2472 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2473 <GIC_PPI 11
2474 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2475 <GIC_PPI 10
2476 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
2477 arm,no-tick-in-suspend;
2478 };
2479
2480 xtal: xtal-clk {
2481 compatible = "fixed-clock";
2482 clock-frequency = <24000000>;
2483 clock-output-names = "xtal";
2484 #clock-cells = <0>;
2485 };
2486
2487 };
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