0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/irq.h>
0007 #include <dt-bindings/interrupt-controller/arm-gic.h>
0008 #include <dt-bindings/gpio/meson-a1-gpio.h>
0009
0010 / {
0011 compatible = "amlogic,a1";
0012
0013 interrupt-parent = <&gic>;
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016
0017 cpus {
0018 #address-cells = <2>;
0019 #size-cells = <0>;
0020
0021 cpu0: cpu@0 {
0022 device_type = "cpu";
0023 compatible = "arm,cortex-a35";
0024 reg = <0x0 0x0>;
0025 enable-method = "psci";
0026 next-level-cache = <&l2>;
0027 };
0028
0029 cpu1: cpu@1 {
0030 device_type = "cpu";
0031 compatible = "arm,cortex-a35";
0032 reg = <0x0 0x1>;
0033 enable-method = "psci";
0034 next-level-cache = <&l2>;
0035 };
0036
0037 l2: l2-cache0 {
0038 compatible = "cache";
0039 };
0040 };
0041
0042 psci {
0043 compatible = "arm,psci-1.0";
0044 method = "smc";
0045 };
0046
0047 reserved-memory {
0048 #address-cells = <2>;
0049 #size-cells = <2>;
0050 ranges;
0051
0052 linux,cma {
0053 compatible = "shared-dma-pool";
0054 reusable;
0055 size = <0x0 0x800000>;
0056 alignment = <0x0 0x400000>;
0057 linux,cma-default;
0058 };
0059 };
0060
0061 sm: secure-monitor {
0062 compatible = "amlogic,meson-gxbb-sm";
0063
0064 pwrc: power-controller {
0065 compatible = "amlogic,meson-a1-pwrc";
0066 #power-domain-cells = <1>;
0067 status = "okay";
0068 };
0069 };
0070
0071 soc {
0072 compatible = "simple-bus";
0073 #address-cells = <2>;
0074 #size-cells = <2>;
0075 ranges;
0076
0077 apb: bus@fe000000 {
0078 compatible = "simple-bus";
0079 reg = <0x0 0xfe000000 0x0 0x1000000>;
0080 #address-cells = <2>;
0081 #size-cells = <2>;
0082 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
0083
0084
0085 reset: reset-controller@0 {
0086 compatible = "amlogic,meson-a1-reset";
0087 reg = <0x0 0x0 0x0 0x8c>;
0088 #reset-cells = <1>;
0089 };
0090
0091 periphs_pinctrl: pinctrl@400 {
0092 compatible = "amlogic,meson-a1-periphs-pinctrl";
0093 #address-cells = <2>;
0094 #size-cells = <2>;
0095 ranges;
0096
0097 gpio: bank@400 {
0098 reg = <0x0 0x0400 0x0 0x003c>,
0099 <0x0 0x0480 0x0 0x0118>;
0100 reg-names = "mux", "gpio";
0101 gpio-controller;
0102 #gpio-cells = <2>;
0103 gpio-ranges = <&periphs_pinctrl 0 0 62>;
0104 };
0105
0106 };
0107
0108 uart_AO: serial@1c00 {
0109 compatible = "amlogic,meson-gx-uart",
0110 "amlogic,meson-ao-uart";
0111 reg = <0x0 0x1c00 0x0 0x18>;
0112 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
0113 clocks = <&xtal>, <&xtal>, <&xtal>;
0114 clock-names = "xtal", "pclk", "baud";
0115 status = "disabled";
0116 };
0117
0118 uart_AO_B: serial@2000 {
0119 compatible = "amlogic,meson-gx-uart",
0120 "amlogic,meson-ao-uart";
0121 reg = <0x0 0x2000 0x0 0x18>;
0122 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
0123 clocks = <&xtal>, <&xtal>, <&xtal>;
0124 clock-names = "xtal", "pclk", "baud";
0125 status = "disabled";
0126 };
0127 };
0128
0129 gic: interrupt-controller@ff901000 {
0130 compatible = "arm,gic-400";
0131 reg = <0x0 0xff901000 0x0 0x1000>,
0132 <0x0 0xff902000 0x0 0x2000>,
0133 <0x0 0xff904000 0x0 0x2000>,
0134 <0x0 0xff906000 0x0 0x2000>;
0135 interrupt-controller;
0136 interrupts = <GIC_PPI 9
0137 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
0138 #interrupt-cells = <3>;
0139 #address-cells = <0>;
0140 };
0141 };
0142
0143 timer {
0144 compatible = "arm,armv8-timer";
0145 interrupts = <GIC_PPI 13
0146 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
0147 <GIC_PPI 14
0148 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
0149 <GIC_PPI 11
0150 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
0151 <GIC_PPI 10
0152 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
0153 };
0154
0155 xtal: xtal-clk {
0156 compatible = "fixed-clock";
0157 clock-frequency = <24000000>;
0158 clock-output-names = "xtal";
0159 #clock-cells = <0>;
0160 };
0161 };
