arm64/altera/socfpga_stratix10_swvp.dts

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2022, Intel Corporation
0004  */
0005
0006 #include "socfpga_stratix10.dtsi"
0007
0008 / {
0009         model = "SOCFPGA Stratix 10 SWVP";
0010         compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
0011
0012         aliases {
0013                 serial0 = &uart0;
0014                 serial1 = &uart1;
0015
0016                 timer0 = &timer0;
0017                 timer1 = &timer1;
0018                 timer2 = &timer2;
0019                 timer3 = &timer3;
0020
0021                 ethernet0 = &gmac0;
0022                 ethernet1 = &gmac1;
0023                 ethernet2 = &gmac2;
0024         };
0025
0026         chosen {
0027                 stdout-path = "serial1:115200n8";
0028                 linux,initrd-start = <0x10000000>;
0029                 linux,initrd-end = <0x125c8324>;
0030         };
0031
0032         memory {
0033                 device_type = "memory";
0034                 reg = <0x0 0x0 0x0 0x80000000>;
0035         };
0036 };
0037
0038 &cpu0 {
0039         enable-method = "spin-table";
0040         cpu-release-addr = <0x0 0x0000fff8>;
0041 };
0042
0043 &cpu1 {
0044         enable-method = "spin-table";
0045         cpu-release-addr = <0x0 0x0000fff8>;
0046 };
0047
0048 &cpu2 {
0049         enable-method = "spin-table";
0050         cpu-release-addr = <0x0 0x0000fff8>;
0051 };
0052
0053 &cpu3 {
0054         enable-method = "spin-table";
0055         cpu-release-addr = <0x0 0x0000fff8>;
0056 };
0057
0058 &osc1 {
0059         clock-frequency = <25000000>;
0060 };
0061
0062 &gmac0 {
0063         status = "okay";
0064         phy-mode = "rgmii";
0065         phy-addr = <0xffffffff>;
0066         snps,max-mtu = <0x0>;
0067 };
0068
0069 &gmac1 {
0070         status = "okay";
0071         phy-mode = "rgmii";
0072         phy-addr = <0xffffffff>;
0073 };
0074
0075 &gmac2 {
0076         status = "okay";
0077         phy-mode = "rgmii";
0078         phy-addr = <0xffffffff>;
0079 };
0080
0081 &mmc {
0082         status = "okay";
0083         altr,dw-mshc-ciu-div = <0x3>;
0084         altr,dw-mshc-sdr-timing = <0x0 0x3>;
0085         cap-sd-highspeed;
0086         cap-mmc-highspeed;
0087         broken-cd;
0088         bus-width = <4>;
0089 };
0090
0091 &uart0 {
0092         status = "okay";
0093 };
0094
0095 &uart1 {
0096         status = "okay";
0097 };
0098
0099 &usb0 {
0100         clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
0101         status = "okay";
0102 };
0103
0104 &usb1 {
0105         clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
0106         status = "okay";
0107 };
0108
0109 &rst {
0110         altr,modrst-offset = <0x20>;
0111 };
0112
0113 &sysmgr {
0114         reg = <0xffd12000 0x1000>;
0115         interrupts = <0x0 0x10 0x4>;
0116         cpu1-start-addr = <0xffd06230>;
0117 };