0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright Altera Corporation (C) 2015. All rights reserved.
0004 */
0005
0006 /dts-v1/;
0007 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/clock/stratix10-clock.h>
0010
0011 / {
0012 compatible = "altr,socfpga-stratix10";
0013 #address-cells = <2>;
0014 #size-cells = <2>;
0015
0016 reserved-memory {
0017 #address-cells = <2>;
0018 #size-cells = <2>;
0019 ranges;
0020
0021 service_reserved: svcbuffer@0 {
0022 compatible = "shared-dma-pool";
0023 reg = <0x0 0x0 0x0 0x1000000>;
0024 alignment = <0x1000>;
0025 no-map;
0026 };
0027 };
0028
0029 cpus {
0030 #address-cells = <1>;
0031 #size-cells = <0>;
0032
0033 cpu0: cpu@0 {
0034 compatible = "arm,cortex-a53";
0035 device_type = "cpu";
0036 enable-method = "psci";
0037 reg = <0x0>;
0038 };
0039
0040 cpu1: cpu@1 {
0041 compatible = "arm,cortex-a53";
0042 device_type = "cpu";
0043 enable-method = "psci";
0044 reg = <0x1>;
0045 };
0046
0047 cpu2: cpu@2 {
0048 compatible = "arm,cortex-a53";
0049 device_type = "cpu";
0050 enable-method = "psci";
0051 reg = <0x2>;
0052 };
0053
0054 cpu3: cpu@3 {
0055 compatible = "arm,cortex-a53";
0056 device_type = "cpu";
0057 enable-method = "psci";
0058 reg = <0x3>;
0059 };
0060 };
0061
0062 pmu {
0063 compatible = "arm,armv8-pmuv3";
0064 interrupts = <0 170 4>,
0065 <0 171 4>,
0066 <0 172 4>,
0067 <0 173 4>;
0068 interrupt-affinity = <&cpu0>,
0069 <&cpu1>,
0070 <&cpu2>,
0071 <&cpu3>;
0072 interrupt-parent = <&intc>;
0073 };
0074
0075 psci {
0076 compatible = "arm,psci-0.2";
0077 method = "smc";
0078 };
0079
0080 /* Local timer */
0081 timer {
0082 compatible = "arm,armv8-timer";
0083 interrupts = <1 13 0xf08>,
0084 <1 14 0xf08>,
0085 <1 11 0xf08>,
0086 <1 10 0xf08>;
0087 interrupt-parent = <&intc>;
0088 };
0089
0090 intc: interrupt-controller@fffc1000 {
0091 compatible = "arm,gic-400", "arm,cortex-a15-gic";
0092 #interrupt-cells = <3>;
0093 interrupt-controller;
0094 reg = <0x0 0xfffc1000 0x0 0x1000>,
0095 <0x0 0xfffc2000 0x0 0x2000>,
0096 <0x0 0xfffc4000 0x0 0x2000>,
0097 <0x0 0xfffc6000 0x0 0x2000>;
0098 };
0099
0100 clocks {
0101 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
0102 #clock-cells = <0>;
0103 compatible = "fixed-clock";
0104 };
0105
0106 cb_intosc_ls_clk: cb-intosc-ls-clk {
0107 #clock-cells = <0>;
0108 compatible = "fixed-clock";
0109 };
0110
0111 f2s_free_clk: f2s-free-clk {
0112 #clock-cells = <0>;
0113 compatible = "fixed-clock";
0114 };
0115
0116 osc1: osc1 {
0117 #clock-cells = <0>;
0118 compatible = "fixed-clock";
0119 };
0120
0121 qspi_clk: qspi-clk {
0122 #clock-cells = <0>;
0123 compatible = "fixed-clock";
0124 clock-frequency = <200000000>;
0125 };
0126 };
0127
0128 soc {
0129 #address-cells = <1>;
0130 #size-cells = <1>;
0131 compatible = "simple-bus";
0132 device_type = "soc";
0133 interrupt-parent = <&intc>;
0134 ranges = <0 0 0 0xffffffff>;
0135
0136 base_fpga_region {
0137 #address-cells = <0x1>;
0138 #size-cells = <0x1>;
0139
0140 compatible = "fpga-region";
0141 fpga-mgr = <&fpga_mgr>;
0142 };
0143
0144 clkmgr: clock-controller@ffd10000 {
0145 compatible = "intel,stratix10-clkmgr";
0146 reg = <0xffd10000 0x1000>;
0147 #clock-cells = <1>;
0148 };
0149
0150 gmac0: ethernet@ff800000 {
0151 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
0152 reg = <0xff800000 0x2000>;
0153 interrupts = <0 90 4>;
0154 interrupt-names = "macirq";
0155 mac-address = [00 00 00 00 00 00];
0156 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
0157 reset-names = "stmmaceth", "stmmaceth-ocp";
0158 clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
0159 clock-names = "stmmaceth", "ptp_ref";
0160 tx-fifo-depth = <16384>;
0161 rx-fifo-depth = <16384>;
0162 snps,multicast-filter-bins = <256>;
0163 iommus = <&smmu 1>;
0164 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
0165 status = "disabled";
0166 };
0167
0168 gmac1: ethernet@ff802000 {
0169 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
0170 reg = <0xff802000 0x2000>;
0171 interrupts = <0 91 4>;
0172 interrupt-names = "macirq";
0173 mac-address = [00 00 00 00 00 00];
0174 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
0175 reset-names = "stmmaceth", "stmmaceth-ocp";
0176 clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
0177 clock-names = "stmmaceth", "ptp_ref";
0178 tx-fifo-depth = <16384>;
0179 rx-fifo-depth = <16384>;
0180 snps,multicast-filter-bins = <256>;
0181 iommus = <&smmu 2>;
0182 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
0183 status = "disabled";
0184 };
0185
0186 gmac2: ethernet@ff804000 {
0187 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
0188 reg = <0xff804000 0x2000>;
0189 interrupts = <0 92 4>;
0190 interrupt-names = "macirq";
0191 mac-address = [00 00 00 00 00 00];
0192 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
0193 reset-names = "stmmaceth", "stmmaceth-ocp";
0194 clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
0195 clock-names = "stmmaceth", "ptp_ref";
0196 tx-fifo-depth = <16384>;
0197 rx-fifo-depth = <16384>;
0198 snps,multicast-filter-bins = <256>;
0199 iommus = <&smmu 3>;
0200 altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
0201 status = "disabled";
0202 };
0203
0204 gpio0: gpio@ffc03200 {
0205 #address-cells = <1>;
0206 #size-cells = <0>;
0207 compatible = "snps,dw-apb-gpio";
0208 reg = <0xffc03200 0x100>;
0209 resets = <&rst GPIO0_RESET>;
0210 status = "disabled";
0211
0212 porta: gpio-controller@0 {
0213 compatible = "snps,dw-apb-gpio-port";
0214 gpio-controller;
0215 #gpio-cells = <2>;
0216 ngpios = <24>;
0217 reg = <0>;
0218 interrupt-controller;
0219 #interrupt-cells = <2>;
0220 interrupts = <0 110 4>;
0221 };
0222 };
0223
0224 gpio1: gpio@ffc03300 {
0225 #address-cells = <1>;
0226 #size-cells = <0>;
0227 compatible = "snps,dw-apb-gpio";
0228 reg = <0xffc03300 0x100>;
0229 resets = <&rst GPIO1_RESET>;
0230 status = "disabled";
0231
0232 portb: gpio-controller@0 {
0233 compatible = "snps,dw-apb-gpio-port";
0234 gpio-controller;
0235 #gpio-cells = <2>;
0236 ngpios = <24>;
0237 reg = <0>;
0238 interrupt-controller;
0239 #interrupt-cells = <2>;
0240 interrupts = <0 111 4>;
0241 };
0242 };
0243
0244 i2c0: i2c@ffc02800 {
0245 #address-cells = <1>;
0246 #size-cells = <0>;
0247 compatible = "snps,designware-i2c";
0248 reg = <0xffc02800 0x100>;
0249 interrupts = <0 103 4>;
0250 resets = <&rst I2C0_RESET>;
0251 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
0252 status = "disabled";
0253 };
0254
0255 i2c1: i2c@ffc02900 {
0256 #address-cells = <1>;
0257 #size-cells = <0>;
0258 compatible = "snps,designware-i2c";
0259 reg = <0xffc02900 0x100>;
0260 interrupts = <0 104 4>;
0261 resets = <&rst I2C1_RESET>;
0262 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
0263 status = "disabled";
0264 };
0265
0266 i2c2: i2c@ffc02a00 {
0267 #address-cells = <1>;
0268 #size-cells = <0>;
0269 compatible = "snps,designware-i2c";
0270 reg = <0xffc02a00 0x100>;
0271 interrupts = <0 105 4>;
0272 resets = <&rst I2C2_RESET>;
0273 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
0274 status = "disabled";
0275 };
0276
0277 i2c3: i2c@ffc02b00 {
0278 #address-cells = <1>;
0279 #size-cells = <0>;
0280 compatible = "snps,designware-i2c";
0281 reg = <0xffc02b00 0x100>;
0282 interrupts = <0 106 4>;
0283 resets = <&rst I2C3_RESET>;
0284 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
0285 status = "disabled";
0286 };
0287
0288 i2c4: i2c@ffc02c00 {
0289 #address-cells = <1>;
0290 #size-cells = <0>;
0291 compatible = "snps,designware-i2c";
0292 reg = <0xffc02c00 0x100>;
0293 interrupts = <0 107 4>;
0294 resets = <&rst I2C4_RESET>;
0295 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
0296 status = "disabled";
0297 };
0298
0299 mmc: mmc@ff808000 {
0300 #address-cells = <1>;
0301 #size-cells = <0>;
0302 compatible = "altr,socfpga-dw-mshc";
0303 reg = <0xff808000 0x1000>;
0304 interrupts = <0 96 4>;
0305 fifo-depth = <0x400>;
0306 resets = <&rst SDMMC_RESET>;
0307 reset-names = "reset";
0308 clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
0309 <&clkmgr STRATIX10_SDMMC_CLK>;
0310 clock-names = "biu", "ciu";
0311 iommus = <&smmu 5>;
0312 status = "disabled";
0313 };
0314
0315 nand: nand-controller@ffb90000 {
0316 #address-cells = <1>;
0317 #size-cells = <0>;
0318 compatible = "altr,socfpga-denali-nand";
0319 reg = <0xffb90000 0x10000>,
0320 <0xffb80000 0x1000>;
0321 reg-names = "nand_data", "denali_reg";
0322 interrupts = <0 97 4>;
0323 clocks = <&clkmgr STRATIX10_NAND_CLK>,
0324 <&clkmgr STRATIX10_NAND_X_CLK>,
0325 <&clkmgr STRATIX10_NAND_ECC_CLK>;
0326 clock-names = "nand", "nand_x", "ecc";
0327 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
0328 status = "disabled";
0329 };
0330
0331 ocram: sram@ffe00000 {
0332 compatible = "mmio-sram";
0333 reg = <0xffe00000 0x100000>;
0334 };
0335
0336 pdma: dma-controller@ffda0000 {
0337 compatible = "arm,pl330", "arm,primecell";
0338 reg = <0xffda0000 0x1000>;
0339 interrupts = <0 81 4>,
0340 <0 82 4>,
0341 <0 83 4>,
0342 <0 84 4>,
0343 <0 85 4>,
0344 <0 86 4>,
0345 <0 87 4>,
0346 <0 88 4>,
0347 <0 89 4>;
0348 #dma-cells = <1>;
0349 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
0350 clock-names = "apb_pclk";
0351 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
0352 reset-names = "dma", "dma-ocp";
0353 };
0354
0355 rst: rstmgr@ffd11000 {
0356 #reset-cells = <1>;
0357 compatible = "altr,stratix10-rst-mgr";
0358 reg = <0xffd11000 0x1000>;
0359 };
0360
0361 smmu: iommu@fa000000 {
0362 compatible = "arm,mmu-500", "arm,smmu-v2";
0363 reg = <0xfa000000 0x40000>;
0364 #global-interrupts = <2>;
0365 #iommu-cells = <1>;
0366 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
0367 clock-names = "iommu";
0368 interrupt-parent = <&intc>;
0369 interrupts = <0 128 4>, /* Global Secure Fault */
0370 <0 129 4>, /* Global Non-secure Fault */
0371 /* Non-secure Context Interrupts (32) */
0372 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
0373 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
0374 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
0375 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
0376 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
0377 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
0378 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
0379 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
0380 stream-match-mask = <0x7ff0>;
0381 status = "disabled";
0382 };
0383
0384 spi0: spi@ffda4000 {
0385 compatible = "snps,dw-apb-ssi";
0386 #address-cells = <1>;
0387 #size-cells = <0>;
0388 reg = <0xffda4000 0x1000>;
0389 interrupts = <0 99 4>;
0390 resets = <&rst SPIM0_RESET>;
0391 reset-names = "spi";
0392 reg-io-width = <4>;
0393 num-cs = <4>;
0394 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
0395 status = "disabled";
0396 };
0397
0398 spi1: spi@ffda5000 {
0399 compatible = "snps,dw-apb-ssi";
0400 #address-cells = <1>;
0401 #size-cells = <0>;
0402 reg = <0xffda5000 0x1000>;
0403 interrupts = <0 100 4>;
0404 resets = <&rst SPIM1_RESET>;
0405 reset-names = "spi";
0406 reg-io-width = <4>;
0407 num-cs = <4>;
0408 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
0409 status = "disabled";
0410 };
0411
0412 sysmgr: sysmgr@ffd12000 {
0413 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
0414 reg = <0xffd12000 0x228>;
0415 };
0416
0417 timer0: timer0@ffc03000 {
0418 compatible = "snps,dw-apb-timer";
0419 interrupts = <0 113 4>;
0420 reg = <0xffc03000 0x100>;
0421 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
0422 clock-names = "timer";
0423 };
0424
0425 timer1: timer1@ffc03100 {
0426 compatible = "snps,dw-apb-timer";
0427 interrupts = <0 114 4>;
0428 reg = <0xffc03100 0x100>;
0429 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
0430 clock-names = "timer";
0431 };
0432
0433 timer2: timer2@ffd00000 {
0434 compatible = "snps,dw-apb-timer";
0435 interrupts = <0 115 4>;
0436 reg = <0xffd00000 0x100>;
0437 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
0438 clock-names = "timer";
0439 };
0440
0441 timer3: timer3@ffd00100 {
0442 compatible = "snps,dw-apb-timer";
0443 interrupts = <0 116 4>;
0444 reg = <0xffd00100 0x100>;
0445 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
0446 clock-names = "timer";
0447 };
0448
0449 uart0: serial@ffc02000 {
0450 compatible = "snps,dw-apb-uart";
0451 reg = <0xffc02000 0x100>;
0452 interrupts = <0 108 4>;
0453 reg-shift = <2>;
0454 reg-io-width = <4>;
0455 resets = <&rst UART0_RESET>;
0456 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
0457 status = "disabled";
0458 };
0459
0460 uart1: serial@ffc02100 {
0461 compatible = "snps,dw-apb-uart";
0462 reg = <0xffc02100 0x100>;
0463 interrupts = <0 109 4>;
0464 reg-shift = <2>;
0465 reg-io-width = <4>;
0466 resets = <&rst UART1_RESET>;
0467 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
0468 status = "disabled";
0469 };
0470
0471 usbphy0: usbphy@0 {
0472 #phy-cells = <0>;
0473 compatible = "usb-nop-xceiv";
0474 status = "okay";
0475 };
0476
0477 usb0: usb@ffb00000 {
0478 compatible = "snps,dwc2";
0479 reg = <0xffb00000 0x40000>;
0480 interrupts = <0 93 4>;
0481 phys = <&usbphy0>;
0482 phy-names = "usb2-phy";
0483 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
0484 reset-names = "dwc2", "dwc2-ecc";
0485 clocks = <&clkmgr STRATIX10_USB_CLK>;
0486 clock-names = "otg";
0487 iommus = <&smmu 6>;
0488 status = "disabled";
0489 };
0490
0491 usb1: usb@ffb40000 {
0492 compatible = "snps,dwc2";
0493 reg = <0xffb40000 0x40000>;
0494 interrupts = <0 94 4>;
0495 phys = <&usbphy0>;
0496 phy-names = "usb2-phy";
0497 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
0498 reset-names = "dwc2", "dwc2-ecc";
0499 clocks = <&clkmgr STRATIX10_USB_CLK>;
0500 iommus = <&smmu 7>;
0501 status = "disabled";
0502 };
0503
0504 watchdog0: watchdog@ffd00200 {
0505 compatible = "snps,dw-wdt";
0506 reg = <0xffd00200 0x100>;
0507 interrupts = <0 117 4>;
0508 resets = <&rst WATCHDOG0_RESET>;
0509 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
0510 status = "disabled";
0511 };
0512
0513 watchdog1: watchdog@ffd00300 {
0514 compatible = "snps,dw-wdt";
0515 reg = <0xffd00300 0x100>;
0516 interrupts = <0 118 4>;
0517 resets = <&rst WATCHDOG1_RESET>;
0518 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
0519 status = "disabled";
0520 };
0521
0522 watchdog2: watchdog@ffd00400 {
0523 compatible = "snps,dw-wdt";
0524 reg = <0xffd00400 0x100>;
0525 interrupts = <0 125 4>;
0526 resets = <&rst WATCHDOG2_RESET>;
0527 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
0528 status = "disabled";
0529 };
0530
0531 watchdog3: watchdog@ffd00500 {
0532 compatible = "snps,dw-wdt";
0533 reg = <0xffd00500 0x100>;
0534 interrupts = <0 126 4>;
0535 resets = <&rst WATCHDOG3_RESET>;
0536 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
0537 status = "disabled";
0538 };
0539
0540 sdr: sdr@f8011100 {
0541 compatible = "altr,sdr-ctl", "syscon";
0542 reg = <0xf8011100 0xc0>;
0543 };
0544
0545 eccmgr {
0546 compatible = "altr,socfpga-s10-ecc-manager",
0547 "altr,socfpga-a10-ecc-manager";
0548 altr,sysmgr-syscon = <&sysmgr>;
0549 #address-cells = <1>;
0550 #size-cells = <1>;
0551 interrupts = <0 15 4>;
0552 interrupt-controller;
0553 #interrupt-cells = <2>;
0554 ranges;
0555
0556 sdramedac {
0557 compatible = "altr,sdram-edac-s10";
0558 altr,sdr-syscon = <&sdr>;
0559 interrupts = <16 4>;
0560 };
0561
0562 ocram-ecc@ff8cc000 {
0563 compatible = "altr,socfpga-s10-ocram-ecc",
0564 "altr,socfpga-a10-ocram-ecc";
0565 reg = <0xff8cc000 0x100>;
0566 altr,ecc-parent = <&ocram>;
0567 interrupts = <1 4>;
0568 };
0569
0570 usb0-ecc@ff8c4000 {
0571 compatible = "altr,socfpga-s10-usb-ecc",
0572 "altr,socfpga-usb-ecc";
0573 reg = <0xff8c4000 0x100>;
0574 altr,ecc-parent = <&usb0>;
0575 interrupts = <2 4>;
0576 };
0577
0578 emac0-rx-ecc@ff8c0000 {
0579 compatible = "altr,socfpga-s10-eth-mac-ecc",
0580 "altr,socfpga-eth-mac-ecc";
0581 reg = <0xff8c0000 0x100>;
0582 altr,ecc-parent = <&gmac0>;
0583 interrupts = <4 4>;
0584 };
0585
0586 emac0-tx-ecc@ff8c0400 {
0587 compatible = "altr,socfpga-s10-eth-mac-ecc",
0588 "altr,socfpga-eth-mac-ecc";
0589 reg = <0xff8c0400 0x100>;
0590 altr,ecc-parent = <&gmac0>;
0591 interrupts = <5 4>;
0592 };
0593
0594 };
0595
0596 qspi: spi@ff8d2000 {
0597 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
0598 #address-cells = <1>;
0599 #size-cells = <0>;
0600 reg = <0xff8d2000 0x100>,
0601 <0xff900000 0x100000>;
0602 interrupts = <0 3 4>;
0603 cdns,fifo-depth = <128>;
0604 cdns,fifo-width = <4>;
0605 cdns,trigger-address = <0x00000000>;
0606 clocks = <&qspi_clk>;
0607
0608 status = "disabled";
0609 };
0610
0611 firmware {
0612 svc {
0613 compatible = "intel,stratix10-svc";
0614 method = "smc";
0615 memory-region = <&service_reserved>;
0616
0617 fpga_mgr: fpga-mgr {
0618 compatible = "intel,stratix10-soc-fpga-mgr";
0619 };
0620 };
0621 };
0622 };
0623 };
