0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 // Copyright (C) 2020 Arm Ltd.
0003 // based on the H6 dtsi, which is:
0004 // Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
0005
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/clock/sun50i-h616-ccu.h>
0008 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
0009 #include <dt-bindings/clock/sun6i-rtc.h>
0010 #include <dt-bindings/reset/sun50i-h616-ccu.h>
0011 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
0012
0013 / {
0014 interrupt-parent = <&gic>;
0015 #address-cells = <2>;
0016 #size-cells = <2>;
0017
0018 cpus {
0019 #address-cells = <1>;
0020 #size-cells = <0>;
0021
0022 cpu0: cpu@0 {
0023 compatible = "arm,cortex-a53";
0024 device_type = "cpu";
0025 reg = <0>;
0026 enable-method = "psci";
0027 clocks = <&ccu CLK_CPUX>;
0028 };
0029
0030 cpu1: cpu@1 {
0031 compatible = "arm,cortex-a53";
0032 device_type = "cpu";
0033 reg = <1>;
0034 enable-method = "psci";
0035 clocks = <&ccu CLK_CPUX>;
0036 };
0037
0038 cpu2: cpu@2 {
0039 compatible = "arm,cortex-a53";
0040 device_type = "cpu";
0041 reg = <2>;
0042 enable-method = "psci";
0043 clocks = <&ccu CLK_CPUX>;
0044 };
0045
0046 cpu3: cpu@3 {
0047 compatible = "arm,cortex-a53";
0048 device_type = "cpu";
0049 reg = <3>;
0050 enable-method = "psci";
0051 clocks = <&ccu CLK_CPUX>;
0052 };
0053 };
0054
0055 reserved-memory {
0056 #address-cells = <2>;
0057 #size-cells = <2>;
0058 ranges;
0059
0060 /*
0061 * 256 KiB reserved for Trusted Firmware-A (BL31).
0062 * This is added by BL31 itself, but some bootloaders fail
0063 * to propagate this into the DTB handed to kernels.
0064 */
0065 secmon@40000000 {
0066 reg = <0x0 0x40000000 0x0 0x40000>;
0067 no-map;
0068 };
0069 };
0070
0071 osc24M: osc24M-clk {
0072 #clock-cells = <0>;
0073 compatible = "fixed-clock";
0074 clock-frequency = <24000000>;
0075 clock-output-names = "osc24M";
0076 };
0077
0078 pmu {
0079 compatible = "arm,cortex-a53-pmu";
0080 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
0081 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
0082 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
0083 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0084 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0085 };
0086
0087 psci {
0088 compatible = "arm,psci-0.2";
0089 method = "smc";
0090 };
0091
0092 timer {
0093 compatible = "arm,armv8-timer";
0094 arm,no-tick-in-suspend;
0095 interrupts = <GIC_PPI 13
0096 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0097 <GIC_PPI 14
0098 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0099 <GIC_PPI 11
0100 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0101 <GIC_PPI 10
0102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0103 };
0104
0105 soc {
0106 compatible = "simple-bus";
0107 #address-cells = <1>;
0108 #size-cells = <1>;
0109 ranges = <0x0 0x0 0x0 0x40000000>;
0110
0111 syscon: syscon@3000000 {
0112 compatible = "allwinner,sun50i-h616-system-control";
0113 reg = <0x03000000 0x1000>;
0114 #address-cells = <1>;
0115 #size-cells = <1>;
0116 ranges;
0117
0118 sram_c: sram@28000 {
0119 compatible = "mmio-sram";
0120 reg = <0x00028000 0x30000>;
0121 #address-cells = <1>;
0122 #size-cells = <1>;
0123 ranges = <0 0x00028000 0x30000>;
0124 };
0125 };
0126
0127 ccu: clock@3001000 {
0128 compatible = "allwinner,sun50i-h616-ccu";
0129 reg = <0x03001000 0x1000>;
0130 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
0131 clock-names = "hosc", "losc", "iosc";
0132 #clock-cells = <1>;
0133 #reset-cells = <1>;
0134 };
0135
0136 watchdog: watchdog@30090a0 {
0137 compatible = "allwinner,sun50i-h616-wdt",
0138 "allwinner,sun6i-a31-wdt";
0139 reg = <0x030090a0 0x20>;
0140 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0141 clocks = <&osc24M>;
0142 };
0143
0144 pio: pinctrl@300b000 {
0145 compatible = "allwinner,sun50i-h616-pinctrl";
0146 reg = <0x0300b000 0x400>;
0147 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
0148 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
0149 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
0150 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
0151 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
0152 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
0153 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
0154 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0155 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
0156 clock-names = "apb", "hosc", "losc";
0157 gpio-controller;
0158 #gpio-cells = <3>;
0159 interrupt-controller;
0160 #interrupt-cells = <3>;
0161
0162 ext_rgmii_pins: rgmii-pins {
0163 pins = "PI0", "PI1", "PI2", "PI3", "PI4",
0164 "PI5", "PI7", "PI8", "PI9", "PI10",
0165 "PI11", "PI12", "PI13", "PI14", "PI15",
0166 "PI16";
0167 function = "emac0";
0168 drive-strength = <40>;
0169 };
0170
0171 i2c0_pins: i2c0-pins {
0172 pins = "PI6", "PI7";
0173 function = "i2c0";
0174 };
0175
0176 i2c3_ph_pins: i2c3-ph-pins {
0177 pins = "PH4", "PH5";
0178 function = "i2c3";
0179 };
0180
0181 ir_rx_pin: ir-rx-pin {
0182 pins = "PH10";
0183 function = "ir_rx";
0184 };
0185
0186 mmc0_pins: mmc0-pins {
0187 pins = "PF0", "PF1", "PF2", "PF3",
0188 "PF4", "PF5";
0189 function = "mmc0";
0190 drive-strength = <30>;
0191 bias-pull-up;
0192 };
0193
0194 /omit-if-no-ref/
0195 mmc1_pins: mmc1-pins {
0196 pins = "PG0", "PG1", "PG2", "PG3",
0197 "PG4", "PG5";
0198 function = "mmc1";
0199 drive-strength = <30>;
0200 bias-pull-up;
0201 };
0202
0203 mmc2_pins: mmc2-pins {
0204 pins = "PC0", "PC1", "PC5", "PC6",
0205 "PC8", "PC9", "PC10", "PC11",
0206 "PC13", "PC14", "PC15", "PC16";
0207 function = "mmc2";
0208 drive-strength = <30>;
0209 bias-pull-up;
0210 };
0211
0212 /omit-if-no-ref/
0213 spi0_pins: spi0-pins {
0214 pins = "PC0", "PC2", "PC4";
0215 function = "spi0";
0216 };
0217
0218 /omit-if-no-ref/
0219 spi0_cs0_pin: spi0-cs0-pin {
0220 pins = "PC3";
0221 function = "spi0";
0222 };
0223
0224 /omit-if-no-ref/
0225 spi1_pins: spi1-pins {
0226 pins = "PH6", "PH7", "PH8";
0227 function = "spi1";
0228 };
0229
0230 /omit-if-no-ref/
0231 spi1_cs0_pin: spi1-cs0-pin {
0232 pins = "PH5";
0233 function = "spi1";
0234 };
0235
0236 uart0_ph_pins: uart0-ph-pins {
0237 pins = "PH0", "PH1";
0238 function = "uart0";
0239 };
0240
0241 /omit-if-no-ref/
0242 uart1_pins: uart1-pins {
0243 pins = "PG6", "PG7";
0244 function = "uart1";
0245 };
0246
0247 /omit-if-no-ref/
0248 uart1_rts_cts_pins: uart1-rts-cts-pins {
0249 pins = "PG8", "PG9";
0250 function = "uart1";
0251 };
0252 };
0253
0254 gic: interrupt-controller@3021000 {
0255 compatible = "arm,gic-400";
0256 reg = <0x03021000 0x1000>,
0257 <0x03022000 0x2000>,
0258 <0x03024000 0x2000>,
0259 <0x03026000 0x2000>;
0260 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0261 interrupt-controller;
0262 #interrupt-cells = <3>;
0263 };
0264
0265 mmc0: mmc@4020000 {
0266 compatible = "allwinner,sun50i-h616-mmc",
0267 "allwinner,sun50i-a100-mmc";
0268 reg = <0x04020000 0x1000>;
0269 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
0270 clock-names = "ahb", "mmc";
0271 resets = <&ccu RST_BUS_MMC0>;
0272 reset-names = "ahb";
0273 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0274 pinctrl-names = "default";
0275 pinctrl-0 = <&mmc0_pins>;
0276 status = "disabled";
0277 max-frequency = <150000000>;
0278 cap-sd-highspeed;
0279 cap-mmc-highspeed;
0280 mmc-ddr-3_3v;
0281 cap-sdio-irq;
0282 #address-cells = <1>;
0283 #size-cells = <0>;
0284 };
0285
0286 mmc1: mmc@4021000 {
0287 compatible = "allwinner,sun50i-h616-mmc",
0288 "allwinner,sun50i-a100-mmc";
0289 reg = <0x04021000 0x1000>;
0290 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
0291 clock-names = "ahb", "mmc";
0292 resets = <&ccu RST_BUS_MMC1>;
0293 reset-names = "ahb";
0294 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0295 pinctrl-names = "default";
0296 pinctrl-0 = <&mmc1_pins>;
0297 status = "disabled";
0298 max-frequency = <150000000>;
0299 cap-sd-highspeed;
0300 cap-mmc-highspeed;
0301 mmc-ddr-3_3v;
0302 cap-sdio-irq;
0303 #address-cells = <1>;
0304 #size-cells = <0>;
0305 };
0306
0307 mmc2: mmc@4022000 {
0308 compatible = "allwinner,sun50i-h616-emmc",
0309 "allwinner,sun50i-a100-emmc";
0310 reg = <0x04022000 0x1000>;
0311 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
0312 clock-names = "ahb", "mmc";
0313 resets = <&ccu RST_BUS_MMC2>;
0314 reset-names = "ahb";
0315 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0316 pinctrl-names = "default";
0317 pinctrl-0 = <&mmc2_pins>;
0318 status = "disabled";
0319 max-frequency = <150000000>;
0320 cap-sd-highspeed;
0321 cap-mmc-highspeed;
0322 mmc-ddr-3_3v;
0323 cap-sdio-irq;
0324 #address-cells = <1>;
0325 #size-cells = <0>;
0326 };
0327
0328 uart0: serial@5000000 {
0329 compatible = "snps,dw-apb-uart";
0330 reg = <0x05000000 0x400>;
0331 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0332 reg-shift = <2>;
0333 reg-io-width = <4>;
0334 clocks = <&ccu CLK_BUS_UART0>;
0335 resets = <&ccu RST_BUS_UART0>;
0336 status = "disabled";
0337 };
0338
0339 uart1: serial@5000400 {
0340 compatible = "snps,dw-apb-uart";
0341 reg = <0x05000400 0x400>;
0342 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0343 reg-shift = <2>;
0344 reg-io-width = <4>;
0345 clocks = <&ccu CLK_BUS_UART1>;
0346 resets = <&ccu RST_BUS_UART1>;
0347 status = "disabled";
0348 };
0349
0350 uart2: serial@5000800 {
0351 compatible = "snps,dw-apb-uart";
0352 reg = <0x05000800 0x400>;
0353 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0354 reg-shift = <2>;
0355 reg-io-width = <4>;
0356 clocks = <&ccu CLK_BUS_UART2>;
0357 resets = <&ccu RST_BUS_UART2>;
0358 status = "disabled";
0359 };
0360
0361 uart3: serial@5000c00 {
0362 compatible = "snps,dw-apb-uart";
0363 reg = <0x05000c00 0x400>;
0364 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0365 reg-shift = <2>;
0366 reg-io-width = <4>;
0367 clocks = <&ccu CLK_BUS_UART3>;
0368 resets = <&ccu RST_BUS_UART3>;
0369 status = "disabled";
0370 };
0371
0372 uart4: serial@5001000 {
0373 compatible = "snps,dw-apb-uart";
0374 reg = <0x05001000 0x400>;
0375 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0376 reg-shift = <2>;
0377 reg-io-width = <4>;
0378 clocks = <&ccu CLK_BUS_UART4>;
0379 resets = <&ccu RST_BUS_UART4>;
0380 status = "disabled";
0381 };
0382
0383 uart5: serial@5001400 {
0384 compatible = "snps,dw-apb-uart";
0385 reg = <0x05001400 0x400>;
0386 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0387 reg-shift = <2>;
0388 reg-io-width = <4>;
0389 clocks = <&ccu CLK_BUS_UART5>;
0390 resets = <&ccu RST_BUS_UART5>;
0391 status = "disabled";
0392 };
0393
0394 i2c0: i2c@5002000 {
0395 compatible = "allwinner,sun50i-h616-i2c",
0396 "allwinner,sun8i-v536-i2c",
0397 "allwinner,sun6i-a31-i2c";
0398 reg = <0x05002000 0x400>;
0399 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0400 clocks = <&ccu CLK_BUS_I2C0>;
0401 resets = <&ccu RST_BUS_I2C0>;
0402 pinctrl-names = "default";
0403 pinctrl-0 = <&i2c0_pins>;
0404 status = "disabled";
0405 #address-cells = <1>;
0406 #size-cells = <0>;
0407 };
0408
0409 i2c1: i2c@5002400 {
0410 compatible = "allwinner,sun50i-h616-i2c",
0411 "allwinner,sun8i-v536-i2c",
0412 "allwinner,sun6i-a31-i2c";
0413 reg = <0x05002400 0x400>;
0414 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0415 clocks = <&ccu CLK_BUS_I2C1>;
0416 resets = <&ccu RST_BUS_I2C1>;
0417 status = "disabled";
0418 #address-cells = <1>;
0419 #size-cells = <0>;
0420 };
0421
0422 i2c2: i2c@5002800 {
0423 compatible = "allwinner,sun50i-h616-i2c",
0424 "allwinner,sun8i-v536-i2c",
0425 "allwinner,sun6i-a31-i2c";
0426 reg = <0x05002800 0x400>;
0427 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0428 clocks = <&ccu CLK_BUS_I2C2>;
0429 resets = <&ccu RST_BUS_I2C2>;
0430 status = "disabled";
0431 #address-cells = <1>;
0432 #size-cells = <0>;
0433 };
0434
0435 i2c3: i2c@5002c00 {
0436 compatible = "allwinner,sun50i-h616-i2c",
0437 "allwinner,sun8i-v536-i2c",
0438 "allwinner,sun6i-a31-i2c";
0439 reg = <0x05002c00 0x400>;
0440 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0441 clocks = <&ccu CLK_BUS_I2C3>;
0442 resets = <&ccu RST_BUS_I2C3>;
0443 status = "disabled";
0444 #address-cells = <1>;
0445 #size-cells = <0>;
0446 };
0447
0448 i2c4: i2c@5003000 {
0449 compatible = "allwinner,sun50i-h616-i2c",
0450 "allwinner,sun8i-v536-i2c",
0451 "allwinner,sun6i-a31-i2c";
0452 reg = <0x05003000 0x400>;
0453 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0454 clocks = <&ccu CLK_BUS_I2C4>;
0455 resets = <&ccu RST_BUS_I2C4>;
0456 status = "disabled";
0457 #address-cells = <1>;
0458 #size-cells = <0>;
0459 };
0460
0461 spi0: spi@5010000 {
0462 compatible = "allwinner,sun50i-h616-spi",
0463 "allwinner,sun8i-h3-spi";
0464 reg = <0x05010000 0x1000>;
0465 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0466 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
0467 clock-names = "ahb", "mod";
0468 resets = <&ccu RST_BUS_SPI0>;
0469 status = "disabled";
0470 #address-cells = <1>;
0471 #size-cells = <0>;
0472 };
0473
0474 spi1: spi@5011000 {
0475 compatible = "allwinner,sun50i-h616-spi",
0476 "allwinner,sun8i-h3-spi";
0477 reg = <0x05011000 0x1000>;
0478 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0479 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
0480 clock-names = "ahb", "mod";
0481 resets = <&ccu RST_BUS_SPI1>;
0482 status = "disabled";
0483 #address-cells = <1>;
0484 #size-cells = <0>;
0485 };
0486
0487 emac0: ethernet@5020000 {
0488 compatible = "allwinner,sun50i-h616-emac0",
0489 "allwinner,sun50i-a64-emac";
0490 reg = <0x05020000 0x10000>;
0491 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0492 interrupt-names = "macirq";
0493 clocks = <&ccu CLK_BUS_EMAC0>;
0494 clock-names = "stmmaceth";
0495 resets = <&ccu RST_BUS_EMAC0>;
0496 reset-names = "stmmaceth";
0497 syscon = <&syscon>;
0498 status = "disabled";
0499
0500 mdio0: mdio {
0501 compatible = "snps,dwmac-mdio";
0502 #address-cells = <1>;
0503 #size-cells = <0>;
0504 };
0505 };
0506
0507 rtc: rtc@7000000 {
0508 compatible = "allwinner,sun50i-h616-rtc";
0509 reg = <0x07000000 0x400>;
0510 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
0511 clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>,
0512 <&ccu CLK_PLL_SYSTEM_32K>;
0513 clock-names = "bus", "hosc",
0514 "pll-32k";
0515 #clock-cells = <1>;
0516 };
0517
0518 r_ccu: clock@7010000 {
0519 compatible = "allwinner,sun50i-h616-r-ccu";
0520 reg = <0x07010000 0x210>;
0521 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
0522 <&ccu CLK_PLL_PERIPH0>;
0523 clock-names = "hosc", "losc", "iosc", "pll-periph";
0524 #clock-cells = <1>;
0525 #reset-cells = <1>;
0526 };
0527
0528 r_pio: pinctrl@7022000 {
0529 compatible = "allwinner,sun50i-h616-r-pinctrl";
0530 reg = <0x07022000 0x400>;
0531 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>,
0532 <&rtc CLK_OSC32K>;
0533 clock-names = "apb", "hosc", "losc";
0534 gpio-controller;
0535 #gpio-cells = <3>;
0536
0537 /omit-if-no-ref/
0538 r_i2c_pins: r-i2c-pins {
0539 pins = "PL0", "PL1";
0540 function = "s_i2c";
0541 };
0542
0543 r_rsb_pins: r-rsb-pins {
0544 pins = "PL0", "PL1";
0545 function = "s_rsb";
0546 };
0547 };
0548
0549 ir: ir@7040000 {
0550 compatible = "allwinner,sun50i-h616-ir",
0551 "allwinner,sun6i-a31-ir";
0552 reg = <0x07040000 0x400>;
0553 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0554 clocks = <&r_ccu CLK_R_APB1_IR>,
0555 <&r_ccu CLK_IR>;
0556 clock-names = "apb", "ir";
0557 resets = <&r_ccu RST_R_APB1_IR>;
0558 pinctrl-names = "default";
0559 pinctrl-0 = <&ir_rx_pin>;
0560 status = "disabled";
0561 };
0562
0563 r_i2c: i2c@7081400 {
0564 compatible = "allwinner,sun50i-h616-i2c",
0565 "allwinner,sun8i-v536-i2c",
0566 "allwinner,sun6i-a31-i2c";
0567 reg = <0x07081400 0x400>;
0568 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0569 clocks = <&r_ccu CLK_R_APB2_I2C>;
0570 resets = <&r_ccu RST_R_APB2_I2C>;
0571 status = "disabled";
0572 #address-cells = <1>;
0573 #size-cells = <0>;
0574 };
0575
0576 r_rsb: rsb@7083000 {
0577 compatible = "allwinner,sun50i-h616-rsb",
0578 "allwinner,sun8i-a23-rsb";
0579 reg = <0x07083000 0x400>;
0580 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
0581 clocks = <&r_ccu CLK_R_APB2_RSB>;
0582 clock-frequency = <3000000>;
0583 resets = <&r_ccu RST_R_APB2_RSB>;
0584 pinctrl-names = "default";
0585 pinctrl-0 = <&r_rsb_pins>;
0586 status = "disabled";
0587 #address-cells = <1>;
0588 #size-cells = <0>;
0589 };
0590 };
0591 };
