0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 // Copyright (C) 2016 ARM Ltd.
0003
0004 #include <arm/sunxi-h3-h5.dtsi>
0005
0006 #include <dt-bindings/thermal/thermal.h>
0007
0008 / {
0009 cpus {
0010 #address-cells = <1>;
0011 #size-cells = <0>;
0012
0013 cpu0: cpu@0 {
0014 compatible = "arm,cortex-a53";
0015 device_type = "cpu";
0016 reg = <0>;
0017 enable-method = "psci";
0018 clocks = <&ccu CLK_CPUX>;
0019 clock-latency-ns = <244144>; /* 8 32k periods */
0020 #cooling-cells = <2>;
0021 };
0022
0023 cpu1: cpu@1 {
0024 compatible = "arm,cortex-a53";
0025 device_type = "cpu";
0026 reg = <1>;
0027 enable-method = "psci";
0028 clocks = <&ccu CLK_CPUX>;
0029 clock-latency-ns = <244144>; /* 8 32k periods */
0030 #cooling-cells = <2>;
0031 };
0032
0033 cpu2: cpu@2 {
0034 compatible = "arm,cortex-a53";
0035 device_type = "cpu";
0036 reg = <2>;
0037 enable-method = "psci";
0038 clocks = <&ccu CLK_CPUX>;
0039 clock-latency-ns = <244144>; /* 8 32k periods */
0040 #cooling-cells = <2>;
0041 };
0042
0043 cpu3: cpu@3 {
0044 compatible = "arm,cortex-a53";
0045 device_type = "cpu";
0046 reg = <3>;
0047 enable-method = "psci";
0048 clocks = <&ccu CLK_CPUX>;
0049 clock-latency-ns = <244144>; /* 8 32k periods */
0050 #cooling-cells = <2>;
0051 };
0052 };
0053
0054 pmu {
0055 compatible = "arm,cortex-a53-pmu";
0056 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
0057 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
0058 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
0059 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
0060 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0061 };
0062
0063 psci {
0064 compatible = "arm,psci-0.2";
0065 method = "smc";
0066 };
0067
0068 timer {
0069 compatible = "arm,armv8-timer";
0070 arm,no-tick-in-suspend;
0071 interrupts = <GIC_PPI 13
0072 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0073 <GIC_PPI 14
0074 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0075 <GIC_PPI 11
0076 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0077 <GIC_PPI 10
0078 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0079 };
0080
0081 soc {
0082 syscon: system-control@1c00000 {
0083 compatible = "allwinner,sun50i-h5-system-control";
0084 reg = <0x01c00000 0x1000>;
0085 #address-cells = <1>;
0086 #size-cells = <1>;
0087 ranges;
0088
0089 sram_c1: sram@18000 {
0090 compatible = "mmio-sram";
0091 reg = <0x00018000 0x1c000>;
0092 #address-cells = <1>;
0093 #size-cells = <1>;
0094 ranges = <0 0x00018000 0x1c000>;
0095
0096 ve_sram: sram-section@0 {
0097 compatible = "allwinner,sun50i-h5-sram-c1",
0098 "allwinner,sun4i-a10-sram-c1";
0099 reg = <0x000000 0x1c000>;
0100 };
0101 };
0102 };
0103
0104 video-codec@1c0e000 {
0105 compatible = "allwinner,sun50i-h5-video-engine";
0106 reg = <0x01c0e000 0x1000>;
0107 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
0108 <&ccu CLK_DRAM_VE>;
0109 clock-names = "ahb", "mod", "ram";
0110 resets = <&ccu RST_BUS_VE>;
0111 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0112 allwinner,sram = <&ve_sram 1>;
0113 };
0114
0115 crypto: crypto@1c15000 {
0116 compatible = "allwinner,sun50i-h5-crypto";
0117 reg = <0x01c15000 0x1000>;
0118 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0119 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
0120 clock-names = "bus", "mod";
0121 resets = <&ccu RST_BUS_CE>;
0122 };
0123
0124 deinterlace: deinterlace@1e00000 {
0125 compatible = "allwinner,sun8i-h3-deinterlace";
0126 reg = <0x01e00000 0x20000>;
0127 clocks = <&ccu CLK_BUS_DEINTERLACE>,
0128 <&ccu CLK_DEINTERLACE>,
0129 <&ccu CLK_DRAM_DEINTERLACE>;
0130 clock-names = "bus", "mod", "ram";
0131 resets = <&ccu RST_BUS_DEINTERLACE>;
0132 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
0133 interconnects = <&mbus 9>;
0134 interconnect-names = "dma-mem";
0135 };
0136
0137 mali: gpu@1e80000 {
0138 compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
0139 reg = <0x01e80000 0x30000>;
0140 /*
0141 * While the datasheet lists an interrupt for the
0142 * PMU, the actual silicon does not have the PMU
0143 * block. Reads all return zero, and writes are
0144 * ignored.
0145 */
0146 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
0147 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
0148 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
0149 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
0150 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
0151 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
0152 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
0153 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0154 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0155 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0156 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0157 interrupt-names = "gp",
0158 "gpmmu",
0159 "pp",
0160 "pp0",
0161 "ppmmu0",
0162 "pp1",
0163 "ppmmu1",
0164 "pp2",
0165 "ppmmu2",
0166 "pp3",
0167 "ppmmu3";
0168 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
0169 clock-names = "bus", "core";
0170 resets = <&ccu RST_BUS_GPU>;
0171
0172 assigned-clocks = <&ccu CLK_GPU>;
0173 assigned-clock-rates = <384000000>;
0174 };
0175
0176 ths: thermal-sensor@1c25000 {
0177 compatible = "allwinner,sun50i-h5-ths";
0178 reg = <0x01c25000 0x400>;
0179 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0180 resets = <&ccu RST_BUS_THS>;
0181 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
0182 clock-names = "bus", "mod";
0183 nvmem-cells = <&ths_calibration>;
0184 nvmem-cell-names = "calibration";
0185 #thermal-sensor-cells = <1>;
0186 };
0187 };
0188
0189 thermal-zones {
0190 cpu_thermal: cpu-thermal {
0191 polling-delay-passive = <0>;
0192 polling-delay = <0>;
0193 thermal-sensors = <&ths 0>;
0194
0195 trips {
0196 cpu_hot_trip: cpu-hot {
0197 temperature = <80000>;
0198 hysteresis = <2000>;
0199 type = "passive";
0200 };
0201
0202 cpu_very_hot_trip: cpu-very-hot {
0203 temperature = <100000>;
0204 hysteresis = <0>;
0205 type = "critical";
0206 };
0207 };
0208
0209 cooling-maps {
0210 cpu-hot-limit {
0211 trip = <&cpu_hot_trip>;
0212 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0213 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0214 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0215 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0216 };
0217 };
0218 };
0219
0220 gpu-thermal {
0221 polling-delay-passive = <0>;
0222 polling-delay = <0>;
0223 thermal-sensors = <&ths 1>;
0224 };
0225 };
0226 };
0227
0228 &ccu {
0229 compatible = "allwinner,sun50i-h5-ccu";
0230 };
0231
0232 &display_clocks {
0233 compatible = "allwinner,sun50i-h5-de2-clk";
0234 };
0235
0236 &mbus {
0237 compatible = "allwinner,sun50i-h5-mbus";
0238 };
0239
0240 &mmc0 {
0241 compatible = "allwinner,sun50i-h5-mmc",
0242 "allwinner,sun50i-a64-mmc";
0243 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
0244 clock-names = "ahb", "mmc";
0245 };
0246
0247 &mmc1 {
0248 compatible = "allwinner,sun50i-h5-mmc",
0249 "allwinner,sun50i-a64-mmc";
0250 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
0251 clock-names = "ahb", "mmc";
0252 };
0253
0254 &mmc2 {
0255 compatible = "allwinner,sun50i-h5-emmc",
0256 "allwinner,sun50i-a64-emmc";
0257 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
0258 clock-names = "ahb", "mmc";
0259 };
0260
0261 &pio {
0262 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0263 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
0264 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0265 compatible = "allwinner,sun50i-h5-pinctrl";
0266 };
0267
0268 &rtc {
0269 compatible = "allwinner,sun50i-h5-rtc";
0270 };
0271
0272 &sid {
0273 compatible = "allwinner,sun50i-h5-sid";
0274 };
