0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 // Copyright (C) 2016 ARM Ltd.
0003 // based on the Allwinner H3 dtsi:
0004 // Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
0005
0006 #include <dt-bindings/clock/sun50i-a64-ccu.h>
0007 #include <dt-bindings/clock/sun6i-rtc.h>
0008 #include <dt-bindings/clock/sun8i-de2.h>
0009 #include <dt-bindings/clock/sun8i-r-ccu.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/reset/sun50i-a64-ccu.h>
0012 #include <dt-bindings/reset/sun8i-de2.h>
0013 #include <dt-bindings/reset/sun8i-r-ccu.h>
0014 #include <dt-bindings/thermal/thermal.h>
0015
0016 / {
0017 interrupt-parent = <&gic>;
0018 #address-cells = <1>;
0019 #size-cells = <1>;
0020
0021 chosen {
0022 #address-cells = <1>;
0023 #size-cells = <1>;
0024 ranges;
0025
0026 simplefb_lcd: framebuffer-lcd {
0027 compatible = "allwinner,simple-framebuffer",
0028 "simple-framebuffer";
0029 allwinner,pipeline = "mixer0-lcd0";
0030 clocks = <&ccu CLK_TCON0>,
0031 <&display_clocks CLK_MIXER0>;
0032 status = "disabled";
0033 };
0034
0035 simplefb_hdmi: framebuffer-hdmi {
0036 compatible = "allwinner,simple-framebuffer",
0037 "simple-framebuffer";
0038 allwinner,pipeline = "mixer1-lcd1-hdmi";
0039 clocks = <&display_clocks CLK_MIXER1>,
0040 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
0041 status = "disabled";
0042 };
0043 };
0044
0045 cpus {
0046 #address-cells = <1>;
0047 #size-cells = <0>;
0048
0049 cpu0: cpu@0 {
0050 compatible = "arm,cortex-a53";
0051 device_type = "cpu";
0052 reg = <0>;
0053 enable-method = "psci";
0054 next-level-cache = <&L2>;
0055 clocks = <&ccu CLK_CPUX>;
0056 clock-names = "cpu";
0057 #cooling-cells = <2>;
0058 };
0059
0060 cpu1: cpu@1 {
0061 compatible = "arm,cortex-a53";
0062 device_type = "cpu";
0063 reg = <1>;
0064 enable-method = "psci";
0065 next-level-cache = <&L2>;
0066 clocks = <&ccu CLK_CPUX>;
0067 clock-names = "cpu";
0068 #cooling-cells = <2>;
0069 };
0070
0071 cpu2: cpu@2 {
0072 compatible = "arm,cortex-a53";
0073 device_type = "cpu";
0074 reg = <2>;
0075 enable-method = "psci";
0076 next-level-cache = <&L2>;
0077 clocks = <&ccu CLK_CPUX>;
0078 clock-names = "cpu";
0079 #cooling-cells = <2>;
0080 };
0081
0082 cpu3: cpu@3 {
0083 compatible = "arm,cortex-a53";
0084 device_type = "cpu";
0085 reg = <3>;
0086 enable-method = "psci";
0087 next-level-cache = <&L2>;
0088 clocks = <&ccu CLK_CPUX>;
0089 clock-names = "cpu";
0090 #cooling-cells = <2>;
0091 };
0092
0093 L2: l2-cache {
0094 compatible = "cache";
0095 cache-level = <2>;
0096 };
0097 };
0098
0099 de: display-engine {
0100 compatible = "allwinner,sun50i-a64-display-engine";
0101 allwinner,pipelines = <&mixer0>,
0102 <&mixer1>;
0103 status = "disabled";
0104 };
0105
0106 gpu_opp_table: opp-table-gpu {
0107 compatible = "operating-points-v2";
0108
0109 opp-120000000 {
0110 opp-hz = /bits/ 64 <120000000>;
0111 };
0112
0113 opp-312000000 {
0114 opp-hz = /bits/ 64 <312000000>;
0115 };
0116
0117 opp-432000000 {
0118 opp-hz = /bits/ 64 <432000000>;
0119 };
0120 };
0121
0122 osc24M: osc24M_clk {
0123 #clock-cells = <0>;
0124 compatible = "fixed-clock";
0125 clock-frequency = <24000000>;
0126 clock-output-names = "osc24M";
0127 };
0128
0129 osc32k: osc32k_clk {
0130 #clock-cells = <0>;
0131 compatible = "fixed-clock";
0132 clock-frequency = <32768>;
0133 clock-output-names = "ext-osc32k";
0134 };
0135
0136 pmu {
0137 compatible = "arm,cortex-a53-pmu";
0138 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
0139 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
0140 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
0141 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
0142 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0143 };
0144
0145 psci {
0146 compatible = "arm,psci-0.2";
0147 method = "smc";
0148 };
0149
0150 sound: sound {
0151 #address-cells = <1>;
0152 #size-cells = <0>;
0153 compatible = "simple-audio-card";
0154 simple-audio-card,name = "sun50i-a64-audio";
0155 simple-audio-card,aux-devs = <&codec_analog>;
0156 simple-audio-card,routing =
0157 "Left DAC", "DACL",
0158 "Right DAC", "DACR",
0159 "ADCL", "Left ADC",
0160 "ADCR", "Right ADC";
0161 status = "disabled";
0162
0163 simple-audio-card,dai-link@0 {
0164 format = "i2s";
0165 frame-master = <&link0_cpu>;
0166 bitclock-master = <&link0_cpu>;
0167 mclk-fs = <128>;
0168
0169 link0_cpu: cpu {
0170 sound-dai = <&dai>;
0171 };
0172
0173 link0_codec: codec {
0174 sound-dai = <&codec 0>;
0175 };
0176 };
0177 };
0178
0179 timer {
0180 compatible = "arm,armv8-timer";
0181 allwinner,erratum-unknown1;
0182 arm,no-tick-in-suspend;
0183 interrupts = <GIC_PPI 13
0184 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0185 <GIC_PPI 14
0186 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0187 <GIC_PPI 11
0188 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0189 <GIC_PPI 10
0190 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0191 };
0192
0193 thermal-zones {
0194 cpu_thermal: cpu0-thermal {
0195 /* milliseconds */
0196 polling-delay-passive = <0>;
0197 polling-delay = <0>;
0198 thermal-sensors = <&ths 0>;
0199
0200 cooling-maps {
0201 map0 {
0202 trip = <&cpu_alert0>;
0203 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0204 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0205 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0206 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0207 };
0208 map1 {
0209 trip = <&cpu_alert1>;
0210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0211 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0212 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0213 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0214 };
0215 };
0216
0217 trips {
0218 cpu_alert0: cpu_alert0 {
0219 /* milliCelsius */
0220 temperature = <75000>;
0221 hysteresis = <2000>;
0222 type = "passive";
0223 };
0224
0225 cpu_alert1: cpu_alert1 {
0226 /* milliCelsius */
0227 temperature = <90000>;
0228 hysteresis = <2000>;
0229 type = "hot";
0230 };
0231
0232 cpu_crit: cpu_crit {
0233 /* milliCelsius */
0234 temperature = <110000>;
0235 hysteresis = <2000>;
0236 type = "critical";
0237 };
0238 };
0239 };
0240
0241 gpu0_thermal: gpu0-thermal {
0242 /* milliseconds */
0243 polling-delay-passive = <0>;
0244 polling-delay = <0>;
0245 thermal-sensors = <&ths 1>;
0246 };
0247
0248 gpu1_thermal: gpu1-thermal {
0249 /* milliseconds */
0250 polling-delay-passive = <0>;
0251 polling-delay = <0>;
0252 thermal-sensors = <&ths 2>;
0253 };
0254 };
0255
0256 soc {
0257 compatible = "simple-bus";
0258 #address-cells = <1>;
0259 #size-cells = <1>;
0260 ranges;
0261
0262 bus@1000000 {
0263 compatible = "allwinner,sun50i-a64-de2";
0264 reg = <0x1000000 0x400000>;
0265 allwinner,sram = <&de2_sram 1>;
0266 #address-cells = <1>;
0267 #size-cells = <1>;
0268 ranges = <0 0x1000000 0x400000>;
0269
0270 display_clocks: clock@0 {
0271 compatible = "allwinner,sun50i-a64-de2-clk";
0272 reg = <0x0 0x10000>;
0273 clocks = <&ccu CLK_BUS_DE>,
0274 <&ccu CLK_DE>;
0275 clock-names = "bus",
0276 "mod";
0277 resets = <&ccu RST_BUS_DE>;
0278 #clock-cells = <1>;
0279 #reset-cells = <1>;
0280 };
0281
0282 rotate: rotate@20000 {
0283 compatible = "allwinner,sun50i-a64-de2-rotate",
0284 "allwinner,sun8i-a83t-de2-rotate";
0285 reg = <0x20000 0x10000>;
0286 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0287 clocks = <&display_clocks CLK_BUS_ROT>,
0288 <&display_clocks CLK_ROT>;
0289 clock-names = "bus",
0290 "mod";
0291 resets = <&display_clocks RST_ROT>;
0292 };
0293
0294 mixer0: mixer@100000 {
0295 compatible = "allwinner,sun50i-a64-de2-mixer-0";
0296 reg = <0x100000 0x100000>;
0297 clocks = <&display_clocks CLK_BUS_MIXER0>,
0298 <&display_clocks CLK_MIXER0>;
0299 clock-names = "bus",
0300 "mod";
0301 resets = <&display_clocks RST_MIXER0>;
0302
0303 ports {
0304 #address-cells = <1>;
0305 #size-cells = <0>;
0306
0307 mixer0_out: port@1 {
0308 #address-cells = <1>;
0309 #size-cells = <0>;
0310 reg = <1>;
0311
0312 mixer0_out_tcon0: endpoint@0 {
0313 reg = <0>;
0314 remote-endpoint = <&tcon0_in_mixer0>;
0315 };
0316
0317 mixer0_out_tcon1: endpoint@1 {
0318 reg = <1>;
0319 remote-endpoint = <&tcon1_in_mixer0>;
0320 };
0321 };
0322 };
0323 };
0324
0325 mixer1: mixer@200000 {
0326 compatible = "allwinner,sun50i-a64-de2-mixer-1";
0327 reg = <0x200000 0x100000>;
0328 clocks = <&display_clocks CLK_BUS_MIXER1>,
0329 <&display_clocks CLK_MIXER1>;
0330 clock-names = "bus",
0331 "mod";
0332 resets = <&display_clocks RST_MIXER1>;
0333
0334 ports {
0335 #address-cells = <1>;
0336 #size-cells = <0>;
0337
0338 mixer1_out: port@1 {
0339 #address-cells = <1>;
0340 #size-cells = <0>;
0341 reg = <1>;
0342
0343 mixer1_out_tcon0: endpoint@0 {
0344 reg = <0>;
0345 remote-endpoint = <&tcon0_in_mixer1>;
0346 };
0347
0348 mixer1_out_tcon1: endpoint@1 {
0349 reg = <1>;
0350 remote-endpoint = <&tcon1_in_mixer1>;
0351 };
0352 };
0353 };
0354 };
0355 };
0356
0357 syscon: syscon@1c00000 {
0358 compatible = "allwinner,sun50i-a64-system-control";
0359 reg = <0x01c00000 0x1000>;
0360 #address-cells = <1>;
0361 #size-cells = <1>;
0362 ranges;
0363
0364 sram_c: sram@18000 {
0365 compatible = "mmio-sram";
0366 reg = <0x00018000 0x28000>;
0367 #address-cells = <1>;
0368 #size-cells = <1>;
0369 ranges = <0 0x00018000 0x28000>;
0370
0371 de2_sram: sram-section@0 {
0372 compatible = "allwinner,sun50i-a64-sram-c";
0373 reg = <0x0000 0x28000>;
0374 };
0375 };
0376
0377 sram_c1: sram@1d00000 {
0378 compatible = "mmio-sram";
0379 reg = <0x01d00000 0x40000>;
0380 #address-cells = <1>;
0381 #size-cells = <1>;
0382 ranges = <0 0x01d00000 0x40000>;
0383
0384 ve_sram: sram-section@0 {
0385 compatible = "allwinner,sun50i-a64-sram-c1",
0386 "allwinner,sun4i-a10-sram-c1";
0387 reg = <0x000000 0x40000>;
0388 };
0389 };
0390 };
0391
0392 dma: dma-controller@1c02000 {
0393 compatible = "allwinner,sun50i-a64-dma";
0394 reg = <0x01c02000 0x1000>;
0395 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0396 clocks = <&ccu CLK_BUS_DMA>;
0397 dma-channels = <8>;
0398 dma-requests = <27>;
0399 resets = <&ccu RST_BUS_DMA>;
0400 #dma-cells = <1>;
0401 };
0402
0403 tcon0: lcd-controller@1c0c000 {
0404 compatible = "allwinner,sun50i-a64-tcon-lcd",
0405 "allwinner,sun8i-a83t-tcon-lcd";
0406 reg = <0x01c0c000 0x1000>;
0407 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0408 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
0409 clock-names = "ahb", "tcon-ch0";
0410 clock-output-names = "tcon-pixel-clock";
0411 #clock-cells = <0>;
0412 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
0413 reset-names = "lcd", "lvds";
0414
0415 ports {
0416 #address-cells = <1>;
0417 #size-cells = <0>;
0418
0419 tcon0_in: port@0 {
0420 #address-cells = <1>;
0421 #size-cells = <0>;
0422 reg = <0>;
0423
0424 tcon0_in_mixer0: endpoint@0 {
0425 reg = <0>;
0426 remote-endpoint = <&mixer0_out_tcon0>;
0427 };
0428
0429 tcon0_in_mixer1: endpoint@1 {
0430 reg = <1>;
0431 remote-endpoint = <&mixer1_out_tcon0>;
0432 };
0433 };
0434
0435 tcon0_out: port@1 {
0436 #address-cells = <1>;
0437 #size-cells = <0>;
0438 reg = <1>;
0439
0440 tcon0_out_dsi: endpoint@1 {
0441 reg = <1>;
0442 remote-endpoint = <&dsi_in_tcon0>;
0443 allwinner,tcon-channel = <1>;
0444 };
0445 };
0446 };
0447 };
0448
0449 tcon1: lcd-controller@1c0d000 {
0450 compatible = "allwinner,sun50i-a64-tcon-tv",
0451 "allwinner,sun8i-a83t-tcon-tv";
0452 reg = <0x01c0d000 0x1000>;
0453 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0454 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
0455 clock-names = "ahb", "tcon-ch1";
0456 resets = <&ccu RST_BUS_TCON1>;
0457 reset-names = "lcd";
0458
0459 ports {
0460 #address-cells = <1>;
0461 #size-cells = <0>;
0462
0463 tcon1_in: port@0 {
0464 #address-cells = <1>;
0465 #size-cells = <0>;
0466 reg = <0>;
0467
0468 tcon1_in_mixer0: endpoint@0 {
0469 reg = <0>;
0470 remote-endpoint = <&mixer0_out_tcon1>;
0471 };
0472
0473 tcon1_in_mixer1: endpoint@1 {
0474 reg = <1>;
0475 remote-endpoint = <&mixer1_out_tcon1>;
0476 };
0477 };
0478
0479 tcon1_out: port@1 {
0480 #address-cells = <1>;
0481 #size-cells = <0>;
0482 reg = <1>;
0483
0484 tcon1_out_hdmi: endpoint@1 {
0485 reg = <1>;
0486 remote-endpoint = <&hdmi_in_tcon1>;
0487 };
0488 };
0489 };
0490 };
0491
0492 video-codec@1c0e000 {
0493 compatible = "allwinner,sun50i-a64-video-engine";
0494 reg = <0x01c0e000 0x1000>;
0495 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
0496 <&ccu CLK_DRAM_VE>;
0497 clock-names = "ahb", "mod", "ram";
0498 resets = <&ccu RST_BUS_VE>;
0499 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0500 allwinner,sram = <&ve_sram 1>;
0501 };
0502
0503 mmc0: mmc@1c0f000 {
0504 compatible = "allwinner,sun50i-a64-mmc";
0505 reg = <0x01c0f000 0x1000>;
0506 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
0507 clock-names = "ahb", "mmc";
0508 resets = <&ccu RST_BUS_MMC0>;
0509 reset-names = "ahb";
0510 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0511 max-frequency = <150000000>;
0512 status = "disabled";
0513 #address-cells = <1>;
0514 #size-cells = <0>;
0515 };
0516
0517 mmc1: mmc@1c10000 {
0518 compatible = "allwinner,sun50i-a64-mmc";
0519 reg = <0x01c10000 0x1000>;
0520 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
0521 clock-names = "ahb", "mmc";
0522 resets = <&ccu RST_BUS_MMC1>;
0523 reset-names = "ahb";
0524 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0525 max-frequency = <150000000>;
0526 status = "disabled";
0527 #address-cells = <1>;
0528 #size-cells = <0>;
0529 };
0530
0531 mmc2: mmc@1c11000 {
0532 compatible = "allwinner,sun50i-a64-emmc";
0533 reg = <0x01c11000 0x1000>;
0534 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
0535 clock-names = "ahb", "mmc";
0536 resets = <&ccu RST_BUS_MMC2>;
0537 reset-names = "ahb";
0538 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0539 max-frequency = <150000000>;
0540 status = "disabled";
0541 #address-cells = <1>;
0542 #size-cells = <0>;
0543 };
0544
0545 sid: eeprom@1c14000 {
0546 compatible = "allwinner,sun50i-a64-sid";
0547 reg = <0x1c14000 0x400>;
0548 #address-cells = <1>;
0549 #size-cells = <1>;
0550
0551 ths_calibration: thermal-sensor-calibration@34 {
0552 reg = <0x34 0x8>;
0553 };
0554 };
0555
0556 crypto: crypto@1c15000 {
0557 compatible = "allwinner,sun50i-a64-crypto";
0558 reg = <0x01c15000 0x1000>;
0559 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0560 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
0561 clock-names = "bus", "mod";
0562 resets = <&ccu RST_BUS_CE>;
0563 };
0564
0565 msgbox: mailbox@1c17000 {
0566 compatible = "allwinner,sun50i-a64-msgbox",
0567 "allwinner,sun6i-a31-msgbox";
0568 reg = <0x01c17000 0x1000>;
0569 clocks = <&ccu CLK_BUS_MSGBOX>;
0570 resets = <&ccu RST_BUS_MSGBOX>;
0571 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0572 #mbox-cells = <1>;
0573 };
0574
0575 usb_otg: usb@1c19000 {
0576 compatible = "allwinner,sun8i-a33-musb";
0577 reg = <0x01c19000 0x0400>;
0578 clocks = <&ccu CLK_BUS_OTG>;
0579 resets = <&ccu RST_BUS_OTG>;
0580 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0581 interrupt-names = "mc";
0582 phys = <&usbphy 0>;
0583 phy-names = "usb";
0584 extcon = <&usbphy 0>;
0585 dr_mode = "otg";
0586 status = "disabled";
0587 };
0588
0589 usbphy: phy@1c19400 {
0590 compatible = "allwinner,sun50i-a64-usb-phy";
0591 reg = <0x01c19400 0x14>,
0592 <0x01c1a800 0x4>,
0593 <0x01c1b800 0x4>;
0594 reg-names = "phy_ctrl",
0595 "pmu0",
0596 "pmu1";
0597 clocks = <&ccu CLK_USB_PHY0>,
0598 <&ccu CLK_USB_PHY1>;
0599 clock-names = "usb0_phy",
0600 "usb1_phy";
0601 resets = <&ccu RST_USB_PHY0>,
0602 <&ccu RST_USB_PHY1>;
0603 reset-names = "usb0_reset",
0604 "usb1_reset";
0605 status = "disabled";
0606 #phy-cells = <1>;
0607 };
0608
0609 ehci0: usb@1c1a000 {
0610 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
0611 reg = <0x01c1a000 0x100>;
0612 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0613 clocks = <&ccu CLK_BUS_OHCI0>,
0614 <&ccu CLK_BUS_EHCI0>,
0615 <&ccu CLK_USB_OHCI0>;
0616 resets = <&ccu RST_BUS_OHCI0>,
0617 <&ccu RST_BUS_EHCI0>;
0618 phys = <&usbphy 0>;
0619 phy-names = "usb";
0620 status = "disabled";
0621 };
0622
0623 ohci0: usb@1c1a400 {
0624 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
0625 reg = <0x01c1a400 0x100>;
0626 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0627 clocks = <&ccu CLK_BUS_OHCI0>,
0628 <&ccu CLK_USB_OHCI0>;
0629 resets = <&ccu RST_BUS_OHCI0>;
0630 phys = <&usbphy 0>;
0631 phy-names = "usb";
0632 status = "disabled";
0633 };
0634
0635 ehci1: usb@1c1b000 {
0636 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
0637 reg = <0x01c1b000 0x100>;
0638 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0639 clocks = <&ccu CLK_BUS_OHCI1>,
0640 <&ccu CLK_BUS_EHCI1>,
0641 <&ccu CLK_USB_OHCI1>;
0642 resets = <&ccu RST_BUS_OHCI1>,
0643 <&ccu RST_BUS_EHCI1>;
0644 phys = <&usbphy 1>;
0645 phy-names = "usb";
0646 status = "disabled";
0647 };
0648
0649 ohci1: usb@1c1b400 {
0650 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
0651 reg = <0x01c1b400 0x100>;
0652 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0653 clocks = <&ccu CLK_BUS_OHCI1>,
0654 <&ccu CLK_USB_OHCI1>;
0655 resets = <&ccu RST_BUS_OHCI1>;
0656 phys = <&usbphy 1>;
0657 phy-names = "usb";
0658 status = "disabled";
0659 };
0660
0661 ccu: clock@1c20000 {
0662 compatible = "allwinner,sun50i-a64-ccu";
0663 reg = <0x01c20000 0x400>;
0664 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
0665 clock-names = "hosc", "losc";
0666 #clock-cells = <1>;
0667 #reset-cells = <1>;
0668 };
0669
0670 pio: pinctrl@1c20800 {
0671 compatible = "allwinner,sun50i-a64-pinctrl";
0672 reg = <0x01c20800 0x400>;
0673 interrupt-parent = <&r_intc>;
0674 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0675 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
0676 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0677 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
0678 <&rtc CLK_OSC32K>;
0679 clock-names = "apb", "hosc", "losc";
0680 gpio-controller;
0681 #gpio-cells = <3>;
0682 interrupt-controller;
0683 #interrupt-cells = <3>;
0684
0685 /omit-if-no-ref/
0686 aif2_pins: aif2-pins {
0687 pins = "PB4", "PB5", "PB6", "PB7";
0688 function = "aif2";
0689 };
0690
0691 /omit-if-no-ref/
0692 aif3_pins: aif3-pins {
0693 pins = "PG10", "PG11", "PG12", "PG13";
0694 function = "aif3";
0695 };
0696
0697 csi_pins: csi-pins {
0698 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
0699 "PE7", "PE8", "PE9", "PE10", "PE11";
0700 function = "csi";
0701 };
0702
0703 /omit-if-no-ref/
0704 csi_mclk_pin: csi-mclk-pin {
0705 pins = "PE1";
0706 function = "csi";
0707 };
0708
0709 i2c0_pins: i2c0-pins {
0710 pins = "PH0", "PH1";
0711 function = "i2c0";
0712 };
0713
0714 i2c1_pins: i2c1-pins {
0715 pins = "PH2", "PH3";
0716 function = "i2c1";
0717 };
0718
0719 i2c2_pins: i2c2-pins {
0720 pins = "PE14", "PE15";
0721 function = "i2c2";
0722 };
0723
0724 /omit-if-no-ref/
0725 lcd_rgb666_pins: lcd-rgb666-pins {
0726 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
0727 "PD5", "PD6", "PD7", "PD8", "PD9",
0728 "PD10", "PD11", "PD12", "PD13",
0729 "PD14", "PD15", "PD16", "PD17",
0730 "PD18", "PD19", "PD20", "PD21";
0731 function = "lcd0";
0732 };
0733
0734 mmc0_pins: mmc0-pins {
0735 pins = "PF0", "PF1", "PF2", "PF3",
0736 "PF4", "PF5";
0737 function = "mmc0";
0738 drive-strength = <30>;
0739 bias-pull-up;
0740 };
0741
0742 mmc1_pins: mmc1-pins {
0743 pins = "PG0", "PG1", "PG2", "PG3",
0744 "PG4", "PG5";
0745 function = "mmc1";
0746 drive-strength = <30>;
0747 bias-pull-up;
0748 };
0749
0750 mmc2_pins: mmc2-pins {
0751 pins = "PC5", "PC6", "PC8", "PC9",
0752 "PC10","PC11", "PC12", "PC13",
0753 "PC14", "PC15", "PC16";
0754 function = "mmc2";
0755 drive-strength = <30>;
0756 bias-pull-up;
0757 };
0758
0759 mmc2_ds_pin: mmc2-ds-pin {
0760 pins = "PC1";
0761 function = "mmc2";
0762 drive-strength = <30>;
0763 bias-pull-up;
0764 };
0765
0766 pwm_pin: pwm-pin {
0767 pins = "PD22";
0768 function = "pwm";
0769 };
0770
0771 rmii_pins: rmii-pins {
0772 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
0773 "PD18", "PD19", "PD20", "PD22", "PD23";
0774 function = "emac";
0775 drive-strength = <40>;
0776 };
0777
0778 rgmii_pins: rgmii-pins {
0779 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
0780 "PD13", "PD15", "PD16", "PD17", "PD18",
0781 "PD19", "PD20", "PD21", "PD22", "PD23";
0782 function = "emac";
0783 drive-strength = <40>;
0784 };
0785
0786 spdif_tx_pin: spdif-tx-pin {
0787 pins = "PH8";
0788 function = "spdif";
0789 };
0790
0791 spi0_pins: spi0-pins {
0792 pins = "PC0", "PC1", "PC2", "PC3";
0793 function = "spi0";
0794 };
0795
0796 spi1_pins: spi1-pins {
0797 pins = "PD0", "PD1", "PD2", "PD3";
0798 function = "spi1";
0799 };
0800
0801 uart0_pb_pins: uart0-pb-pins {
0802 pins = "PB8", "PB9";
0803 function = "uart0";
0804 };
0805
0806 uart1_pins: uart1-pins {
0807 pins = "PG6", "PG7";
0808 function = "uart1";
0809 };
0810
0811 uart1_rts_cts_pins: uart1-rts-cts-pins {
0812 pins = "PG8", "PG9";
0813 function = "uart1";
0814 };
0815
0816 uart2_pins: uart2-pins {
0817 pins = "PB0", "PB1";
0818 function = "uart2";
0819 };
0820
0821 uart3_pins: uart3-pins {
0822 pins = "PD0", "PD1";
0823 function = "uart3";
0824 };
0825
0826 uart4_pins: uart4-pins {
0827 pins = "PD2", "PD3";
0828 function = "uart4";
0829 };
0830
0831 uart4_rts_cts_pins: uart4-rts-cts-pins {
0832 pins = "PD4", "PD5";
0833 function = "uart4";
0834 };
0835 };
0836
0837 timer@1c20c00 {
0838 compatible = "allwinner,sun50i-a64-timer",
0839 "allwinner,sun8i-a23-timer";
0840 reg = <0x01c20c00 0xa0>;
0841 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0842 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0843 clocks = <&osc24M>;
0844 };
0845
0846 wdt0: watchdog@1c20ca0 {
0847 compatible = "allwinner,sun50i-a64-wdt",
0848 "allwinner,sun6i-a31-wdt";
0849 reg = <0x01c20ca0 0x20>;
0850 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0851 clocks = <&osc24M>;
0852 };
0853
0854 spdif: spdif@1c21000 {
0855 #sound-dai-cells = <0>;
0856 compatible = "allwinner,sun50i-a64-spdif",
0857 "allwinner,sun8i-h3-spdif";
0858 reg = <0x01c21000 0x400>;
0859 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0860 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
0861 resets = <&ccu RST_BUS_SPDIF>;
0862 clock-names = "apb", "spdif";
0863 dmas = <&dma 2>;
0864 dma-names = "tx";
0865 pinctrl-names = "default";
0866 pinctrl-0 = <&spdif_tx_pin>;
0867 status = "disabled";
0868 };
0869
0870 lradc: lradc@1c21800 {
0871 compatible = "allwinner,sun50i-a64-lradc",
0872 "allwinner,sun8i-a83t-r-lradc";
0873 reg = <0x01c21800 0x400>;
0874 interrupt-parent = <&r_intc>;
0875 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0876 status = "disabled";
0877 };
0878
0879 i2s0: i2s@1c22000 {
0880 #sound-dai-cells = <0>;
0881 compatible = "allwinner,sun50i-a64-i2s",
0882 "allwinner,sun8i-h3-i2s";
0883 reg = <0x01c22000 0x400>;
0884 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0885 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
0886 clock-names = "apb", "mod";
0887 resets = <&ccu RST_BUS_I2S0>;
0888 dma-names = "rx", "tx";
0889 dmas = <&dma 3>, <&dma 3>;
0890 status = "disabled";
0891 };
0892
0893 i2s1: i2s@1c22400 {
0894 #sound-dai-cells = <0>;
0895 compatible = "allwinner,sun50i-a64-i2s",
0896 "allwinner,sun8i-h3-i2s";
0897 reg = <0x01c22400 0x400>;
0898 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0899 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
0900 clock-names = "apb", "mod";
0901 resets = <&ccu RST_BUS_I2S1>;
0902 dma-names = "rx", "tx";
0903 dmas = <&dma 4>, <&dma 4>;
0904 status = "disabled";
0905 };
0906
0907 i2s2: i2s@1c22800 {
0908 #sound-dai-cells = <0>;
0909 compatible = "allwinner,sun50i-a64-i2s",
0910 "allwinner,sun8i-h3-i2s";
0911 reg = <0x01c22800 0x400>;
0912 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0913 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
0914 clock-names = "apb", "mod";
0915 resets = <&ccu RST_BUS_I2S2>;
0916 dma-names = "rx", "tx";
0917 dmas = <&dma 27>, <&dma 27>;
0918 status = "disabled";
0919 };
0920
0921 dai: dai@1c22c00 {
0922 #sound-dai-cells = <0>;
0923 compatible = "allwinner,sun50i-a64-codec-i2s";
0924 reg = <0x01c22c00 0x200>;
0925 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0926 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
0927 clock-names = "apb", "mod";
0928 resets = <&ccu RST_BUS_CODEC>;
0929 dmas = <&dma 15>, <&dma 15>;
0930 dma-names = "rx", "tx";
0931 status = "disabled";
0932 };
0933
0934 codec: codec@1c22e00 {
0935 #sound-dai-cells = <1>;
0936 compatible = "allwinner,sun50i-a64-codec",
0937 "allwinner,sun8i-a33-codec";
0938 reg = <0x01c22e00 0x600>;
0939 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0940 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
0941 clock-names = "bus", "mod";
0942 status = "disabled";
0943 };
0944
0945 ths: thermal-sensor@1c25000 {
0946 compatible = "allwinner,sun50i-a64-ths";
0947 reg = <0x01c25000 0x100>;
0948 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
0949 clock-names = "bus", "mod";
0950 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0951 resets = <&ccu RST_BUS_THS>;
0952 nvmem-cells = <&ths_calibration>;
0953 nvmem-cell-names = "calibration";
0954 #thermal-sensor-cells = <1>;
0955 };
0956
0957 uart0: serial@1c28000 {
0958 compatible = "snps,dw-apb-uart";
0959 reg = <0x01c28000 0x400>;
0960 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0961 reg-shift = <2>;
0962 reg-io-width = <4>;
0963 clocks = <&ccu CLK_BUS_UART0>;
0964 resets = <&ccu RST_BUS_UART0>;
0965 status = "disabled";
0966 };
0967
0968 uart1: serial@1c28400 {
0969 compatible = "snps,dw-apb-uart";
0970 reg = <0x01c28400 0x400>;
0971 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0972 reg-shift = <2>;
0973 reg-io-width = <4>;
0974 clocks = <&ccu CLK_BUS_UART1>;
0975 resets = <&ccu RST_BUS_UART1>;
0976 status = "disabled";
0977 };
0978
0979 uart2: serial@1c28800 {
0980 compatible = "snps,dw-apb-uart";
0981 reg = <0x01c28800 0x400>;
0982 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0983 reg-shift = <2>;
0984 reg-io-width = <4>;
0985 clocks = <&ccu CLK_BUS_UART2>;
0986 resets = <&ccu RST_BUS_UART2>;
0987 status = "disabled";
0988 };
0989
0990 uart3: serial@1c28c00 {
0991 compatible = "snps,dw-apb-uart";
0992 reg = <0x01c28c00 0x400>;
0993 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0994 reg-shift = <2>;
0995 reg-io-width = <4>;
0996 clocks = <&ccu CLK_BUS_UART3>;
0997 resets = <&ccu RST_BUS_UART3>;
0998 status = "disabled";
0999 };
1000
1001 uart4: serial@1c29000 {
1002 compatible = "snps,dw-apb-uart";
1003 reg = <0x01c29000 0x400>;
1004 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1005 reg-shift = <2>;
1006 reg-io-width = <4>;
1007 clocks = <&ccu CLK_BUS_UART4>;
1008 resets = <&ccu RST_BUS_UART4>;
1009 status = "disabled";
1010 };
1011
1012 i2c0: i2c@1c2ac00 {
1013 compatible = "allwinner,sun6i-a31-i2c";
1014 reg = <0x01c2ac00 0x400>;
1015 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1016 clocks = <&ccu CLK_BUS_I2C0>;
1017 resets = <&ccu RST_BUS_I2C0>;
1018 pinctrl-names = "default";
1019 pinctrl-0 = <&i2c0_pins>;
1020 status = "disabled";
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1023 };
1024
1025 i2c1: i2c@1c2b000 {
1026 compatible = "allwinner,sun6i-a31-i2c";
1027 reg = <0x01c2b000 0x400>;
1028 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1029 clocks = <&ccu CLK_BUS_I2C1>;
1030 resets = <&ccu RST_BUS_I2C1>;
1031 pinctrl-names = "default";
1032 pinctrl-0 = <&i2c1_pins>;
1033 status = "disabled";
1034 #address-cells = <1>;
1035 #size-cells = <0>;
1036 };
1037
1038 i2c2: i2c@1c2b400 {
1039 compatible = "allwinner,sun6i-a31-i2c";
1040 reg = <0x01c2b400 0x400>;
1041 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1042 clocks = <&ccu CLK_BUS_I2C2>;
1043 resets = <&ccu RST_BUS_I2C2>;
1044 pinctrl-names = "default";
1045 pinctrl-0 = <&i2c2_pins>;
1046 status = "disabled";
1047 #address-cells = <1>;
1048 #size-cells = <0>;
1049 };
1050
1051 spi0: spi@1c68000 {
1052 compatible = "allwinner,sun8i-h3-spi";
1053 reg = <0x01c68000 0x1000>;
1054 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1055 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
1056 clock-names = "ahb", "mod";
1057 dmas = <&dma 23>, <&dma 23>;
1058 dma-names = "rx", "tx";
1059 pinctrl-names = "default";
1060 pinctrl-0 = <&spi0_pins>;
1061 resets = <&ccu RST_BUS_SPI0>;
1062 status = "disabled";
1063 num-cs = <1>;
1064 #address-cells = <1>;
1065 #size-cells = <0>;
1066 };
1067
1068 spi1: spi@1c69000 {
1069 compatible = "allwinner,sun8i-h3-spi";
1070 reg = <0x01c69000 0x1000>;
1071 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
1073 clock-names = "ahb", "mod";
1074 dmas = <&dma 24>, <&dma 24>;
1075 dma-names = "rx", "tx";
1076 pinctrl-names = "default";
1077 pinctrl-0 = <&spi1_pins>;
1078 resets = <&ccu RST_BUS_SPI1>;
1079 status = "disabled";
1080 num-cs = <1>;
1081 #address-cells = <1>;
1082 #size-cells = <0>;
1083 };
1084
1085 emac: ethernet@1c30000 {
1086 compatible = "allwinner,sun50i-a64-emac";
1087 syscon = <&syscon>;
1088 reg = <0x01c30000 0x10000>;
1089 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1090 interrupt-names = "macirq";
1091 resets = <&ccu RST_BUS_EMAC>;
1092 reset-names = "stmmaceth";
1093 clocks = <&ccu CLK_BUS_EMAC>;
1094 clock-names = "stmmaceth";
1095 status = "disabled";
1096
1097 mdio: mdio {
1098 compatible = "snps,dwmac-mdio";
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1101 };
1102 };
1103
1104 mali: gpu@1c40000 {
1105 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1106 reg = <0x01c40000 0x10000>;
1107 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1114 interrupt-names = "gp",
1115 "gpmmu",
1116 "pp0",
1117 "ppmmu0",
1118 "pp1",
1119 "ppmmu1",
1120 "pmu";
1121 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1122 clock-names = "bus", "core";
1123 resets = <&ccu RST_BUS_GPU>;
1124 operating-points-v2 = <&gpu_opp_table>;
1125 };
1126
1127 gic: interrupt-controller@1c81000 {
1128 compatible = "arm,gic-400";
1129 reg = <0x01c81000 0x1000>,
1130 <0x01c82000 0x2000>,
1131 <0x01c84000 0x2000>,
1132 <0x01c86000 0x2000>;
1133 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1134 interrupt-controller;
1135 #interrupt-cells = <3>;
1136 };
1137
1138 pwm: pwm@1c21400 {
1139 compatible = "allwinner,sun50i-a64-pwm",
1140 "allwinner,sun5i-a13-pwm";
1141 reg = <0x01c21400 0x400>;
1142 clocks = <&osc24M>;
1143 pinctrl-names = "default";
1144 pinctrl-0 = <&pwm_pin>;
1145 #pwm-cells = <3>;
1146 status = "disabled";
1147 };
1148
1149 mbus: dram-controller@1c62000 {
1150 compatible = "allwinner,sun50i-a64-mbus";
1151 reg = <0x01c62000 0x1000>,
1152 <0x01c63000 0x1000>;
1153 reg-names = "mbus", "dram";
1154 clocks = <&ccu CLK_MBUS>,
1155 <&ccu CLK_DRAM>,
1156 <&ccu CLK_BUS_DRAM>;
1157 clock-names = "mbus", "dram", "bus";
1158 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1159 #address-cells = <1>;
1160 #size-cells = <1>;
1161 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1162 #interconnect-cells = <1>;
1163 };
1164
1165 csi: csi@1cb0000 {
1166 compatible = "allwinner,sun50i-a64-csi";
1167 reg = <0x01cb0000 0x1000>;
1168 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1169 clocks = <&ccu CLK_BUS_CSI>,
1170 <&ccu CLK_CSI_SCLK>,
1171 <&ccu CLK_DRAM_CSI>;
1172 clock-names = "bus", "mod", "ram";
1173 resets = <&ccu RST_BUS_CSI>;
1174 pinctrl-names = "default";
1175 pinctrl-0 = <&csi_pins>;
1176 status = "disabled";
1177 };
1178
1179 dsi: dsi@1ca0000 {
1180 compatible = "allwinner,sun50i-a64-mipi-dsi";
1181 reg = <0x01ca0000 0x1000>;
1182 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1183 clocks = <&ccu CLK_BUS_MIPI_DSI>;
1184 resets = <&ccu RST_BUS_MIPI_DSI>;
1185 phys = <&dphy>;
1186 phy-names = "dphy";
1187 status = "disabled";
1188 #address-cells = <1>;
1189 #size-cells = <0>;
1190
1191 port {
1192 dsi_in_tcon0: endpoint {
1193 remote-endpoint = <&tcon0_out_dsi>;
1194 };
1195 };
1196 };
1197
1198 dphy: d-phy@1ca1000 {
1199 compatible = "allwinner,sun50i-a64-mipi-dphy",
1200 "allwinner,sun6i-a31-mipi-dphy";
1201 reg = <0x01ca1000 0x1000>;
1202 clocks = <&ccu CLK_BUS_MIPI_DSI>,
1203 <&ccu CLK_DSI_DPHY>;
1204 clock-names = "bus", "mod";
1205 resets = <&ccu RST_BUS_MIPI_DSI>;
1206 status = "disabled";
1207 #phy-cells = <0>;
1208 };
1209
1210 deinterlace: deinterlace@1e00000 {
1211 compatible = "allwinner,sun50i-a64-deinterlace",
1212 "allwinner,sun8i-h3-deinterlace";
1213 reg = <0x01e00000 0x20000>;
1214 clocks = <&ccu CLK_BUS_DEINTERLACE>,
1215 <&ccu CLK_DEINTERLACE>,
1216 <&ccu CLK_DRAM_DEINTERLACE>;
1217 clock-names = "bus", "mod", "ram";
1218 resets = <&ccu RST_BUS_DEINTERLACE>;
1219 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1220 interconnects = <&mbus 9>;
1221 interconnect-names = "dma-mem";
1222 };
1223
1224 hdmi: hdmi@1ee0000 {
1225 compatible = "allwinner,sun50i-a64-dw-hdmi",
1226 "allwinner,sun8i-a83t-dw-hdmi";
1227 reg = <0x01ee0000 0x10000>;
1228 reg-io-width = <1>;
1229 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1230 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1231 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
1232 clock-names = "iahb", "isfr", "tmds", "cec";
1233 resets = <&ccu RST_BUS_HDMI1>;
1234 reset-names = "ctrl";
1235 phys = <&hdmi_phy>;
1236 phy-names = "phy";
1237 status = "disabled";
1238
1239 ports {
1240 #address-cells = <1>;
1241 #size-cells = <0>;
1242
1243 hdmi_in: port@0 {
1244 reg = <0>;
1245
1246 hdmi_in_tcon1: endpoint {
1247 remote-endpoint = <&tcon1_out_hdmi>;
1248 };
1249 };
1250
1251 hdmi_out: port@1 {
1252 reg = <1>;
1253 };
1254 };
1255 };
1256
1257 hdmi_phy: hdmi-phy@1ef0000 {
1258 compatible = "allwinner,sun50i-a64-hdmi-phy";
1259 reg = <0x01ef0000 0x10000>;
1260 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1261 <&ccu CLK_PLL_VIDEO0>;
1262 clock-names = "bus", "mod", "pll-0";
1263 resets = <&ccu RST_BUS_HDMI0>;
1264 reset-names = "phy";
1265 #phy-cells = <0>;
1266 };
1267
1268 rtc: rtc@1f00000 {
1269 compatible = "allwinner,sun50i-a64-rtc",
1270 "allwinner,sun8i-h3-rtc";
1271 reg = <0x01f00000 0x400>;
1272 interrupt-parent = <&r_intc>;
1273 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1275 clock-output-names = "osc32k", "osc32k-out", "iosc";
1276 clocks = <&osc32k>;
1277 #clock-cells = <1>;
1278 };
1279
1280 r_intc: interrupt-controller@1f00c00 {
1281 compatible = "allwinner,sun50i-a64-r-intc",
1282 "allwinner,sun6i-a31-r-intc";
1283 interrupt-controller;
1284 #interrupt-cells = <3>;
1285 reg = <0x01f00c00 0x400>;
1286 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1287 };
1288
1289 r_ccu: clock@1f01400 {
1290 compatible = "allwinner,sun50i-a64-r-ccu";
1291 reg = <0x01f01400 0x100>;
1292 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
1293 <&ccu CLK_PLL_PERIPH0>;
1294 clock-names = "hosc", "losc", "iosc", "pll-periph";
1295 #clock-cells = <1>;
1296 #reset-cells = <1>;
1297 };
1298
1299 codec_analog: codec-analog@1f015c0 {
1300 compatible = "allwinner,sun50i-a64-codec-analog";
1301 reg = <0x01f015c0 0x4>;
1302 status = "disabled";
1303 };
1304
1305 r_i2c: i2c@1f02400 {
1306 compatible = "allwinner,sun50i-a64-i2c",
1307 "allwinner,sun6i-a31-i2c";
1308 reg = <0x01f02400 0x400>;
1309 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1310 clocks = <&r_ccu CLK_APB0_I2C>;
1311 resets = <&r_ccu RST_APB0_I2C>;
1312 status = "disabled";
1313 #address-cells = <1>;
1314 #size-cells = <0>;
1315 };
1316
1317 r_ir: ir@1f02000 {
1318 compatible = "allwinner,sun50i-a64-ir",
1319 "allwinner,sun6i-a31-ir";
1320 reg = <0x01f02000 0x400>;
1321 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1322 clock-names = "apb", "ir";
1323 resets = <&r_ccu RST_APB0_IR>;
1324 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1325 pinctrl-names = "default";
1326 pinctrl-0 = <&r_ir_rx_pin>;
1327 status = "disabled";
1328 };
1329
1330 r_pwm: pwm@1f03800 {
1331 compatible = "allwinner,sun50i-a64-pwm",
1332 "allwinner,sun5i-a13-pwm";
1333 reg = <0x01f03800 0x400>;
1334 clocks = <&osc24M>;
1335 pinctrl-names = "default";
1336 pinctrl-0 = <&r_pwm_pin>;
1337 #pwm-cells = <3>;
1338 status = "disabled";
1339 };
1340
1341 r_pio: pinctrl@1f02c00 {
1342 compatible = "allwinner,sun50i-a64-r-pinctrl";
1343 reg = <0x01f02c00 0x400>;
1344 interrupt-parent = <&r_intc>;
1345 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1346 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1347 clock-names = "apb", "hosc", "losc";
1348 gpio-controller;
1349 #gpio-cells = <3>;
1350 interrupt-controller;
1351 #interrupt-cells = <3>;
1352
1353 r_i2c_pl89_pins: r-i2c-pl89-pins {
1354 pins = "PL8", "PL9";
1355 function = "s_i2c";
1356 };
1357
1358 r_ir_rx_pin: r-ir-rx-pin {
1359 pins = "PL11";
1360 function = "s_cir_rx";
1361 };
1362
1363 r_pwm_pin: r-pwm-pin {
1364 pins = "PL10";
1365 function = "s_pwm";
1366 };
1367
1368 r_rsb_pins: r-rsb-pins {
1369 pins = "PL0", "PL1";
1370 function = "s_rsb";
1371 };
1372 };
1373
1374 r_rsb: rsb@1f03400 {
1375 compatible = "allwinner,sun8i-a23-rsb";
1376 reg = <0x01f03400 0x400>;
1377 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1378 clocks = <&r_ccu 6>;
1379 clock-frequency = <3000000>;
1380 resets = <&r_ccu 2>;
1381 pinctrl-names = "default";
1382 pinctrl-0 = <&r_rsb_pins>;
1383 status = "disabled";
1384 #address-cells = <1>;
1385 #size-cells = <0>;
1386 };
1387 };
1388 };
