arm64/allwinner/sun50i-a64-sopine.dtsi

0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 // Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
0003 // Based on sun50i-a64-pine64.dts, which is:
0004 //   Copyright (c) 2016 ARM Ltd.
0005
0006 #include "sun50i-a64.dtsi"
0007 #include "sun50i-a64-cpu-opp.dtsi"
0008
0009 #include <dt-bindings/gpio/gpio.h>
0010
0011 &codec_analog {
0012         cpvdd-supply = <&reg_eldo1>;
0013 };
0014
0015 &cpu0 {
0016         cpu-supply = <&reg_dcdc2>;
0017 };
0018
0019 &cpu1 {
0020         cpu-supply = <&reg_dcdc2>;
0021 };
0022
0023 &cpu2 {
0024         cpu-supply = <&reg_dcdc2>;
0025 };
0026
0027 &cpu3 {
0028         cpu-supply = <&reg_dcdc2>;
0029 };
0030
0031 &mmc0 {
0032         pinctrl-names = "default";
0033         pinctrl-0 = <&mmc0_pins>;
0034         vmmc-supply = <&reg_dcdc1>;
0035         disable-wp;
0036         bus-width = <4>;
0037         cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 push-pull switch */
0038         status = "okay";
0039 };
0040
0041 &r_rsb {
0042         status = "okay";
0043
0044         axp803: pmic@3a3 {
0045                 compatible = "x-powers,axp803";
0046                 reg = <0x3a3>;
0047                 interrupt-parent = <&r_intc>;
0048                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
0049         };
0050 };
0051
0052 &spi0  {
0053         status = "okay";
0054
0055         flash@0 {
0056                 #address-cells = <1>;
0057                 #size-cells = <1>;
0058                 compatible = "jedec,spi-nor";
0059                 reg = <0>;
0060                 spi-max-frequency = <40000000>;
0061         };
0062 };
0063
0064 #include "axp803.dtsi"
0065
0066 &reg_aldo2 {
0067         regulator-always-on;
0068         regulator-min-microvolt = <1800000>;
0069         regulator-max-microvolt = <3300000>;
0070         regulator-name = "vcc-pl";
0071 };
0072
0073 &reg_aldo3 {
0074         regulator-always-on;
0075         regulator-min-microvolt = <3000000>;
0076         regulator-max-microvolt = <3000000>;
0077         regulator-name = "vcc-pll-avcc";
0078 };
0079
0080 &reg_dcdc1 {
0081         regulator-always-on;
0082         regulator-min-microvolt = <3300000>;
0083         regulator-max-microvolt = <3300000>;
0084         regulator-name = "vcc-3v3";
0085 };
0086
0087 &reg_dcdc2 {
0088         regulator-always-on;
0089         regulator-min-microvolt = <1040000>;
0090         regulator-max-microvolt = <1300000>;
0091         regulator-name = "vdd-cpux";
0092 };
0093
0094 /* DCDC3 is polyphased with DCDC2 */
0095
0096 &reg_dcdc5 {
0097         regulator-always-on;
0098         regulator-min-microvolt = <1200000>;
0099         regulator-max-microvolt = <1200000>;
0100         regulator-name = "vcc-dram";
0101 };
0102
0103 &reg_dcdc6 {
0104         regulator-always-on;
0105         regulator-min-microvolt = <1100000>;
0106         regulator-max-microvolt = <1100000>;
0107         regulator-name = "vdd-sys";
0108 };
0109
0110 &reg_eldo1 {
0111         regulator-always-on;
0112         regulator-min-microvolt = <1800000>;
0113         regulator-max-microvolt = <1800000>;
0114         regulator-name = "vdd-1v8-lpddr";
0115 };
0116
0117 &reg_fldo1 {
0118         regulator-min-microvolt = <1200000>;
0119         regulator-max-microvolt = <1200000>;
0120         regulator-name = "vcc-1v2-hsic";
0121 };
0122
0123 /*
0124  * The A64 chip cannot work without this regulator off, although
0125  * it seems to be only driving the AR100 core.
0126  * Maybe we don't still know well about CPUs domain.
0127  */
0128 &reg_fldo2 {
0129         regulator-always-on;
0130         regulator-min-microvolt = <1100000>;
0131         regulator-max-microvolt = <1100000>;
0132         regulator-name = "vdd-cpus";
0133 };
0134
0135 &reg_rtc_ldo {
0136         regulator-name = "vcc-rtc";
0137 };