0001 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
0002 /*
0003 * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/clock/sun50i-a100-ccu.h>
0008 #include <dt-bindings/clock/sun50i-a100-r-ccu.h>
0009 #include <dt-bindings/reset/sun50i-a100-ccu.h>
0010 #include <dt-bindings/reset/sun50i-a100-r-ccu.h>
0011
0012 / {
0013 interrupt-parent = <&gic>;
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016
0017 cpus {
0018 #address-cells = <1>;
0019 #size-cells = <0>;
0020
0021 cpu0: cpu@0 {
0022 compatible = "arm,cortex-a53";
0023 device_type = "cpu";
0024 reg = <0x0>;
0025 enable-method = "psci";
0026 };
0027
0028 cpu@1 {
0029 compatible = "arm,cortex-a53";
0030 device_type = "cpu";
0031 reg = <0x1>;
0032 enable-method = "psci";
0033 };
0034
0035 cpu@2 {
0036 compatible = "arm,cortex-a53";
0037 device_type = "cpu";
0038 reg = <0x2>;
0039 enable-method = "psci";
0040 };
0041
0042 cpu@3 {
0043 compatible = "arm,cortex-a53";
0044 device_type = "cpu";
0045 reg = <0x3>;
0046 enable-method = "psci";
0047 };
0048 };
0049
0050 psci {
0051 compatible = "arm,psci-1.0";
0052 method = "smc";
0053 };
0054
0055 dcxo24M: dcxo24M-clk {
0056 compatible = "fixed-clock";
0057 clock-frequency = <24000000>;
0058 clock-output-names = "dcxo24M";
0059 #clock-cells = <0>;
0060 };
0061
0062 iosc: internal-osc-clk {
0063 compatible = "fixed-clock";
0064 clock-frequency = <16000000>;
0065 clock-accuracy = <300000000>;
0066 clock-output-names = "iosc";
0067 #clock-cells = <0>;
0068 };
0069
0070 osc32k: osc32k-clk {
0071 compatible = "fixed-clock";
0072 clock-frequency = <32768>;
0073 clock-output-names = "osc32k";
0074 #clock-cells = <0>;
0075 };
0076
0077 timer {
0078 compatible = "arm,armv8-timer";
0079 interrupts = <GIC_PPI 13
0080 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0081 <GIC_PPI 14
0082 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0083 <GIC_PPI 11
0084 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0085 <GIC_PPI 10
0086 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0087 };
0088
0089 soc {
0090 compatible = "simple-bus";
0091 #address-cells = <1>;
0092 #size-cells = <1>;
0093 ranges = <0 0 0 0x3fffffff>;
0094
0095 ccu: clock@3001000 {
0096 compatible = "allwinner,sun50i-a100-ccu";
0097 reg = <0x03001000 0x1000>;
0098 clocks = <&dcxo24M>, <&osc32k>, <&iosc>;
0099 clock-names = "hosc", "losc", "iosc";
0100 #clock-cells = <1>;
0101 #reset-cells = <1>;
0102 };
0103
0104 gic: interrupt-controller@3021000 {
0105 compatible = "arm,gic-400";
0106 reg = <0x03021000 0x1000>, <0x03022000 0x2000>,
0107 <0x03024000 0x2000>, <0x03026000 0x2000>;
0108 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
0109 IRQ_TYPE_LEVEL_HIGH)>;
0110 interrupt-controller;
0111 #interrupt-cells = <3>;
0112 };
0113
0114 efuse@3006000 {
0115 compatible = "allwinner,sun50i-a100-sid",
0116 "allwinner,sun50i-a64-sid";
0117 reg = <0x03006000 0x1000>;
0118 #address-cells = <1>;
0119 #size-cells = <1>;
0120
0121 ths_calibration: calib@14 {
0122 reg = <0x14 8>;
0123 };
0124 };
0125
0126 pio: pinctrl@300b000 {
0127 compatible = "allwinner,sun50i-a100-pinctrl";
0128 reg = <0x0300b000 0x400>;
0129 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
0130 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
0131 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
0132 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
0133 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
0134 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
0135 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0136 clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>;
0137 clock-names = "apb", "hosc", "losc";
0138 gpio-controller;
0139 #gpio-cells = <3>;
0140 interrupt-controller;
0141 #interrupt-cells = <3>;
0142
0143 uart0_pb_pins: uart0-pb-pins {
0144 pins = "PB9", "PB10";
0145 function = "uart0";
0146 };
0147 };
0148
0149 uart0: serial@5000000 {
0150 compatible = "snps,dw-apb-uart";
0151 reg = <0x05000000 0x400>;
0152 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0153 reg-shift = <2>;
0154 reg-io-width = <4>;
0155 clocks = <&ccu CLK_BUS_UART0>;
0156 resets = <&ccu RST_BUS_UART0>;
0157 status = "disabled";
0158 };
0159
0160 uart1: serial@5000400 {
0161 compatible = "snps,dw-apb-uart";
0162 reg = <0x05000400 0x400>;
0163 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0164 reg-shift = <2>;
0165 reg-io-width = <4>;
0166 clocks = <&ccu CLK_BUS_UART1>;
0167 resets = <&ccu RST_BUS_UART1>;
0168 status = "disabled";
0169 };
0170
0171 uart2: serial@5000800 {
0172 compatible = "snps,dw-apb-uart";
0173 reg = <0x05000800 0x400>;
0174 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0175 reg-shift = <2>;
0176 reg-io-width = <4>;
0177 clocks = <&ccu CLK_BUS_UART2>;
0178 resets = <&ccu RST_BUS_UART2>;
0179 status = "disabled";
0180 };
0181
0182 uart3: serial@5000c00 {
0183 compatible = "snps,dw-apb-uart";
0184 reg = <0x05000c00 0x400>;
0185 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0186 reg-shift = <2>;
0187 reg-io-width = <4>;
0188 clocks = <&ccu CLK_BUS_UART3>;
0189 resets = <&ccu RST_BUS_UART3>;
0190 status = "disabled";
0191 };
0192
0193 uart4: serial@5001000 {
0194 compatible = "snps,dw-apb-uart";
0195 reg = <0x05001000 0x400>;
0196 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0197 reg-shift = <2>;
0198 reg-io-width = <4>;
0199 clocks = <&ccu CLK_BUS_UART4>;
0200 resets = <&ccu RST_BUS_UART4>;
0201 status = "disabled";
0202 };
0203
0204 i2c0: i2c@5002000 {
0205 compatible = "allwinner,sun50i-a100-i2c",
0206 "allwinner,sun8i-v536-i2c",
0207 "allwinner,sun6i-a31-i2c";
0208 reg = <0x05002000 0x400>;
0209 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0210 clocks = <&ccu CLK_BUS_I2C0>;
0211 resets = <&ccu RST_BUS_I2C0>;
0212 status = "disabled";
0213 #address-cells = <1>;
0214 #size-cells = <0>;
0215 };
0216
0217 i2c1: i2c@5002400 {
0218 compatible = "allwinner,sun50i-a100-i2c",
0219 "allwinner,sun8i-v536-i2c",
0220 "allwinner,sun6i-a31-i2c";
0221 reg = <0x05002400 0x400>;
0222 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0223 clocks = <&ccu CLK_BUS_I2C1>;
0224 resets = <&ccu RST_BUS_I2C1>;
0225 status = "disabled";
0226 #address-cells = <1>;
0227 #size-cells = <0>;
0228 };
0229
0230 i2c2: i2c@5002800 {
0231 compatible = "allwinner,sun50i-a100-i2c",
0232 "allwinner,sun8i-v536-i2c",
0233 "allwinner,sun6i-a31-i2c";
0234 reg = <0x05002800 0x400>;
0235 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0236 clocks = <&ccu CLK_BUS_I2C2>;
0237 resets = <&ccu RST_BUS_I2C2>;
0238 status = "disabled";
0239 #address-cells = <1>;
0240 #size-cells = <0>;
0241 };
0242
0243 i2c3: i2c@5002c00 {
0244 compatible = "allwinner,sun50i-a100-i2c",
0245 "allwinner,sun8i-v536-i2c",
0246 "allwinner,sun6i-a31-i2c";
0247 reg = <0x05002c00 0x400>;
0248 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0249 clocks = <&ccu CLK_BUS_I2C3>;
0250 resets = <&ccu RST_BUS_I2C3>;
0251 status = "disabled";
0252 #address-cells = <1>;
0253 #size-cells = <0>;
0254 };
0255
0256 ths: thermal-sensor@5070400 {
0257 compatible = "allwinner,sun50i-a100-ths";
0258 reg = <0x05070400 0x100>;
0259 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0260 clocks = <&ccu CLK_BUS_THS>;
0261 clock-names = "bus";
0262 resets = <&ccu RST_BUS_THS>;
0263 nvmem-cells = <&ths_calibration>;
0264 nvmem-cell-names = "calibration";
0265 #thermal-sensor-cells = <1>;
0266 };
0267
0268 r_ccu: clock@7010000 {
0269 compatible = "allwinner,sun50i-a100-r-ccu";
0270 reg = <0x07010000 0x300>;
0271 clocks = <&dcxo24M>, <&osc32k>, <&iosc>,
0272 <&ccu CLK_PLL_PERIPH0>;
0273 clock-names = "hosc", "losc", "iosc", "pll-periph";
0274 #clock-cells = <1>;
0275 #reset-cells = <1>;
0276 };
0277
0278 r_intc: interrupt-controller@7010320 {
0279 compatible = "allwinner,sun50i-a100-nmi",
0280 "allwinner,sun9i-a80-nmi";
0281 interrupt-controller;
0282 #interrupt-cells = <2>;
0283 reg = <0x07010320 0xc>;
0284 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0285 };
0286
0287 r_pio: pinctrl@7022000 {
0288 compatible = "allwinner,sun50i-a100-r-pinctrl";
0289 reg = <0x07022000 0x400>;
0290 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
0291 clocks = <&r_ccu CLK_R_APB1>, <&dcxo24M>, <&osc32k>;
0292 clock-names = "apb", "hosc", "losc";
0293 gpio-controller;
0294 #gpio-cells = <3>;
0295 interrupt-controller;
0296 #interrupt-cells = <3>;
0297
0298 r_i2c0_pins: r-i2c0-pins {
0299 pins = "PL0", "PL1";
0300 function = "s_i2c0";
0301 };
0302
0303 r_i2c1_pins: r-i2c1-pins {
0304 pins = "PL8", "PL9";
0305 function = "s_i2c1";
0306 };
0307 };
0308
0309 r_uart: serial@7080000 {
0310 compatible = "snps,dw-apb-uart";
0311 reg = <0x07080000 0x400>;
0312 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
0313 reg-shift = <2>;
0314 reg-io-width = <4>;
0315 clocks = <&r_ccu CLK_R_APB2_UART>;
0316 resets = <&r_ccu RST_R_APB2_UART>;
0317 status = "disabled";
0318 };
0319
0320 r_i2c0: i2c@7081400 {
0321 compatible = "allwinner,sun50i-a100-i2c",
0322 "allwinner,sun8i-v536-i2c",
0323 "allwinner,sun6i-a31-i2c";
0324 reg = <0x07081400 0x400>;
0325 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
0326 clocks = <&r_ccu CLK_R_APB2_I2C0>;
0327 resets = <&r_ccu RST_R_APB2_I2C0>;
0328 pinctrl-names = "default";
0329 pinctrl-0 = <&r_i2c0_pins>;
0330 status = "disabled";
0331 #address-cells = <1>;
0332 #size-cells = <0>;
0333 };
0334
0335 r_i2c1: i2c@7081800 {
0336 compatible = "allwinner,sun50i-a100-i2c",
0337 "allwinner,sun8i-v536-i2c",
0338 "allwinner,sun6i-a31-i2c";
0339 reg = <0x07081800 0x400>;
0340 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0341 clocks = <&r_ccu CLK_R_APB2_I2C1>;
0342 resets = <&r_ccu RST_R_APB2_I2C1>;
0343 pinctrl-names = "default";
0344 pinctrl-0 = <&r_i2c1_pins>;
0345 status = "disabled";
0346 #address-cells = <1>;
0347 #size-cells = <0>;
0348 };
0349 };
0350
0351 thermal-zones {
0352 cpu-thermal {
0353 polling-delay-passive = <0>;
0354 polling-delay = <0>;
0355 thermal-sensors = <&ths 0>;
0356 };
0357
0358 ddr-thermal {
0359 polling-delay-passive = <0>;
0360 polling-delay = <0>;
0361 thermal-sensors = <&ths 2>;
0362 };
0363
0364 gpu-thermal {
0365 polling-delay-passive = <0>;
0366 polling-delay = <0>;
0367 thermal-sensors = <&ths 1>;
0368 };
0369 };
0370 };
