0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2017 Andreas Färber
0004 */
0005
0006 #include <dt-bindings/clock/actions,s900-cmu.h>
0007 #include <dt-bindings/gpio/gpio.h>
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/reset/actions,s900-reset.h>
0010
0011 / {
0012 compatible = "actions,s900";
0013 interrupt-parent = <&gic>;
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016
0017 cpus {
0018 #address-cells = <2>;
0019 #size-cells = <0>;
0020
0021 cpu0: cpu@0 {
0022 device_type = "cpu";
0023 compatible = "arm,cortex-a53";
0024 reg = <0x0 0x0>;
0025 enable-method = "psci";
0026 };
0027
0028 cpu1: cpu@1 {
0029 device_type = "cpu";
0030 compatible = "arm,cortex-a53";
0031 reg = <0x0 0x1>;
0032 enable-method = "psci";
0033 };
0034
0035 cpu2: cpu@2 {
0036 device_type = "cpu";
0037 compatible = "arm,cortex-a53";
0038 reg = <0x0 0x2>;
0039 enable-method = "psci";
0040 };
0041
0042 cpu3: cpu@3 {
0043 device_type = "cpu";
0044 compatible = "arm,cortex-a53";
0045 reg = <0x0 0x3>;
0046 enable-method = "psci";
0047 };
0048 };
0049
0050 reserved-memory {
0051 #address-cells = <2>;
0052 #size-cells = <2>;
0053 ranges;
0054
0055 secmon@1f000000 {
0056 reg = <0x0 0x1f000000 0x0 0x1000000>;
0057 no-map;
0058 };
0059 };
0060
0061 psci {
0062 compatible = "arm,psci-0.2";
0063 method = "smc";
0064 };
0065
0066 arm-pmu {
0067 compatible = "arm,cortex-a53-pmu";
0068 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0069 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0070 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0071 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0072 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0073 };
0074
0075 timer {
0076 compatible = "arm,armv8-timer";
0077 interrupts = <GIC_PPI 13
0078 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0079 <GIC_PPI 14
0080 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0081 <GIC_PPI 11
0082 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0083 <GIC_PPI 10
0084 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0085 };
0086
0087 hosc: hosc {
0088 compatible = "fixed-clock";
0089 clock-frequency = <24000000>;
0090 #clock-cells = <0>;
0091 };
0092
0093 losc: losc {
0094 compatible = "fixed-clock";
0095 clock-frequency = <32768>;
0096 #clock-cells = <0>;
0097 };
0098
0099 diff24M: diff24M {
0100 compatible = "fixed-clock";
0101 clock-frequency = <24000000>;
0102 #clock-cells = <0>;
0103 };
0104
0105 soc {
0106 compatible = "simple-bus";
0107 #address-cells = <2>;
0108 #size-cells = <2>;
0109 ranges;
0110
0111 gic: interrupt-controller@e00f1000 {
0112 compatible = "arm,gic-400";
0113 reg = <0x0 0xe00f1000 0x0 0x1000>,
0114 <0x0 0xe00f2000 0x0 0x2000>,
0115 <0x0 0xe00f4000 0x0 0x2000>,
0116 <0x0 0xe00f6000 0x0 0x2000>;
0117 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0118 interrupt-controller;
0119 #interrupt-cells = <3>;
0120 };
0121
0122 uart0: serial@e0120000 {
0123 compatible = "actions,s900-uart", "actions,owl-uart";
0124 reg = <0x0 0xe0120000 0x0 0x2000>;
0125 clocks = <&cmu CLK_UART0>;
0126 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0127 status = "disabled";
0128 };
0129
0130 uart1: serial@e0122000 {
0131 compatible = "actions,s900-uart", "actions,owl-uart";
0132 reg = <0x0 0xe0122000 0x0 0x2000>;
0133 clocks = <&cmu CLK_UART1>;
0134 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0135 status = "disabled";
0136 };
0137
0138 uart2: serial@e0124000 {
0139 compatible = "actions,s900-uart", "actions,owl-uart";
0140 reg = <0x0 0xe0124000 0x0 0x2000>;
0141 clocks = <&cmu CLK_UART2>;
0142 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0143 status = "disabled";
0144 };
0145
0146 uart3: serial@e0126000 {
0147 compatible = "actions,s900-uart", "actions,owl-uart";
0148 reg = <0x0 0xe0126000 0x0 0x2000>;
0149 clocks = <&cmu CLK_UART3>;
0150 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0151 status = "disabled";
0152 };
0153
0154 uart4: serial@e0128000 {
0155 compatible = "actions,s900-uart", "actions,owl-uart";
0156 reg = <0x0 0xe0128000 0x0 0x2000>;
0157 clocks = <&cmu CLK_UART4>;
0158 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0159 status = "disabled";
0160 };
0161
0162 uart5: serial@e012a000 {
0163 compatible = "actions,s900-uart", "actions,owl-uart";
0164 reg = <0x0 0xe012a000 0x0 0x2000>;
0165 clocks = <&cmu CLK_UART5>;
0166 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0167 status = "disabled";
0168 };
0169
0170 uart6: serial@e012c000 {
0171 compatible = "actions,s900-uart", "actions,owl-uart";
0172 reg = <0x0 0xe012c000 0x0 0x2000>;
0173 clocks = <&cmu CLK_UART6>;
0174 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0175 status = "disabled";
0176 };
0177
0178 sps: power-controller@e012e000 {
0179 compatible = "actions,s900-sps";
0180 reg = <0x0 0xe012e000 0x0 0x2000>;
0181 #power-domain-cells = <1>;
0182 };
0183
0184 cmu: clock-controller@e0160000 {
0185 compatible = "actions,s900-cmu";
0186 reg = <0x0 0xe0160000 0x0 0x1000>;
0187 clocks = <&hosc>, <&losc>;
0188 #clock-cells = <1>;
0189 #reset-cells = <1>;
0190 };
0191
0192 i2c0: i2c@e0170000 {
0193 compatible = "actions,s900-i2c";
0194 reg = <0 0xe0170000 0 0x1000>;
0195 clocks = <&cmu CLK_I2C0>;
0196 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0197 #address-cells = <1>;
0198 #size-cells = <0>;
0199 status = "disabled";
0200 };
0201
0202 i2c1: i2c@e0172000 {
0203 compatible = "actions,s900-i2c";
0204 reg = <0 0xe0172000 0 0x1000>;
0205 clocks = <&cmu CLK_I2C1>;
0206 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0207 #address-cells = <1>;
0208 #size-cells = <0>;
0209 status = "disabled";
0210 };
0211
0212 i2c2: i2c@e0174000 {
0213 compatible = "actions,s900-i2c";
0214 reg = <0 0xe0174000 0 0x1000>;
0215 clocks = <&cmu CLK_I2C2>;
0216 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0217 #address-cells = <1>;
0218 #size-cells = <0>;
0219 status = "disabled";
0220 };
0221
0222 i2c3: i2c@e0176000 {
0223 compatible = "actions,s900-i2c";
0224 reg = <0 0xe0176000 0 0x1000>;
0225 clocks = <&cmu CLK_I2C3>;
0226 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0227 #address-cells = <1>;
0228 #size-cells = <0>;
0229 status = "disabled";
0230 };
0231
0232 i2c4: i2c@e0178000 {
0233 compatible = "actions,s900-i2c";
0234 reg = <0 0xe0178000 0 0x1000>;
0235 clocks = <&cmu CLK_I2C4>;
0236 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0237 #address-cells = <1>;
0238 #size-cells = <0>;
0239 status = "disabled";
0240 };
0241
0242 i2c5: i2c@e017a000 {
0243 compatible = "actions,s900-i2c";
0244 reg = <0 0xe017a000 0 0x1000>;
0245 clocks = <&cmu CLK_I2C5>;
0246 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0247 #address-cells = <1>;
0248 #size-cells = <0>;
0249 status = "disabled";
0250 };
0251
0252 pinctrl: pinctrl@e01b0000 {
0253 compatible = "actions,s900-pinctrl";
0254 reg = <0x0 0xe01b0000 0x0 0x1000>;
0255 clocks = <&cmu CLK_GPIO>;
0256 gpio-controller;
0257 gpio-ranges = <&pinctrl 0 0 146>;
0258 #gpio-cells = <2>;
0259 interrupt-controller;
0260 #interrupt-cells = <2>;
0261 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
0262 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
0263 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
0264 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
0265 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
0266 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0267 };
0268
0269 timer: timer@e0228000 {
0270 compatible = "actions,s900-timer";
0271 reg = <0x0 0xe0228000 0x0 0x8000>;
0272 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0273 interrupt-names = "timer1";
0274 };
0275
0276 dma: dma-controller@e0260000 {
0277 compatible = "actions,s900-dma";
0278 reg = <0x0 0xe0260000 0x0 0x1000>;
0279 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
0280 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
0281 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
0282 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0283 #dma-cells = <1>;
0284 dma-channels = <12>;
0285 dma-requests = <46>;
0286 clocks = <&cmu CLK_DMAC>;
0287 };
0288
0289 mmc0: mmc@e0330000 {
0290 compatible = "actions,owl-mmc";
0291 reg = <0x0 0xe0330000 0x0 0x4000>;
0292 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0293 clocks = <&cmu CLK_SD0>;
0294 resets = <&cmu RESET_SD0>;
0295 dmas = <&dma 2>;
0296 dma-names = "mmc";
0297 status = "disabled";
0298 };
0299
0300 mmc1: mmc@e0334000 {
0301 compatible = "actions,owl-mmc";
0302 reg = <0x0 0xe0334000 0x0 0x4000>;
0303 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
0304 clocks = <&cmu CLK_SD1>;
0305 resets = <&cmu RESET_SD1>;
0306 dmas = <&dma 3>;
0307 dma-names = "mmc";
0308 status = "disabled";
0309 };
0310
0311 mmc2: mmc@e0338000 {
0312 compatible = "actions,owl-mmc";
0313 reg = <0x0 0xe0338000 0x0 0x4000>;
0314 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
0315 clocks = <&cmu CLK_SD2>;
0316 resets = <&cmu RESET_SD2>;
0317 dmas = <&dma 4>;
0318 dma-names = "mmc";
0319 status = "disabled";
0320 };
0321
0322 mmc3: mmc@e033c000 {
0323 compatible = "actions,owl-mmc";
0324 reg = <0x0 0xe033c000 0x0 0x4000>;
0325 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0326 clocks = <&cmu CLK_SD3>;
0327 resets = <&cmu RESET_SD3>;
0328 dmas = <&dma 46>;
0329 dma-names = "mmc";
0330 status = "disabled";
0331 };
0332 };
0333 };
