0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2017 Andreas Färber
0004 */
0005
0006 #include <dt-bindings/clock/actions,s700-cmu.h>
0007 #include <dt-bindings/interrupt-controller/arm-gic.h>
0008 #include <dt-bindings/power/owl-s700-powergate.h>
0009 #include <dt-bindings/reset/actions,s700-reset.h>
0010
0011 / {
0012 compatible = "actions,s700";
0013 interrupt-parent = <&gic>;
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016
0017 cpus {
0018 #address-cells = <2>;
0019 #size-cells = <0>;
0020
0021 cpu0: cpu@0 {
0022 device_type = "cpu";
0023 compatible = "arm,cortex-a53";
0024 reg = <0x0 0x0>;
0025 enable-method = "psci";
0026 };
0027
0028 cpu1: cpu@1 {
0029 device_type = "cpu";
0030 compatible = "arm,cortex-a53";
0031 reg = <0x0 0x1>;
0032 enable-method = "psci";
0033 };
0034
0035 cpu2: cpu@2 {
0036 device_type = "cpu";
0037 compatible = "arm,cortex-a53";
0038 reg = <0x0 0x2>;
0039 enable-method = "psci";
0040 };
0041
0042 cpu3: cpu@3 {
0043 device_type = "cpu";
0044 compatible = "arm,cortex-a53";
0045 reg = <0x0 0x3>;
0046 enable-method = "psci";
0047 };
0048 };
0049
0050 reserved-memory {
0051 #address-cells = <2>;
0052 #size-cells = <2>;
0053 ranges;
0054
0055 secmon@1f000000 {
0056 reg = <0x0 0x1f000000 0x0 0x1000000>;
0057 no-map;
0058 };
0059 };
0060
0061 psci {
0062 compatible = "arm,psci-0.2";
0063 method = "smc";
0064 };
0065
0066 arm-pmu {
0067 compatible = "arm,cortex-a53-pmu";
0068 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0069 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0070 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0071 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0072 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0073 };
0074
0075 timer {
0076 compatible = "arm,armv8-timer";
0077 interrupts = <GIC_PPI 13
0078 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0079 <GIC_PPI 14
0080 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0081 <GIC_PPI 11
0082 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0083 <GIC_PPI 10
0084 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0085 };
0086
0087 hosc: hosc {
0088 compatible = "fixed-clock";
0089 clock-frequency = <24000000>;
0090 #clock-cells = <0>;
0091 };
0092
0093 losc: losc {
0094 compatible = "fixed-clock";
0095 clock-frequency = <32768>;
0096 #clock-cells = <0>;
0097 };
0098
0099 soc {
0100 compatible = "simple-bus";
0101 #address-cells = <2>;
0102 #size-cells = <2>;
0103 ranges;
0104
0105 gic: interrupt-controller@e00f1000 {
0106 compatible = "arm,gic-400";
0107 reg = <0x0 0xe00f1000 0x0 0x1000>,
0108 <0x0 0xe00f2000 0x0 0x2000>,
0109 <0x0 0xe00f4000 0x0 0x2000>,
0110 <0x0 0xe00f6000 0x0 0x2000>;
0111 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0112 interrupt-controller;
0113 #interrupt-cells = <3>;
0114 };
0115
0116 uart0: serial@e0120000 {
0117 compatible = "actions,s900-uart", "actions,owl-uart";
0118 reg = <0x0 0xe0120000 0x0 0x2000>;
0119 clocks = <&cmu CLK_UART0>;
0120 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0121 status = "disabled";
0122 };
0123
0124 uart1: serial@e0122000 {
0125 compatible = "actions,s900-uart", "actions,owl-uart";
0126 reg = <0x0 0xe0122000 0x0 0x2000>;
0127 clocks = <&cmu CLK_UART1>;
0128 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0129 status = "disabled";
0130 };
0131
0132 uart2: serial@e0124000 {
0133 compatible = "actions,s900-uart", "actions,owl-uart";
0134 reg = <0x0 0xe0124000 0x0 0x2000>;
0135 clocks = <&cmu CLK_UART2>;
0136 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0137 status = "disabled";
0138 };
0139
0140 uart3: serial@e0126000 {
0141 compatible = "actions,s900-uart", "actions,owl-uart";
0142 reg = <0x0 0xe0126000 0x0 0x2000>;
0143 clocks = <&cmu CLK_UART3>;
0144 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0145 status = "disabled";
0146 };
0147
0148 uart4: serial@e0128000 {
0149 compatible = "actions,s900-uart", "actions,owl-uart";
0150 reg = <0x0 0xe0128000 0x0 0x2000>;
0151 clocks = <&cmu CLK_UART4>;
0152 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0153 status = "disabled";
0154 };
0155
0156 uart5: serial@e012a000 {
0157 compatible = "actions,s900-uart", "actions,owl-uart";
0158 reg = <0x0 0xe012a000 0x0 0x2000>;
0159 clocks = <&cmu CLK_UART5>;
0160 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0161 status = "disabled";
0162 };
0163
0164 uart6: serial@e012c000 {
0165 compatible = "actions,s900-uart", "actions,owl-uart";
0166 reg = <0x0 0xe012c000 0x0 0x2000>;
0167 clocks = <&cmu CLK_UART6>;
0168 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0169 status = "disabled";
0170 };
0171
0172 cmu: clock-controller@e0168000 {
0173 compatible = "actions,s700-cmu";
0174 reg = <0x0 0xe0168000 0x0 0x1000>;
0175 clocks = <&hosc>, <&losc>;
0176 #clock-cells = <1>;
0177 #reset-cells = <1>;
0178 };
0179
0180 i2c0: i2c@e0170000 {
0181 compatible = "actions,s700-i2c";
0182 reg = <0 0xe0170000 0 0x1000>;
0183 clocks = <&cmu CLK_I2C0>;
0184 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0185 #address-cells = <1>;
0186 #size-cells = <0>;
0187 status = "disabled";
0188 };
0189
0190 i2c1: i2c@e0174000 {
0191 compatible = "actions,s700-i2c";
0192 reg = <0 0xe0174000 0 0x1000>;
0193 clocks = <&cmu CLK_I2C1>;
0194 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0195 #address-cells = <1>;
0196 #size-cells = <0>;
0197 status = "disabled";
0198 };
0199
0200 i2c2: i2c@e0178000 {
0201 compatible = "actions,s700-i2c";
0202 reg = <0 0xe0178000 0 0x1000>;
0203 clocks = <&cmu CLK_I2C2>;
0204 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0205 #address-cells = <1>;
0206 #size-cells = <0>;
0207 status = "disabled";
0208 };
0209
0210 i2c3: i2c@e017c000 {
0211 compatible = "actions,s700-i2c";
0212 reg = <0 0xe017c000 0 0x1000>;
0213 clocks = <&cmu CLK_I2C3>;
0214 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0215 #address-cells = <1>;
0216 #size-cells = <0>;
0217 status = "disabled";
0218 };
0219
0220 sps: power-controller@e01b0100 {
0221 compatible = "actions,s700-sps";
0222 reg = <0x0 0xe01b0100 0x0 0x100>;
0223 #power-domain-cells = <1>;
0224 };
0225
0226 timer: timer@e024c000 {
0227 compatible = "actions,s700-timer";
0228 reg = <0x0 0xe024c000 0x0 0x4000>;
0229 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0230 interrupt-names = "timer1";
0231 };
0232
0233 pinctrl: pinctrl@e01b0000 {
0234 compatible = "actions,s700-pinctrl";
0235 reg = <0x0 0xe01b0000 0x0 0x100>;
0236 clocks = <&cmu CLK_GPIO>;
0237 gpio-controller;
0238 gpio-ranges = <&pinctrl 0 0 136>;
0239 #gpio-cells = <2>;
0240 interrupt-controller;
0241 #interrupt-cells = <2>;
0242 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
0243 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
0244 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
0245 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
0246 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
0247 };
0248
0249 dma: dma-controller@e0230000 {
0250 compatible = "actions,s700-dma";
0251 reg = <0x0 0xe0230000 0x0 0x1000>;
0252 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
0253 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
0254 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
0255 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0256 #dma-cells = <1>;
0257 dma-channels = <10>;
0258 dma-requests = <44>;
0259 clocks = <&cmu CLK_DMAC>;
0260 power-domains = <&sps S700_PD_DMA>;
0261 };
0262 };
0263 };
