OSCL-LXR |
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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright Altera Corporation (C) 2014. All rights reserved.
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
0008
0009 / {
0010 #address-cells = <1>;
0011 #size-cells = <1>;
0012
0013 cpus {
0014 #address-cells = <1>;
0015 #size-cells = <0>;
0016 enable-method = "altr,socfpga-a10-smp";
0017
0018 cpu0: cpu@0 {
0019 compatible = "arm,cortex-a9";
0020 device_type = "cpu";
0021 reg = <0>;
0022 next-level-cache = <&L2>;
0023 };
0024 cpu1: cpu@1 {
0025 compatible = "arm,cortex-a9";
0026 device_type = "cpu";
0027 reg = <1>;
0028 next-level-cache = <&L2>;
0029 };
0030 };
0031
0032 pmu: pmu@ff111000 {
0033 compatible = "arm,cortex-a9-pmu";
0034 interrupt-parent = <&intc>;
0035 interrupts = <0 124 4>, <0 125 4>;
0036 interrupt-affinity = <&cpu0>, <&cpu1>;
0037 reg = <0xff111000 0x1000>,
0038 <0xff113000 0x1000>;
0039 };
0040
0041 intc: interrupt-controller@ffffd000 {
0042 compatible = "arm,cortex-a9-gic";
0043 #interrupt-cells = <3>;
0044 interrupt-controller;
0045 reg = <0xffffd000 0x1000>,
0046 <0xffffc100 0x100>;
0047 };
0048
0049 soc {
0050 #address-cells = <1>;
0051 #size-cells = <1>;
0052 compatible = "simple-bus";
0053 device_type = "soc";
0054 interrupt-parent = <&intc>;
0055 ranges;
0056
0057 amba {
0058 compatible = "simple-bus";
0059 #address-cells = <1>;
0060 #size-cells = <1>;
0061 ranges;
0062
0063 pdma: pdma@ffda1000 {
0064 compatible = "arm,pl330", "arm,primecell";
0065 reg = <0xffda1000 0x1000>;
0066 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
0067 <0 84 IRQ_TYPE_LEVEL_HIGH>,
0068 <0 85 IRQ_TYPE_LEVEL_HIGH>,
0069 <0 86 IRQ_TYPE_LEVEL_HIGH>,
0070 <0 87 IRQ_TYPE_LEVEL_HIGH>,
0071 <0 88 IRQ_TYPE_LEVEL_HIGH>,
0072 <0 89 IRQ_TYPE_LEVEL_HIGH>,
0073 <0 90 IRQ_TYPE_LEVEL_HIGH>,
0074 <0 91 IRQ_TYPE_LEVEL_HIGH>;
0075 #dma-cells = <1>;
0076 clocks = <&l4_main_clk>;
0077 clock-names = "apb_pclk";
0078 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
0079 reset-names = "dma", "dma-ocp";
0080 };
0081 };
0082
0083 base_fpga_region {
0084 #address-cells = <0x1>;
0085 #size-cells = <0x1>;
0086
0087 compatible = "fpga-region";
0088 fpga-mgr = <&fpga_mgr>;
0089 };
0090
0091 clkmgr@ffd04000 {
0092 compatible = "altr,clk-mgr";
0093 reg = <0xffd04000 0x1000>;
0094
0095 clocks {
0096 #address-cells = <1>;
0097 #size-cells = <0>;
0098
0099 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
0100 #clock-cells = <0>;
0101 compatible = "fixed-clock";
0102 };
0103
0104 cb_intosc_ls_clk: cb_intosc_ls_clk {
0105 #clock-cells = <0>;
0106 compatible = "fixed-clock";
0107 };
0108
0109 f2s_free_clk: f2s_free_clk {
0110 #clock-cells = <0>;
0111 compatible = "fixed-clock";
0112 };
0113
0114 osc1: osc1 {
0115 #clock-cells = <0>;
0116 compatible = "fixed-clock";
0117 };
0118
0119 main_pll: main_pll@40 {
0120 #address-cells = <1>;
0121 #size-cells = <0>;
0122 #clock-cells = <0>;
0123 compatible = "altr,socfpga-a10-pll-clock";
0124 clocks = <&osc1>, <&cb_intosc_ls_clk>,
0125 <&f2s_free_clk>;
0126 reg = <0x40>;
0127
0128 main_mpu_base_clk: main_mpu_base_clk {
0129 #clock-cells = <0>;
0130 compatible = "altr,socfpga-a10-perip-clk";
0131 clocks = <&main_pll>;
0132 div-reg = <0x140 0 11>;
0133 };
0134
0135 main_noc_base_clk: main_noc_base_clk {
0136 #clock-cells = <0>;
0137 compatible = "altr,socfpga-a10-perip-clk";
0138 clocks = <&main_pll>;
0139 div-reg = <0x144 0 11>;
0140 };
0141
0142 main_emaca_clk: main_emaca_clk@68 {
0143 #clock-cells = <0>;
0144 compatible = "altr,socfpga-a10-perip-clk";
0145 clocks = <&main_pll>;
0146 reg = <0x68>;
0147 };
0148
0149 main_emacb_clk: main_emacb_clk@6c {
0150 #clock-cells = <0>;
0151 compatible = "altr,socfpga-a10-perip-clk";
0152 clocks = <&main_pll>;
0153 reg = <0x6C>;
0154 };
0155
0156 main_emac_ptp_clk: main_emac_ptp_clk@70 {
0157 #clock-cells = <0>;
0158 compatible = "altr,socfpga-a10-perip-clk";
0159 clocks = <&main_pll>;
0160 reg = <0x70>;
0161 };
0162
0163 main_gpio_db_clk: main_gpio_db_clk@74 {
0164 #clock-cells = <0>;
0165 compatible = "altr,socfpga-a10-perip-clk";
0166 clocks = <&main_pll>;
0167 reg = <0x74>;
0168 };
0169
0170 main_sdmmc_clk: main_sdmmc_clk@78 {
0171 #clock-cells = <0>;
0172 compatible = "altr,socfpga-a10-perip-clk"
0173 ;
0174 clocks = <&main_pll>;
0175 reg = <0x78>;
0176 };
0177
0178 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
0179 #clock-cells = <0>;
0180 compatible = "altr,socfpga-a10-perip-clk";
0181 clocks = <&main_pll>;
0182 reg = <0x7C>;
0183 };
0184
0185 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
0186 #clock-cells = <0>;
0187 compatible = "altr,socfpga-a10-perip-clk";
0188 clocks = <&main_pll>;
0189 reg = <0x80>;
0190 };
0191
0192 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
0193 #clock-cells = <0>;
0194 compatible = "altr,socfpga-a10-perip-clk";
0195 clocks = <&main_pll>;
0196 reg = <0x84>;
0197 };
0198
0199 main_periph_ref_clk: main_periph_ref_clk@9c {
0200 #clock-cells = <0>;
0201 compatible = "altr,socfpga-a10-perip-clk";
0202 clocks = <&main_pll>;
0203 reg = <0x9C>;
0204 };
0205 };
0206
0207 periph_pll: periph_pll@c0 {
0208 #address-cells = <1>;
0209 #size-cells = <0>;
0210 #clock-cells = <0>;
0211 compatible = "altr,socfpga-a10-pll-clock";
0212 clocks = <&osc1>, <&cb_intosc_ls_clk>,
0213 <&f2s_free_clk>, <&main_periph_ref_clk>;
0214 reg = <0xC0>;
0215
0216 peri_mpu_base_clk: peri_mpu_base_clk {
0217 #clock-cells = <0>;
0218 compatible = "altr,socfpga-a10-perip-clk";
0219 clocks = <&periph_pll>;
0220 div-reg = <0x140 16 11>;
0221 };
0222
0223 peri_noc_base_clk: peri_noc_base_clk {
0224 #clock-cells = <0>;
0225 compatible = "altr,socfpga-a10-perip-clk";
0226 clocks = <&periph_pll>;
0227 div-reg = <0x144 16 11>;
0228 };
0229
0230 peri_emaca_clk: peri_emaca_clk@e8 {
0231 #clock-cells = <0>;
0232 compatible = "altr,socfpga-a10-perip-clk";
0233 clocks = <&periph_pll>;
0234 reg = <0xE8>;
0235 };
0236
0237 peri_emacb_clk: peri_emacb_clk@ec {
0238 #clock-cells = <0>;
0239 compatible = "altr,socfpga-a10-perip-clk";
0240 clocks = <&periph_pll>;
0241 reg = <0xEC>;
0242 };
0243
0244 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
0245 #clock-cells = <0>;
0246 compatible = "altr,socfpga-a10-perip-clk";
0247 clocks = <&periph_pll>;
0248 reg = <0xF0>;
0249 };
0250
0251 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
0252 #clock-cells = <0>;
0253 compatible = "altr,socfpga-a10-perip-clk";
0254 clocks = <&periph_pll>;
0255 reg = <0xF4>;
0256 };
0257
0258 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
0259 #clock-cells = <0>;
0260 compatible = "altr,socfpga-a10-perip-clk";
0261 clocks = <&periph_pll>;
0262 reg = <0xF8>;
0263 };
0264
0265 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
0266 #clock-cells = <0>;
0267 compatible = "altr,socfpga-a10-perip-clk";
0268 clocks = <&periph_pll>;
0269 reg = <0xFC>;
0270 };
0271
0272 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
0273 #clock-cells = <0>;
0274 compatible = "altr,socfpga-a10-perip-clk";
0275 clocks = <&periph_pll>;
0276 reg = <0x100>;
0277 };
0278
0279 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
0280 #clock-cells = <0>;
0281 compatible = "altr,socfpga-a10-perip-clk";
0282 clocks = <&periph_pll>;
0283 reg = <0x104>;
0284 };
0285 };
0286
0287 mpu_free_clk: mpu_free_clk@60 {
0288 #clock-cells = <0>;
0289 compatible = "altr,socfpga-a10-perip-clk";
0290 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
0291 <&osc1>, <&cb_intosc_hs_div2_clk>,
0292 <&f2s_free_clk>;
0293 reg = <0x60>;
0294 };
0295
0296 noc_free_clk: noc_free_clk@64 {
0297 #clock-cells = <0>;
0298 compatible = "altr,socfpga-a10-perip-clk";
0299 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
0300 <&osc1>, <&cb_intosc_hs_div2_clk>,
0301 <&f2s_free_clk>;
0302 reg = <0x64>;
0303 };
0304
0305 s2f_user1_free_clk: s2f_user1_free_clk@104 {
0306 #clock-cells = <0>;
0307 compatible = "altr,socfpga-a10-perip-clk";
0308 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
0309 <&osc1>, <&cb_intosc_hs_div2_clk>,
0310 <&f2s_free_clk>;
0311 reg = <0x104>;
0312 };
0313
0314 sdmmc_free_clk: sdmmc_free_clk@f8 {
0315 #clock-cells = <0>;
0316 compatible = "altr,socfpga-a10-perip-clk";
0317 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
0318 <&osc1>, <&cb_intosc_hs_div2_clk>,
0319 <&f2s_free_clk>;
0320 fixed-divider = <4>;
0321 reg = <0xF8>;
0322 };
0323
0324 l4_sys_free_clk: l4_sys_free_clk {
0325 #clock-cells = <0>;
0326 compatible = "altr,socfpga-a10-perip-clk";
0327 clocks = <&noc_free_clk>;
0328 fixed-divider = <4>;
0329 };
0330
0331 l4_main_clk: l4_main_clk {
0332 #clock-cells = <0>;
0333 compatible = "altr,socfpga-a10-gate-clk";
0334 clocks = <&noc_free_clk>;
0335 div-reg = <0xA8 0 2>;
0336 clk-gate = <0x48 1>;
0337 };
0338
0339 l4_mp_clk: l4_mp_clk {
0340 #clock-cells = <0>;
0341 compatible = "altr,socfpga-a10-gate-clk";
0342 clocks = <&noc_free_clk>;
0343 div-reg = <0xA8 8 2>;
0344 clk-gate = <0x48 2>;
0345 };
0346
0347 l4_sp_clk: l4_sp_clk {
0348 #clock-cells = <0>;
0349 compatible = "altr,socfpga-a10-gate-clk";
0350 clocks = <&noc_free_clk>;
0351 div-reg = <0xA8 16 2>;
0352 clk-gate = <0x48 3>;
0353 };
0354
0355 mpu_periph_clk: mpu_periph_clk {
0356 #clock-cells = <0>;
0357 compatible = "altr,socfpga-a10-gate-clk";
0358 clocks = <&mpu_free_clk>;
0359 fixed-divider = <4>;
0360 clk-gate = <0x48 0>;
0361 };
0362
0363 sdmmc_clk: sdmmc_clk {
0364 #clock-cells = <0>;
0365 compatible = "altr,socfpga-a10-gate-clk";
0366 clocks = <&sdmmc_free_clk>;
0367 clk-gate = <0xC8 5>;
0368 clk-phase = <0 135>;
0369 };
0370
0371 qspi_clk: qspi_clk {
0372 #clock-cells = <0>;
0373 compatible = "altr,socfpga-a10-gate-clk";
0374 clocks = <&l4_main_clk>;
0375 clk-gate = <0xC8 11>;
0376 };
0377
0378 nand_x_clk: nand_x_clk {
0379 #clock-cells = <0>;
0380 compatible = "altr,socfpga-a10-gate-clk";
0381 clocks = <&l4_mp_clk>;
0382 clk-gate = <0xC8 10>;
0383 };
0384
0385 nand_ecc_clk: nand_ecc_clk {
0386 #clock-cells = <0>;
0387 compatible = "altr,socfpga-a10-gate-clk";
0388 clocks = <&nand_x_clk>;
0389 clk-gate = <0xC8 10>;
0390 };
0391
0392 nand_clk: nand_clk {
0393 #clock-cells = <0>;
0394 compatible = "altr,socfpga-a10-gate-clk";
0395 clocks = <&nand_x_clk>;
0396 fixed-divider = <4>;
0397 clk-gate = <0xC8 10>;
0398 };
0399
0400 spi_m_clk: spi_m_clk {
0401 #clock-cells = <0>;
0402 compatible = "altr,socfpga-a10-gate-clk";
0403 clocks = <&l4_main_clk>;
0404 clk-gate = <0xC8 9>;
0405 };
0406
0407 usb_clk: usb_clk {
0408 #clock-cells = <0>;
0409 compatible = "altr,socfpga-a10-gate-clk";
0410 clocks = <&l4_mp_clk>;
0411 clk-gate = <0xC8 8>;
0412 };
0413
0414 s2f_usr1_clk: s2f_usr1_clk {
0415 #clock-cells = <0>;
0416 compatible = "altr,socfpga-a10-gate-clk";
0417 clocks = <&peri_s2f_usr1_clk>;
0418 clk-gate = <0xC8 6>;
0419 };
0420 };
0421 };
0422
0423 socfpga_axi_setup: stmmac-axi-config {
0424 snps,wr_osr_lmt = <0xf>;
0425 snps,rd_osr_lmt = <0xf>;
0426 snps,blen = <0 0 0 0 16 0 0>;
0427 };
0428
0429 gmac0: ethernet@ff800000 {
0430 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
0431 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
0432 reg = <0xff800000 0x2000>;
0433 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
0434 interrupt-names = "macirq";
0435 /* Filled in by bootloader */
0436 mac-address = [00 00 00 00 00 00];
0437 snps,multicast-filter-bins = <256>;
0438 snps,perfect-filter-entries = <128>;
0439 tx-fifo-depth = <4096>;
0440 rx-fifo-depth = <16384>;
0441 clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
0442 clock-names = "stmmaceth", "ptp_ref";
0443 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
0444 reset-names = "stmmaceth", "stmmaceth-ocp";
0445 snps,axi-config = <&socfpga_axi_setup>;
0446 status = "disabled";
0447 };
0448
0449 gmac1: ethernet@ff802000 {
0450 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
0451 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
0452 reg = <0xff802000 0x2000>;
0453 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
0454 interrupt-names = "macirq";
0455 /* Filled in by bootloader */
0456 mac-address = [00 00 00 00 00 00];
0457 snps,multicast-filter-bins = <256>;
0458 snps,perfect-filter-entries = <128>;
0459 tx-fifo-depth = <4096>;
0460 rx-fifo-depth = <16384>;
0461 clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
0462 clock-names = "stmmaceth", "ptp_ref";
0463 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
0464 reset-names = "stmmaceth", "stmmaceth-ocp";
0465 snps,axi-config = <&socfpga_axi_setup>;
0466 status = "disabled";
0467 };
0468
0469 gmac2: ethernet@ff804000 {
0470 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
0471 altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
0472 reg = <0xff804000 0x2000>;
0473 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
0474 interrupt-names = "macirq";
0475 /* Filled in by bootloader */
0476 mac-address = [00 00 00 00 00 00];
0477 snps,multicast-filter-bins = <256>;
0478 snps,perfect-filter-entries = <128>;
0479 tx-fifo-depth = <4096>;
0480 rx-fifo-depth = <16384>;
0481 clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
0482 clock-names = "stmmaceth", "ptp_ref";
0483 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
0484 reset-names = "stmmaceth", "stmmaceth-ocp";
0485 snps,axi-config = <&socfpga_axi_setup>;
0486 status = "disabled";
0487 };
0488
0489 gpio0: gpio@ffc02900 {
0490 #address-cells = <1>;
0491 #size-cells = <0>;
0492 compatible = "snps,dw-apb-gpio";
0493 reg = <0xffc02900 0x100>;
0494 resets = <&rst GPIO0_RESET>;
0495 status = "disabled";
0496
0497 porta: gpio-controller@0 {
0498 compatible = "snps,dw-apb-gpio-port";
0499 gpio-controller;
0500 #gpio-cells = <2>;
0501 snps,nr-gpios = <29>;
0502 reg = <0>;
0503 interrupt-controller;
0504 #interrupt-cells = <2>;
0505 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
0506 };
0507 };
0508
0509 gpio1: gpio@ffc02a00 {
0510 #address-cells = <1>;
0511 #size-cells = <0>;
0512 compatible = "snps,dw-apb-gpio";
0513 reg = <0xffc02a00 0x100>;
0514 resets = <&rst GPIO1_RESET>;
0515 status = "disabled";
0516
0517 portb: gpio-controller@0 {
0518 compatible = "snps,dw-apb-gpio-port";
0519 gpio-controller;
0520 #gpio-cells = <2>;
0521 snps,nr-gpios = <29>;
0522 reg = <0>;
0523 interrupt-controller;
0524 #interrupt-cells = <2>;
0525 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
0526 };
0527 };
0528
0529 gpio2: gpio@ffc02b00 {
0530 #address-cells = <1>;
0531 #size-cells = <0>;
0532 compatible = "snps,dw-apb-gpio";
0533 reg = <0xffc02b00 0x100>;
0534 resets = <&rst GPIO2_RESET>;
0535 status = "disabled";
0536
0537 portc: gpio-controller@0 {
0538 compatible = "snps,dw-apb-gpio-port";
0539 gpio-controller;
0540 #gpio-cells = <2>;
0541 snps,nr-gpios = <27>;
0542 reg = <0>;
0543 interrupt-controller;
0544 #interrupt-cells = <2>;
0545 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
0546 };
0547 };
0548
0549 fpga_mgr: fpga-mgr@ffd03000 {
0550 compatible = "altr,socfpga-a10-fpga-mgr";
0551 reg = <0xffd03000 0x100
0552 0xffcfe400 0x20>;
0553 clocks = <&l4_mp_clk>;
0554 resets = <&rst FPGAMGR_RESET>;
0555 reset-names = "fpgamgr";
0556 };
0557
0558 i2c0: i2c@ffc02200 {
0559 #address-cells = <1>;
0560 #size-cells = <0>;
0561 compatible = "snps,designware-i2c";
0562 reg = <0xffc02200 0x100>;
0563 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
0564 clocks = <&l4_sp_clk>;
0565 resets = <&rst I2C0_RESET>;
0566 status = "disabled";
0567 };
0568
0569 i2c1: i2c@ffc02300 {
0570 #address-cells = <1>;
0571 #size-cells = <0>;
0572 compatible = "snps,designware-i2c";
0573 reg = <0xffc02300 0x100>;
0574 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
0575 clocks = <&l4_sp_clk>;
0576 resets = <&rst I2C1_RESET>;
0577 status = "disabled";
0578 };
0579
0580 i2c2: i2c@ffc02400 {
0581 #address-cells = <1>;
0582 #size-cells = <0>;
0583 compatible = "snps,designware-i2c";
0584 reg = <0xffc02400 0x100>;
0585 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
0586 clocks = <&l4_sp_clk>;
0587 resets = <&rst I2C2_RESET>;
0588 status = "disabled";
0589 };
0590
0591 i2c3: i2c@ffc02500 {
0592 #address-cells = <1>;
0593 #size-cells = <0>;
0594 compatible = "snps,designware-i2c";
0595 reg = <0xffc02500 0x100>;
0596 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
0597 clocks = <&l4_sp_clk>;
0598 resets = <&rst I2C3_RESET>;
0599 status = "disabled";
0600 };
0601
0602 i2c4: i2c@ffc02600 {
0603 #address-cells = <1>;
0604 #size-cells = <0>;
0605 compatible = "snps,designware-i2c";
0606 reg = <0xffc02600 0x100>;
0607 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
0608 clocks = <&l4_sp_clk>;
0609 resets = <&rst I2C4_RESET>;
0610 status = "disabled";
0611 };
0612
0613 spi0: spi@ffda4000 {
0614 compatible = "snps,dw-apb-ssi";
0615 #address-cells = <1>;
0616 #size-cells = <0>;
0617 reg = <0xffda4000 0x100>;
0618 interrupts = <0 101 4>;
0619 num-cs = <4>;
0620 /*32bit_access;*/
0621 clocks = <&spi_m_clk>;
0622 resets = <&rst SPIM0_RESET>;
0623 reset-names = "spi";
0624 status = "disabled";
0625 };
0626
0627 spi1: spi@ffda5000 {
0628 compatible = "snps,dw-apb-ssi";
0629 #address-cells = <1>;
0630 #size-cells = <0>;
0631 reg = <0xffda5000 0x100>;
0632 interrupts = <0 102 4>;
0633 num-cs = <4>;
0634 /*32bit_access;*/
0635 tx-dma-channel = <&pdma 16>;
0636 rx-dma-channel = <&pdma 17>;
0637 clocks = <&spi_m_clk>;
0638 resets = <&rst SPIM1_RESET>;
0639 reset-names = "spi";
0640 status = "disabled";
0641 };
0642
0643 sdr: sdr@ffcfb100 {
0644 compatible = "altr,sdr-ctl", "syscon";
0645 reg = <0xffcfb100 0x80>;
0646 };
0647
0648 L2: cache-controller@fffff000 {
0649 compatible = "arm,pl310-cache";
0650 reg = <0xfffff000 0x1000>;
0651 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
0652 cache-unified;
0653 cache-level = <2>;
0654 prefetch-data = <1>;
0655 prefetch-instr = <1>;
0656 arm,shared-override;
0657 };
0658
0659 mmc: dwmmc0@ff808000 {
0660 #address-cells = <1>;
0661 #size-cells = <0>;
0662 compatible = "altr,socfpga-dw-mshc";
0663 reg = <0xff808000 0x1000>;
0664 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
0665 fifo-depth = <0x400>;
0666 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
0667 clock-names = "biu", "ciu";
0668 resets = <&rst SDMMC_RESET>;
0669 status = "disabled";
0670 };
0671
0672 nand: nand@ffb90000 {
0673 #address-cells = <1>;
0674 #size-cells = <0>;
0675 compatible = "altr,socfpga-denali-nand";
0676 reg = <0xffb90000 0x72000>,
0677 <0xffb80000 0x10000>;
0678 reg-names = "nand_data", "denali_reg";
0679 interrupts = <0 99 4>;
0680 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
0681 clock-names = "nand", "nand_x", "ecc";
0682 resets = <&rst NAND_RESET>;
0683 status = "disabled";
0684 };
0685
0686 ocram: sram@ffe00000 {
0687 compatible = "mmio-sram";
0688 reg = <0xffe00000 0x40000>;
0689 };
0690
0691 eccmgr: eccmgr {
0692 compatible = "altr,socfpga-a10-ecc-manager";
0693 altr,sysmgr-syscon = <&sysmgr>;
0694 #address-cells = <1>;
0695 #size-cells = <1>;
0696 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
0697 <0 0 IRQ_TYPE_LEVEL_HIGH>;
0698 interrupt-controller;
0699 #interrupt-cells = <2>;
0700 ranges;
0701
0702 sdramedac {
0703 compatible = "altr,sdram-edac-a10";
0704 altr,sdr-syscon = <&sdr>;
0705 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
0706 <49 IRQ_TYPE_LEVEL_HIGH>;
0707 };
0708
0709 l2-ecc@ffd06010 {
0710 compatible = "altr,socfpga-a10-l2-ecc";
0711 reg = <0xffd06010 0x4>;
0712 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
0713 <32 IRQ_TYPE_LEVEL_HIGH>;
0714 };
0715
0716 ocram-ecc@ff8c3000 {
0717 compatible = "altr,socfpga-a10-ocram-ecc";
0718 reg = <0xff8c3000 0x400>;
0719 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
0720 <33 IRQ_TYPE_LEVEL_HIGH>;
0721 };
0722
0723 emac0-rx-ecc@ff8c0800 {
0724 compatible = "altr,socfpga-eth-mac-ecc";
0725 reg = <0xff8c0800 0x400>;
0726 altr,ecc-parent = <&gmac0>;
0727 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
0728 <36 IRQ_TYPE_LEVEL_HIGH>;
0729 };
0730
0731 emac0-tx-ecc@ff8c0c00 {
0732 compatible = "altr,socfpga-eth-mac-ecc";
0733 reg = <0xff8c0c00 0x400>;
0734 altr,ecc-parent = <&gmac0>;
0735 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
0736 <37 IRQ_TYPE_LEVEL_HIGH>;
0737 };
0738
0739 sdmmca-ecc@ff8c2c00 {
0740 compatible = "altr,socfpga-sdmmc-ecc";
0741 reg = <0xff8c2c00 0x400>;
0742 altr,ecc-parent = <&mmc>;
0743 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
0744 <47 IRQ_TYPE_LEVEL_HIGH>,
0745 <16 IRQ_TYPE_LEVEL_HIGH>,
0746 <48 IRQ_TYPE_LEVEL_HIGH>;
0747 };
0748
0749 dma-ecc@ff8c8000 {
0750 compatible = "altr,socfpga-dma-ecc";
0751 reg = <0xff8c8000 0x400>;
0752 altr,ecc-parent = <&pdma>;
0753 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
0754 <42 IRQ_TYPE_LEVEL_HIGH>;
0755 };
0756
0757 usb0-ecc@ff8c8800 {
0758 compatible = "altr,socfpga-usb-ecc";
0759 reg = <0xff8c8800 0x400>;
0760 altr,ecc-parent = <&usb0>;
0761 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
0762 <34 IRQ_TYPE_LEVEL_HIGH>;
0763 };
0764 };
0765
0766 qspi: spi@ff809000 {
0767 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
0768 #address-cells = <1>;
0769 #size-cells = <0>;
0770 reg = <0xff809000 0x100>,
0771 <0xffa00000 0x100000>;
0772 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
0773 cdns,fifo-depth = <128>;
0774 cdns,fifo-width = <4>;
0775 cdns,trigger-address = <0x00000000>;
0776 clocks = <&qspi_clk>;
0777 resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
0778 reset-names = "qspi", "qspi-ocp";
0779 status = "disabled";
0780 };
0781
0782 rst: rstmgr@ffd05000 {
0783 #reset-cells = <1>;
0784 compatible = "altr,rst-mgr";
0785 reg = <0xffd05000 0x100>;
0786 altr,modrst-offset = <0x20>;
0787 };
0788
0789 scu: snoop-control-unit@ffffc000 {
0790 compatible = "arm,cortex-a9-scu";
0791 reg = <0xffffc000 0x100>;
0792 };
0793
0794 sysmgr: sysmgr@ffd06000 {
0795 compatible = "altr,sys-mgr", "syscon";
0796 reg = <0xffd06000 0x300>;
0797 cpu1-start-addr = <0xffd06230>;
0798 };
0799
0800 /* Local timer */
0801 timer@ffffc600 {
0802 compatible = "arm,cortex-a9-twd-timer";
0803 reg = <0xffffc600 0x100>;
0804 interrupts = <1 13 0xf01>;
0805 clocks = <&mpu_periph_clk>;
0806 };
0807
0808 timer0: timer0@ffc02700 {
0809 compatible = "snps,dw-apb-timer";
0810 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
0811 reg = <0xffc02700 0x100>;
0812 clocks = <&l4_sp_clk>;
0813 clock-names = "timer";
0814 resets = <&rst SPTIMER0_RESET>;
0815 reset-names = "timer";
0816 };
0817
0818 timer1: timer1@ffc02800 {
0819 compatible = "snps,dw-apb-timer";
0820 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
0821 reg = <0xffc02800 0x100>;
0822 clocks = <&l4_sp_clk>;
0823 clock-names = "timer";
0824 resets = <&rst SPTIMER1_RESET>;
0825 reset-names = "timer";
0826 };
0827
0828 timer2: timer2@ffd00000 {
0829 compatible = "snps,dw-apb-timer";
0830 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
0831 reg = <0xffd00000 0x100>;
0832 clocks = <&l4_sys_free_clk>;
0833 clock-names = "timer";
0834 resets = <&rst L4SYSTIMER0_RESET>;
0835 reset-names = "timer";
0836 };
0837
0838 timer3: timer3@ffd00100 {
0839 compatible = "snps,dw-apb-timer";
0840 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
0841 reg = <0xffd00100 0x100>;
0842 clocks = <&l4_sys_free_clk>;
0843 clock-names = "timer";
0844 resets = <&rst L4SYSTIMER1_RESET>;
0845 reset-names = "timer";
0846 };
0847
0848 uart0: serial0@ffc02000 {
0849 compatible = "snps,dw-apb-uart";
0850 reg = <0xffc02000 0x100>;
0851 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
0852 reg-shift = <2>;
0853 reg-io-width = <4>;
0854 clocks = <&l4_sp_clk>;
0855 resets = <&rst UART0_RESET>;
0856 status = "disabled";
0857 };
0858
0859 uart1: serial1@ffc02100 {
0860 compatible = "snps,dw-apb-uart";
0861 reg = <0xffc02100 0x100>;
0862 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
0863 reg-shift = <2>;
0864 reg-io-width = <4>;
0865 clocks = <&l4_sp_clk>;
0866 resets = <&rst UART1_RESET>;
0867 status = "disabled";
0868 };
0869
0870 usbphy0: usbphy {
0871 #phy-cells = <0>;
0872 compatible = "usb-nop-xceiv";
0873 status = "okay";
0874 };
0875
0876 usb0: usb@ffb00000 {
0877 compatible = "snps,dwc2";
0878 reg = <0xffb00000 0xffff>;
0879 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
0880 clocks = <&usb_clk>;
0881 clock-names = "otg";
0882 resets = <&rst USB0_RESET>;
0883 reset-names = "dwc2";
0884 phys = <&usbphy0>;
0885 phy-names = "usb2-phy";
0886 status = "disabled";
0887 };
0888
0889 usb1: usb@ffb40000 {
0890 compatible = "snps,dwc2";
0891 reg = <0xffb40000 0xffff>;
0892 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
0893 clocks = <&usb_clk>;
0894 clock-names = "otg";
0895 resets = <&rst USB1_RESET>;
0896 reset-names = "dwc2";
0897 phys = <&usbphy0>;
0898 phy-names = "usb2-phy";
0899 status = "disabled";
0900 };
0901
0902 watchdog0: watchdog@ffd00200 {
0903 compatible = "snps,dw-wdt";
0904 reg = <0xffd00200 0x100>;
0905 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
0906 clocks = <&l4_sys_free_clk>;
0907 resets = <&rst L4WD0_RESET>;
0908 status = "disabled";
0909 };
0910
0911 watchdog1: watchdog@ffd00300 {
0912 compatible = "snps,dw-wdt";
0913 reg = <0xffd00300 0x100>;
0914 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
0915 clocks = <&l4_sys_free_clk>;
0916 resets = <&rst L4WD1_RESET>;
0917 status = "disabled";
0918 };
0919 };
0920 };
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