0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Google Veyron Jaq Rev 1+ board device tree source
0004 *
0005 * Copyright 2015 Google, Inc
0006 */
0007
0008 /dts-v1/;
0009
0010 #include "rk3288-veyron-chromebook.dtsi"
0011 #include "cros-ec-sbs.dtsi"
0012
0013 / {
0014 model = "Google Jaq";
0015 compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
0016 "google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
0017 "google,veyron-jaq-rev1", "google,veyron-jaq",
0018 "google,veyron", "rockchip,rk3288";
0019 };
0020
0021 &backlight {
0022 /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */
0023 brightness-levels = <8 255>;
0024 num-interpolated-steps = <247>;
0025 };
0026
0027 &rk808 {
0028 pinctrl-names = "default";
0029 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
0030 dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
0031 <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
0032
0033 regulators {
0034 mic_vcc: LDO_REG2 {
0035 regulator-name = "mic_vcc";
0036 regulator-always-on;
0037 regulator-boot-on;
0038 regulator-min-microvolt = <1800000>;
0039 regulator-max-microvolt = <1800000>;
0040 regulator-state-mem {
0041 regulator-off-in-suspend;
0042 };
0043 };
0044 };
0045 };
0046
0047 &sdio0 {
0048 #address-cells = <1>;
0049 #size-cells = <0>;
0050
0051 btmrvl: btmrvl@2 {
0052 compatible = "marvell,sd8897-bt";
0053 reg = <2>;
0054 interrupt-parent = <&gpio4>;
0055 interrupts = <RK_PD7 IRQ_TYPE_LEVEL_LOW>;
0056 marvell,wakeup-pin = /bits/ 16 <13>;
0057 pinctrl-names = "default";
0058 pinctrl-0 = <&bt_host_wake_l>;
0059 };
0060 };
0061
0062 &sdmmc {
0063 disable-wp;
0064 pinctrl-names = "default";
0065 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
0066 &sdmmc_bus4>;
0067 };
0068
0069 &vcc_5v {
0070 enable-active-high;
0071 gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
0072 pinctrl-names = "default";
0073 pinctrl-0 = <&drv_5v>;
0074 };
0075
0076 &vcc50_hdmi {
0077 enable-active-high;
0078 gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
0079 pinctrl-names = "default";
0080 pinctrl-0 = <&vcc50_hdmi_en>;
0081 };
0082
0083 &gpio0 {
0084 gpio-line-names = "PMIC_SLEEP_AP",
0085 "DDRIO_PWROFF",
0086 "DDRIO_RETEN",
0087 "TS3A227E_INT_L",
0088 "PMIC_INT_L",
0089 "PWR_KEY_L",
0090 "AP_LID_INT_L",
0091 "EC_IN_RW",
0092
0093 "AC_PRESENT_AP",
0094 /*
0095 * RECOVERY_SW_L is Chrome OS ABI. Schematics call
0096 * it REC_MODE_L.
0097 */
0098 "RECOVERY_SW_L",
0099 "OTP_OUT",
0100 "HOST1_PWR_EN",
0101 "USBOTG_PWREN_H",
0102 "AP_WARM_RESET_H",
0103 "nFALUT2",
0104 "I2C0_SDA_PMIC",
0105
0106 "I2C0_SCL_PMIC",
0107 "SUSPEND_L",
0108 "USB_INT";
0109 };
0110
0111 &gpio2 {
0112 gpio-line-names = "CONFIG0",
0113 "CONFIG1",
0114 "CONFIG2",
0115 "",
0116 "",
0117 "",
0118 "",
0119 "CONFIG3",
0120
0121 "",
0122 "EMMC_RST_L",
0123 "",
0124 "",
0125 "BL_PWR_EN",
0126 "AVDD_1V8_DISP_EN";
0127 };
0128
0129 &gpio3 {
0130 gpio-line-names = "FLASH0_D0",
0131 "FLASH0_D1",
0132 "FLASH0_D2",
0133 "FLASH0_D3",
0134 "FLASH0_D4",
0135 "FLASH0_D5",
0136 "FLASH0_D6",
0137 "FLASH0_D7",
0138
0139 "",
0140 "",
0141 "",
0142 "",
0143 "",
0144 "",
0145 "",
0146 "",
0147
0148 "FLASH0_CS2/EMMC_CMD",
0149 "",
0150 "FLASH0_DQS/EMMC_CLKO";
0151 };
0152
0153 &gpio4 {
0154 gpio-line-names = "",
0155 "",
0156 "",
0157 "",
0158 "",
0159 "",
0160 "",
0161 "",
0162
0163 "",
0164 "",
0165 "",
0166 "",
0167 "",
0168 "",
0169 "",
0170 "",
0171
0172 "UART0_RXD",
0173 "UART0_TXD",
0174 "UART0_CTS",
0175 "UART0_RTS",
0176 "SDIO0_D0",
0177 "SDIO0_D1",
0178 "SDIO0_D2",
0179 "SDIO0_D3",
0180
0181 "SDIO0_CMD",
0182 "SDIO0_CLK",
0183 "BT_DEV_WAKE", /* Maybe missing from mighty? */
0184 "",
0185 "WIFI_ENABLE_H",
0186 "BT_ENABLE_L",
0187 "WIFI_HOST_WAKE",
0188 "BT_HOST_WAKE";
0189 };
0190
0191 &gpio5 {
0192 gpio-line-names = "",
0193 "",
0194 "",
0195 "",
0196 "",
0197 "",
0198 "",
0199 "",
0200
0201 "",
0202 "",
0203 "",
0204 "",
0205 "SPI0_CLK",
0206 "SPI0_CS0",
0207 "SPI0_TXD",
0208 "SPI0_RXD",
0209
0210 "",
0211 "",
0212 "",
0213 "VCC50_HDMI_EN";
0214 };
0215
0216 &gpio6 {
0217 gpio-line-names = "I2S0_SCLK",
0218 "I2S0_LRCK_RX",
0219 "I2S0_LRCK_TX",
0220 "I2S0_SDI",
0221 "I2S0_SDO0",
0222 "HP_DET_H",
0223 "ALS_INT",
0224 "INT_CODEC",
0225
0226 "I2S0_CLK",
0227 "I2C2_SDA",
0228 "I2C2_SCL",
0229 "MICDET",
0230 "",
0231 "",
0232 "",
0233 "",
0234
0235 "SDMMC_D0",
0236 "SDMMC_D1",
0237 "SDMMC_D2",
0238 "SDMMC_D3",
0239 "SDMMC_CLK",
0240 "SDMMC_CMD";
0241 };
0242
0243 &gpio7 {
0244 gpio-line-names = "LCDC_BL",
0245 "PWM_LOG",
0246 "BL_EN",
0247 "TRACKPAD_INT",
0248 "TPM_INT_H",
0249 "SDMMC_DET_L",
0250 /*
0251 * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
0252 * it FW_WP_AP.
0253 */
0254 "AP_FLASH_WP_L",
0255 "EC_INT",
0256
0257 "CPU_NMI",
0258 "DVSOK",
0259 "SDMMC_WP", /* mighty only */
0260 "EDP_HPD",
0261 "DVS1",
0262 "nFALUT1", /* nFAULT1 on jaq */
0263 "LCD_EN",
0264 "DVS2",
0265
0266 "VCC5V_GOOD_H",
0267 "I2C4_SDA_TP",
0268 "I2C4_SCL_TP",
0269 "I2C5_SDA_HDMI",
0270 "I2C5_SCL_HDMI",
0271 "5V_DRV",
0272 "UART2_RXD",
0273 "UART2_TXD";
0274 };
0275
0276 &gpio8 {
0277 gpio-line-names = "RAM_ID0",
0278 "RAM_ID1",
0279 "RAM_ID2",
0280 "RAM_ID3",
0281 "I2C1_SDA_TPM",
0282 "I2C1_SCL_TPM",
0283 "SPI2_CLK",
0284 "SPI2_CS0",
0285
0286 "SPI2_RXD",
0287 "SPI2_TXD";
0288 };
0289
0290 &pinctrl {
0291 pinctrl-names = "default", "sleep";
0292 pinctrl-0 = <
0293 /* Common for sleep and wake, but no owners */
0294 &ddr0_retention
0295 &ddrio_pwroff
0296 &global_pwroff
0297
0298 /* Wake only */
0299 &suspend_l_wake
0300 &bt_dev_wake_awake
0301 >;
0302 pinctrl-1 = <
0303 /* Common for sleep and wake, but no owners */
0304 &ddr0_retention
0305 &ddrio_pwroff
0306 &global_pwroff
0307
0308 /* Sleep only */
0309 &suspend_l_sleep
0310 &bt_dev_wake_sleep
0311 >;
0312
0313 buck-5v {
0314 drv_5v: drv-5v {
0315 rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
0316 };
0317 };
0318
0319 hdmi {
0320 vcc50_hdmi_en: vcc50-hdmi-en {
0321 rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
0322 };
0323 };
0324
0325 pmic {
0326 dvs_1: dvs-1 {
0327 rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
0328 };
0329
0330 dvs_2: dvs-2 {
0331 rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
0332 };
0333 };
0334 };
