0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Google Veyron Fievel Rev 0+ board device tree source
0004 *
0005 * Copyright 2016 Google, Inc
0006 */
0007
0008 /dts-v1/;
0009 #include "rk3288-veyron.dtsi"
0010 #include "rk3288-veyron-analog-audio.dtsi"
0011
0012 / {
0013 model = "Google Fievel";
0014 compatible = "google,veyron-fievel-rev8", "google,veyron-fievel-rev7",
0015 "google,veyron-fievel-rev6", "google,veyron-fievel-rev5",
0016 "google,veyron-fievel-rev4", "google,veyron-fievel-rev3",
0017 "google,veyron-fievel-rev2", "google,veyron-fievel-rev1",
0018 "google,veyron-fievel-rev0", "google,veyron-fievel",
0019 "google,veyron", "rockchip,rk3288";
0020
0021 vccsys: vccsys {
0022 compatible = "regulator-fixed";
0023 regulator-name = "vccsys";
0024 regulator-boot-on;
0025 regulator-always-on;
0026 };
0027
0028 /*
0029 * vcc33_pmuio and vcc33_io is sourced directly from vcc33_sys,
0030 * enabled by vcc_18
0031 */
0032 vcc33_io: vcc33-io {
0033 compatible = "regulator-fixed";
0034 regulator-always-on;
0035 regulator-boot-on;
0036 regulator-name = "vcc33_io";
0037 };
0038
0039 vcc5_host1: vcc5-host1-regulator {
0040 compatible = "regulator-fixed";
0041 enable-active-high;
0042 gpio = <&gpio5 RK_PC2 GPIO_ACTIVE_HIGH>;
0043 pinctrl-names = "default";
0044 pinctrl-0 = <&hub_usb1_pwr_en>;
0045 regulator-name = "vcc5_host1";
0046 regulator-always-on;
0047 regulator-boot-on;
0048 };
0049
0050 vcc5_host2: vcc5-host2-regulator {
0051 compatible = "regulator-fixed";
0052 enable-active-high;
0053 gpio = <&gpio5 RK_PB6 GPIO_ACTIVE_HIGH>;
0054 pinctrl-names = "default";
0055 pinctrl-0 = <&hub_usb2_pwr_en>;
0056 regulator-name = "vcc5_host2";
0057 regulator-always-on;
0058 regulator-boot-on;
0059 };
0060
0061 vcc5v_otg: vcc5v-otg-regulator {
0062 compatible = "regulator-fixed";
0063 enable-active-high;
0064 gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
0065 pinctrl-names = "default";
0066 pinctrl-0 = <&usb_otg_pwr_en>;
0067 regulator-name = "vcc5_otg";
0068 regulator-always-on;
0069 regulator-boot-on;
0070 };
0071
0072 ext_gmac: external-gmac-clock {
0073 compatible = "fixed-clock";
0074 #clock-cells = <0>;
0075 clock-frequency = <125000000>;
0076 clock-output-names = "ext_gmac";
0077 };
0078 };
0079
0080 &gmac {
0081 status = "okay";
0082
0083 assigned-clocks = <&cru SCLK_MAC>;
0084 assigned-clock-parents = <&ext_gmac>;
0085 clock_in_out = "input";
0086 phy-handle = <ðphy>;
0087 phy-mode = "rgmii";
0088 phy-supply = <&vcc33_lan>;
0089 pinctrl-names = "default";
0090 pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
0091 rx_delay = <0x10>;
0092 tx_delay = <0x30>;
0093
0094 /*
0095 * Reset for the RTL8211 PHY which requires a 10-ms reset pulse (low)
0096 * with a 30ms settling time.
0097 */
0098 snps,reset-gpio = <&gpio4 RK_PB0 0>;
0099 snps,reset-active-low;
0100 snps,reset-delays-us = <0 10000 30000>;
0101 wakeup-source;
0102
0103 mdio0 {
0104 compatible = "snps,dwmac-mdio";
0105 #address-cells = <1>;
0106 #size-cells = <0>;
0107
0108 ethphy: ethernet-phy@1 {
0109 reg = <1>;
0110 };
0111 };
0112 };
0113
0114 &rk808 {
0115 dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
0116 <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
0117 pinctrl-names = "default";
0118 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
0119
0120 vcc6-supply = <&vcc33_sys>;
0121 vcc10-supply = <&vcc33_sys>;
0122 vcc11-supply = <&vcc_5v>;
0123 vcc12-supply = <&vcc33_sys>;
0124
0125 regulators {
0126 /delete-node/ LDO_REG1;
0127
0128 /*
0129 * According to the schematic, vcc18_lcdt is for
0130 * HDMI_AVDD_1V8
0131 */
0132 vcc18_lcdt: LDO_REG2 {
0133 regulator-always-on;
0134 regulator-boot-on;
0135 regulator-min-microvolt = <1800000>;
0136 regulator-max-microvolt = <1800000>;
0137 regulator-name = "vdd18_lcdt";
0138 regulator-state-mem {
0139 regulator-off-in-suspend;
0140 };
0141 };
0142
0143 /*
0144 * This is not a pwren anymore, but the real power supply,
0145 * vdd10_lcd for HDMI_AVDD_1V0
0146 */
0147 vdd10_lcd: LDO_REG7 {
0148 regulator-always-on;
0149 regulator-boot-on;
0150 regulator-min-microvolt = <1000000>;
0151 regulator-max-microvolt = <1000000>;
0152 regulator-name = "vdd10_lcd";
0153 regulator-state-mem {
0154 regulator-off-in-suspend;
0155 };
0156 };
0157
0158 /* for usb camera */
0159 vcc33_ccd: LDO_REG8 {
0160 regulator-always-on;
0161 regulator-boot-on;
0162 regulator-min-microvolt = <3300000>;
0163 regulator-max-microvolt = <3300000>;
0164 regulator-name = "vcc33_ccd";
0165 regulator-state-mem {
0166 regulator-off-in-suspend;
0167 };
0168 };
0169
0170 vcc33_lan: SWITCH_REG2 {
0171 regulator-name = "vcc33_lan";
0172 };
0173 };
0174 };
0175
0176 &sdio0 {
0177 #address-cells = <1>;
0178 #size-cells = <0>;
0179
0180 btmrvl: btmrvl@2 {
0181 compatible = "marvell,sd8897-bt";
0182 reg = <2>;
0183 interrupt-parent = <&gpio4>;
0184 interrupts = <RK_PD7 IRQ_TYPE_LEVEL_LOW>;
0185 marvell,wakeup-pin = /bits/ 16 <13>;
0186 pinctrl-names = "default";
0187 pinctrl-0 = <&bt_host_wake_l>;
0188 };
0189 };
0190
0191 &vcc50_hdmi {
0192 enable-active-high;
0193 gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
0194 pinctrl-names = "default";
0195 pinctrl-0 = <&vcc50_hdmi_en>;
0196 };
0197
0198 &vcc_5v {
0199 enable-active-high;
0200 gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
0201 pinctrl-names = "default";
0202 pinctrl-0 = <&drv_5v>;
0203 };
0204
0205 &gpio0 {
0206 gpio-line-names = "PMIC_SLEEP_AP",
0207 "DDRIO_PWROFF",
0208 "DDRIO_RETEN",
0209 "TS3A227E_INT_L",
0210 "PMIC_INT_L",
0211 "PWR_KEY_L",
0212 "HUB_USB1_nFALUT",
0213 "PHY_PMEB",
0214
0215 "PHY_INT",
0216 /*
0217 * RECOVERY_SW_L is Chrome OS ABI. Schematics call
0218 * it REC_MODE_L.
0219 */
0220 "RECOVERY_SW_L",
0221 "OTP_OUT",
0222 "",
0223 "USB_OTG_POWER_EN",
0224 "AP_WARM_RESET_H",
0225 "USB_OTG_nFALUT",
0226 "I2C0_SDA_PMIC",
0227
0228 "I2C0_SCL_PMIC",
0229 "DEVMODE_L",
0230 "USB_INT";
0231 };
0232
0233 &gpio2 {
0234 gpio-line-names = "CONFIG0",
0235 "CONFIG1",
0236 "CONFIG2",
0237 "",
0238 "",
0239 "",
0240 "",
0241 "CONFIG3",
0242
0243 "",
0244 "EMMC_RST_L",
0245 "",
0246 "",
0247 "BL_PWR_EN",
0248 "",
0249 "TOUCH_INT",
0250 "TOUCH_RST",
0251
0252 "I2C3_SCL_TP",
0253 "I2C3_SDA_TP";
0254 };
0255
0256 &gpio3 {
0257 gpio-line-names = "FLASH0_D0",
0258 "FLASH0_D1",
0259 "FLASH0_D2",
0260 "FLASH0_D3",
0261 "FLASH0_D4",
0262 "FLASH0_D5",
0263 "FLASH0_D6",
0264 "FLASH0_D7",
0265
0266 "VCC5V_GOOD_H",
0267 "",
0268 "",
0269 "",
0270 "",
0271 "",
0272 "",
0273 "",
0274
0275 "FLASH0_CS2/EMMC_CMD",
0276 "",
0277 "FLASH0_DQS/EMMC_CLKO",
0278 "",
0279 "",
0280 "",
0281 "",
0282 "",
0283
0284 "PHY_TXD2",
0285 "PHY_TXD3",
0286 "MAC_RXD2",
0287 "MAC_RXD3",
0288 "PHY_TXD0",
0289 "PHY_TXD1",
0290 "MAC_RXD0",
0291 "MAC_RXD1";
0292 };
0293
0294 &gpio4 {
0295 gpio-line-names = "MAC_MDC",
0296 "MAC_RXDV",
0297 "MAC_RXER",
0298 "MAC_CLK",
0299 "PHY_TXEN",
0300 "MAC_MDIO",
0301 "MAC_RXCLK",
0302 "",
0303
0304 "PHY_RST",
0305 "PHY_TXCLK",
0306 "",
0307 "",
0308 "",
0309 "",
0310 "",
0311 "",
0312
0313 "UART0_RXD",
0314 "UART0_TXD",
0315 "UART0_CTS_L",
0316 "UART0_RTS_L",
0317 "SDIO0_D0",
0318 "SDIO0_D1",
0319 "SDIO0_D2",
0320 "SDIO0_D3",
0321
0322 "SDIO0_CMD",
0323 "SDIO0_CLK",
0324 "BT_DEV_WAKE",
0325 "",
0326 "WIFI_ENABLE_H",
0327 "BT_ENABLE_L",
0328 "WIFI_HOST_WAKE",
0329 "BT_HOST_WAKE";
0330 };
0331
0332 &gpio5 {
0333 gpio-line-names = "",
0334 "",
0335 "",
0336 "",
0337 "",
0338 "",
0339 "",
0340 "",
0341
0342 "",
0343 "",
0344 "",
0345 "",
0346 "USB_OTG_CTL1",
0347 "HUB_USB2_CTL1",
0348 "HUB_USB2_PWR_EN",
0349 "HUB_USB_ILIM_SEL",
0350
0351 "USB_OTG_STATUS_L",
0352 "HUB_USB1_CTL1",
0353 "HUB_USB1_PWR_EN",
0354 "VCC50_HDMI_EN";
0355 };
0356
0357 &gpio6 {
0358 gpio-line-names = "I2S0_SCLK",
0359 "I2S0_LRCK_RX",
0360 "I2S0_LRCK_TX",
0361 "I2S0_SDI",
0362 "I2S0_SDO0",
0363 "HP_DET_H",
0364 "",
0365 "INT_CODEC",
0366
0367 "I2S0_CLK",
0368 "I2C2_SDA",
0369 "I2C2_SCL",
0370 "MICDET",
0371 "",
0372 "",
0373 "",
0374 "",
0375
0376 "HUB_USB2_nFALUT",
0377 "USB_OTG_ILIM_SEL";
0378 };
0379
0380 &gpio7 {
0381 gpio-line-names = "LCD_BL_PWM",
0382 "PWM_LOG",
0383 "BL_EN",
0384 "PWR_LED1",
0385 "TPM_INT_H",
0386 "SPK_ON",
0387 /*
0388 * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
0389 * it FW_WP_AP.
0390 */
0391 "AP_FLASH_WP_L",
0392 "",
0393
0394 "CPU_NMI",
0395 "DVSOK",
0396 "",
0397 "EDP_HPD",
0398 "DVS1",
0399 "",
0400 "LCD_EN",
0401 "DVS2",
0402
0403 "HDMI_CEC",
0404 "I2C4_SDA",
0405 "I2C4_SCL",
0406 "I2C5_SDA_HDMI",
0407 "I2C5_SCL_HDMI",
0408 "5V_DRV",
0409 "UART2_RXD",
0410 "UART2_TXD";
0411 };
0412
0413 &gpio8 {
0414 gpio-line-names = "RAM_ID0",
0415 "RAM_ID1",
0416 "RAM_ID2",
0417 "RAM_ID3",
0418 "I2C1_SDA_TPM",
0419 "I2C1_SCL_TPM",
0420 "SPI2_CLK",
0421 "SPI2_CS0",
0422
0423 "SPI2_RXD",
0424 "SPI2_TXD";
0425 };
0426
0427 &pinctrl {
0428 pinctrl-names = "default", "sleep";
0429 pinctrl-0 = <
0430 /* Common for sleep and wake, but no owners */
0431 &ddr0_retention
0432 &ddrio_pwroff
0433 &global_pwroff
0434
0435 /* For usb bc1.2 */
0436 &usb_otg_ilim_sel
0437 &usb_usb_ilim_sel
0438
0439 /* Wake only */
0440 &bt_dev_wake_awake
0441 &pwr_led1_on
0442 >;
0443
0444 pinctrl-1 = <
0445 /* Common for sleep and wake, but no owners */
0446 &ddr0_retention
0447 &ddrio_pwroff
0448 &global_pwroff
0449
0450 /* For usb bc1.2 */
0451 &usb_otg_ilim_sel
0452 &usb_usb_ilim_sel
0453
0454 /* Sleep only */
0455 &bt_dev_wake_sleep
0456 &pwr_led1_blink
0457 >;
0458
0459 buck-5v {
0460 drv_5v: drv-5v {
0461 rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
0462 };
0463 };
0464
0465 gmac {
0466 phy_rst: phy-rst {
0467 rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
0468 };
0469
0470 phy_pmeb: phy-pmeb {
0471 rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
0472 };
0473
0474 phy_int: phy-int {
0475 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
0476 };
0477 };
0478
0479 hdmi {
0480 vcc50_hdmi_en: vcc50-hdmi-en {
0481 rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
0482 };
0483 };
0484
0485 leds {
0486 pwr_led1_on: pwr-led1-on {
0487 rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_low>;
0488 };
0489
0490 pwr_led1_blink: pwr-led1-blink {
0491 rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>;
0492 };
0493 };
0494
0495 pmic {
0496 dvs_1: dvs-1 {
0497 rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
0498 };
0499
0500 dvs_2: dvs-2 {
0501 rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
0502 };
0503 };
0504
0505 usb-bc12 {
0506 usb_otg_ilim_sel: usb-otg-ilim-sel {
0507 rockchip,pins = <6 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>;
0508 };
0509
0510 usb_usb_ilim_sel: usb-usb-ilim-sel {
0511 rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>;
0512 };
0513 };
0514
0515 usb-host {
0516 hub_usb1_pwr_en: hub_usb1_pwr_en {
0517 rockchip,pins = <5 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
0518 };
0519
0520 hub_usb2_pwr_en: hub_usb2_pwr_en {
0521 rockchip,pins = <5 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
0522 };
0523
0524 usb_otg_pwr_en: usb_otg_pwr_en {
0525 rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
0526 };
0527 };
0528 };
