0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2013 MundoReader S.L.
0004 * Author: Heiko Stuebner <heiko@sntech.de>
0005 */
0006
0007 #include <dt-bindings/gpio/gpio.h>
0008 #include <dt-bindings/pinctrl/rockchip.h>
0009 #include <dt-bindings/clock/rk3188-cru.h>
0010 #include <dt-bindings/power/rk3188-power.h>
0011 #include "rk3xxx.dtsi"
0012
0013 / {
0014 compatible = "rockchip,rk3188";
0015
0016 cpus {
0017 #address-cells = <1>;
0018 #size-cells = <0>;
0019 enable-method = "rockchip,rk3066-smp";
0020
0021 cpu0: cpu@0 {
0022 device_type = "cpu";
0023 compatible = "arm,cortex-a9";
0024 next-level-cache = <&L2>;
0025 reg = <0x0>;
0026 clock-latency = <40000>;
0027 clocks = <&cru ARMCLK>;
0028 operating-points-v2 = <&cpu0_opp_table>;
0029 resets = <&cru SRST_CORE0>;
0030 };
0031 cpu1: cpu@1 {
0032 device_type = "cpu";
0033 compatible = "arm,cortex-a9";
0034 next-level-cache = <&L2>;
0035 reg = <0x1>;
0036 operating-points-v2 = <&cpu0_opp_table>;
0037 resets = <&cru SRST_CORE1>;
0038 };
0039 cpu2: cpu@2 {
0040 device_type = "cpu";
0041 compatible = "arm,cortex-a9";
0042 next-level-cache = <&L2>;
0043 reg = <0x2>;
0044 operating-points-v2 = <&cpu0_opp_table>;
0045 resets = <&cru SRST_CORE2>;
0046 };
0047 cpu3: cpu@3 {
0048 device_type = "cpu";
0049 compatible = "arm,cortex-a9";
0050 next-level-cache = <&L2>;
0051 reg = <0x3>;
0052 operating-points-v2 = <&cpu0_opp_table>;
0053 resets = <&cru SRST_CORE3>;
0054 };
0055 };
0056
0057 cpu0_opp_table: opp-table-0 {
0058 compatible = "operating-points-v2";
0059 opp-shared;
0060
0061 opp-312000000 {
0062 opp-hz = /bits/ 64 <312000000>;
0063 opp-microvolt = <875000>;
0064 clock-latency-ns = <40000>;
0065 };
0066 opp-504000000 {
0067 opp-hz = /bits/ 64 <504000000>;
0068 opp-microvolt = <925000>;
0069 };
0070 opp-600000000 {
0071 opp-hz = /bits/ 64 <600000000>;
0072 opp-microvolt = <950000>;
0073 opp-suspend;
0074 };
0075 opp-816000000 {
0076 opp-hz = /bits/ 64 <816000000>;
0077 opp-microvolt = <975000>;
0078 };
0079 opp-1008000000 {
0080 opp-hz = /bits/ 64 <1008000000>;
0081 opp-microvolt = <1075000>;
0082 };
0083 opp-1200000000 {
0084 opp-hz = /bits/ 64 <1200000000>;
0085 opp-microvolt = <1150000>;
0086 };
0087 opp-1416000000 {
0088 opp-hz = /bits/ 64 <1416000000>;
0089 opp-microvolt = <1250000>;
0090 };
0091 opp-1608000000 {
0092 opp-hz = /bits/ 64 <1608000000>;
0093 opp-microvolt = <1350000>;
0094 };
0095 };
0096
0097 display-subsystem {
0098 compatible = "rockchip,display-subsystem";
0099 ports = <&vop0_out>, <&vop1_out>;
0100 };
0101
0102 sram: sram@10080000 {
0103 compatible = "mmio-sram";
0104 reg = <0x10080000 0x8000>;
0105 #address-cells = <1>;
0106 #size-cells = <1>;
0107 ranges = <0 0x10080000 0x8000>;
0108
0109 smp-sram@0 {
0110 compatible = "rockchip,rk3066-smp-sram";
0111 reg = <0x0 0x50>;
0112 };
0113 };
0114
0115 vop0: vop@1010c000 {
0116 compatible = "rockchip,rk3188-vop";
0117 reg = <0x1010c000 0x1000>;
0118 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0119 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
0120 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
0121 power-domains = <&power RK3188_PD_VIO>;
0122 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
0123 reset-names = "axi", "ahb", "dclk";
0124 status = "disabled";
0125
0126 vop0_out: port {
0127 #address-cells = <1>;
0128 #size-cells = <0>;
0129 };
0130 };
0131
0132 vop1: vop@1010e000 {
0133 compatible = "rockchip,rk3188-vop";
0134 reg = <0x1010e000 0x1000>;
0135 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0136 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
0137 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
0138 power-domains = <&power RK3188_PD_VIO>;
0139 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
0140 reset-names = "axi", "ahb", "dclk";
0141 status = "disabled";
0142
0143 vop1_out: port {
0144 #address-cells = <1>;
0145 #size-cells = <0>;
0146 };
0147 };
0148
0149 timer3: timer@2000e000 {
0150 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
0151 reg = <0x2000e000 0x20>;
0152 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0153 clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>;
0154 clock-names = "pclk", "timer";
0155 };
0156
0157 timer6: timer@200380a0 {
0158 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
0159 reg = <0x200380a0 0x20>;
0160 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
0161 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>;
0162 clock-names = "pclk", "timer";
0163 };
0164
0165 i2s0: i2s@1011a000 {
0166 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
0167 reg = <0x1011a000 0x2000>;
0168 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0169 pinctrl-names = "default";
0170 pinctrl-0 = <&i2s0_bus>;
0171 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
0172 clock-names = "i2s_clk", "i2s_hclk";
0173 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
0174 dma-names = "tx", "rx";
0175 rockchip,playback-channels = <2>;
0176 rockchip,capture-channels = <2>;
0177 #sound-dai-cells = <0>;
0178 status = "disabled";
0179 };
0180
0181 spdif: sound@1011e000 {
0182 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
0183 reg = <0x1011e000 0x2000>;
0184 #sound-dai-cells = <0>;
0185 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
0186 clock-names = "mclk", "hclk";
0187 dmas = <&dmac1_s 8>;
0188 dma-names = "tx";
0189 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0190 pinctrl-names = "default";
0191 pinctrl-0 = <&spdif_tx>;
0192 status = "disabled";
0193 };
0194
0195 cru: clock-controller@20000000 {
0196 compatible = "rockchip,rk3188-cru";
0197 reg = <0x20000000 0x1000>;
0198 clocks = <&xin24m>;
0199 clock-names = "xin24m";
0200 rockchip,grf = <&grf>;
0201 #clock-cells = <1>;
0202 #reset-cells = <1>;
0203 };
0204
0205 efuse: efuse@20010000 {
0206 compatible = "rockchip,rk3188-efuse";
0207 reg = <0x20010000 0x4000>;
0208 #address-cells = <1>;
0209 #size-cells = <1>;
0210 clocks = <&cru PCLK_EFUSE>;
0211 clock-names = "pclk_efuse";
0212
0213 cpu_leakage: cpu_leakage@17 {
0214 reg = <0x17 0x1>;
0215 };
0216 };
0217
0218 pinctrl: pinctrl {
0219 compatible = "rockchip,rk3188-pinctrl";
0220 rockchip,grf = <&grf>;
0221 rockchip,pmu = <&pmu>;
0222
0223 #address-cells = <1>;
0224 #size-cells = <1>;
0225 ranges;
0226
0227 gpio0: gpio@2000a000 {
0228 compatible = "rockchip,rk3188-gpio-bank0";
0229 reg = <0x2000a000 0x100>;
0230 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
0231 clocks = <&cru PCLK_GPIO0>;
0232
0233 gpio-controller;
0234 #gpio-cells = <2>;
0235
0236 interrupt-controller;
0237 #interrupt-cells = <2>;
0238 };
0239
0240 gpio1: gpio@2003c000 {
0241 compatible = "rockchip,gpio-bank";
0242 reg = <0x2003c000 0x100>;
0243 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0244 clocks = <&cru PCLK_GPIO1>;
0245
0246 gpio-controller;
0247 #gpio-cells = <2>;
0248
0249 interrupt-controller;
0250 #interrupt-cells = <2>;
0251 };
0252
0253 gpio2: gpio@2003e000 {
0254 compatible = "rockchip,gpio-bank";
0255 reg = <0x2003e000 0x100>;
0256 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0257 clocks = <&cru PCLK_GPIO2>;
0258
0259 gpio-controller;
0260 #gpio-cells = <2>;
0261
0262 interrupt-controller;
0263 #interrupt-cells = <2>;
0264 };
0265
0266 gpio3: gpio@20080000 {
0267 compatible = "rockchip,gpio-bank";
0268 reg = <0x20080000 0x100>;
0269 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0270 clocks = <&cru PCLK_GPIO3>;
0271
0272 gpio-controller;
0273 #gpio-cells = <2>;
0274
0275 interrupt-controller;
0276 #interrupt-cells = <2>;
0277 };
0278
0279 pcfg_pull_up: pcfg-pull-up {
0280 bias-pull-up;
0281 };
0282
0283 pcfg_pull_down: pcfg-pull-down {
0284 bias-pull-down;
0285 };
0286
0287 pcfg_pull_none: pcfg-pull-none {
0288 bias-disable;
0289 };
0290
0291 emmc {
0292 emmc_clk: emmc-clk {
0293 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
0294 };
0295
0296 emmc_cmd: emmc-cmd {
0297 rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>;
0298 };
0299
0300 emmc_rst: emmc-rst {
0301 rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>;
0302 };
0303
0304 /*
0305 * The data pins are shared between nandc and emmc and
0306 * not accessible through pinctrl. Also they should've
0307 * been already set correctly by firmware, as
0308 * flash/emmc is the boot-device.
0309 */
0310 };
0311
0312 emac {
0313 emac_xfer: emac-xfer {
0314 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */
0315 <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */
0316 <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */
0317 <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */
0318 <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */
0319 <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */
0320 <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */
0321 <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */
0322 };
0323
0324 emac_mdio: emac-mdio {
0325 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
0326 <3 RK_PD1 2 &pcfg_pull_none>;
0327 };
0328 };
0329
0330 i2c0 {
0331 i2c0_xfer: i2c0-xfer {
0332 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
0333 <1 RK_PD1 1 &pcfg_pull_none>;
0334 };
0335 };
0336
0337 i2c1 {
0338 i2c1_xfer: i2c1-xfer {
0339 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>,
0340 <1 RK_PD3 1 &pcfg_pull_none>;
0341 };
0342 };
0343
0344 i2c2 {
0345 i2c2_xfer: i2c2-xfer {
0346 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>,
0347 <1 RK_PD5 1 &pcfg_pull_none>;
0348 };
0349 };
0350
0351 i2c3 {
0352 i2c3_xfer: i2c3-xfer {
0353 rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>,
0354 <3 RK_PB7 2 &pcfg_pull_none>;
0355 };
0356 };
0357
0358 i2c4 {
0359 i2c4_xfer: i2c4-xfer {
0360 rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>,
0361 <1 RK_PD7 1 &pcfg_pull_none>;
0362 };
0363 };
0364
0365 lcdc1 {
0366 lcdc1_dclk: lcdc1-dclk {
0367 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>;
0368 };
0369
0370 lcdc1_den: lcdc1-den {
0371 rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>;
0372 };
0373
0374 lcdc1_hsync: lcdc1-hsync {
0375 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
0376 };
0377
0378 lcdc1_vsync: lcdc1-vsync {
0379 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
0380 };
0381
0382 lcdc1_rgb24: ldcd1-rgb24 {
0383 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
0384 <2 RK_PA1 1 &pcfg_pull_none>,
0385 <2 RK_PA2 1 &pcfg_pull_none>,
0386 <2 RK_PA3 1 &pcfg_pull_none>,
0387 <2 RK_PA4 1 &pcfg_pull_none>,
0388 <2 RK_PA5 1 &pcfg_pull_none>,
0389 <2 RK_PA6 1 &pcfg_pull_none>,
0390 <2 RK_PA7 1 &pcfg_pull_none>,
0391 <2 RK_PB0 1 &pcfg_pull_none>,
0392 <2 RK_PB1 1 &pcfg_pull_none>,
0393 <2 RK_PB2 1 &pcfg_pull_none>,
0394 <2 RK_PB3 1 &pcfg_pull_none>,
0395 <2 RK_PB4 1 &pcfg_pull_none>,
0396 <2 RK_PB5 1 &pcfg_pull_none>,
0397 <2 RK_PB6 1 &pcfg_pull_none>,
0398 <2 RK_PB7 1 &pcfg_pull_none>,
0399 <2 RK_PC0 1 &pcfg_pull_none>,
0400 <2 RK_PC1 1 &pcfg_pull_none>,
0401 <2 RK_PC2 1 &pcfg_pull_none>,
0402 <2 RK_PC3 1 &pcfg_pull_none>,
0403 <2 RK_PC4 1 &pcfg_pull_none>,
0404 <2 RK_PC5 1 &pcfg_pull_none>,
0405 <2 RK_PC6 1 &pcfg_pull_none>,
0406 <2 RK_PC7 1 &pcfg_pull_none>;
0407 };
0408 };
0409
0410 pwm0 {
0411 pwm0_out: pwm0-out {
0412 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
0413 };
0414 };
0415
0416 pwm1 {
0417 pwm1_out: pwm1-out {
0418 rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>;
0419 };
0420 };
0421
0422 pwm2 {
0423 pwm2_out: pwm2-out {
0424 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>;
0425 };
0426 };
0427
0428 pwm3 {
0429 pwm3_out: pwm3-out {
0430 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>;
0431 };
0432 };
0433
0434 spi0 {
0435 spi0_clk: spi0-clk {
0436 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>;
0437 };
0438 spi0_cs0: spi0-cs0 {
0439 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>;
0440 };
0441 spi0_tx: spi0-tx {
0442 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>;
0443 };
0444 spi0_rx: spi0-rx {
0445 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>;
0446 };
0447 spi0_cs1: spi0-cs1 {
0448 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>;
0449 };
0450 };
0451
0452 spi1 {
0453 spi1_clk: spi1-clk {
0454 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>;
0455 };
0456 spi1_cs0: spi1-cs0 {
0457 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>;
0458 };
0459 spi1_rx: spi1-rx {
0460 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>;
0461 };
0462 spi1_tx: spi1-tx {
0463 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>;
0464 };
0465 spi1_cs1: spi1-cs1 {
0466 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
0467 };
0468 };
0469
0470 uart0 {
0471 uart0_xfer: uart0-xfer {
0472 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>,
0473 <1 RK_PA1 1 &pcfg_pull_none>;
0474 };
0475
0476 uart0_cts: uart0-cts {
0477 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>;
0478 };
0479
0480 uart0_rts: uart0-rts {
0481 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>;
0482 };
0483 };
0484
0485 uart1 {
0486 uart1_xfer: uart1-xfer {
0487 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>,
0488 <1 RK_PA5 1 &pcfg_pull_none>;
0489 };
0490
0491 uart1_cts: uart1-cts {
0492 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
0493 };
0494
0495 uart1_rts: uart1-rts {
0496 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>;
0497 };
0498 };
0499
0500 uart2 {
0501 uart2_xfer: uart2-xfer {
0502 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>,
0503 <1 RK_PB1 1 &pcfg_pull_none>;
0504 };
0505 /* no rts / cts for uart2 */
0506 };
0507
0508 uart3 {
0509 uart3_xfer: uart3-xfer {
0510 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>,
0511 <1 RK_PB3 1 &pcfg_pull_none>;
0512 };
0513
0514 uart3_cts: uart3-cts {
0515 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>;
0516 };
0517
0518 uart3_rts: uart3-rts {
0519 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>;
0520 };
0521 };
0522
0523 sd0 {
0524 sd0_clk: sd0-clk {
0525 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>;
0526 };
0527
0528 sd0_cmd: sd0-cmd {
0529 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
0530 };
0531
0532 sd0_cd: sd0-cd {
0533 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>;
0534 };
0535
0536 sd0_wp: sd0-wp {
0537 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>;
0538 };
0539
0540 sd0_pwr: sd0-pwr {
0541 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
0542 };
0543
0544 sd0_bus1: sd0-bus-width1 {
0545 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
0546 };
0547
0548 sd0_bus4: sd0-bus-width4 {
0549 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
0550 <3 RK_PA5 1 &pcfg_pull_none>,
0551 <3 RK_PA6 1 &pcfg_pull_none>,
0552 <3 RK_PA7 1 &pcfg_pull_none>;
0553 };
0554 };
0555
0556 sd1 {
0557 sd1_clk: sd1-clk {
0558 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
0559 };
0560
0561 sd1_cmd: sd1-cmd {
0562 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>;
0563 };
0564
0565 sd1_cd: sd1-cd {
0566 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>;
0567 };
0568
0569 sd1_wp: sd1-wp {
0570 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>;
0571 };
0572
0573 sd1_bus1: sd1-bus-width1 {
0574 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>;
0575 };
0576
0577 sd1_bus4: sd1-bus-width4 {
0578 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>,
0579 <3 RK_PC2 1 &pcfg_pull_none>,
0580 <3 RK_PC3 1 &pcfg_pull_none>,
0581 <3 RK_PC4 1 &pcfg_pull_none>;
0582 };
0583 };
0584
0585 i2s0 {
0586 i2s0_bus: i2s0-bus {
0587 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
0588 <1 RK_PC1 1 &pcfg_pull_none>,
0589 <1 RK_PC2 1 &pcfg_pull_none>,
0590 <1 RK_PC3 1 &pcfg_pull_none>,
0591 <1 RK_PC4 1 &pcfg_pull_none>,
0592 <1 RK_PC5 1 &pcfg_pull_none>;
0593 };
0594 };
0595
0596 spdif {
0597 spdif_tx: spdif-tx {
0598 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>;
0599 };
0600 };
0601 };
0602 };
0603
0604 &emac {
0605 compatible = "rockchip,rk3188-emac";
0606 };
0607
0608 &global_timer {
0609 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
0610 status = "disabled";
0611 };
0612
0613 &local_timer {
0614 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
0615 };
0616
0617 &gpu {
0618 compatible = "rockchip,rk3188-mali", "arm,mali-400";
0619 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0620 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0621 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0622 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0623 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0624 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0625 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0626 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0627 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0628 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0629 interrupt-names = "gp",
0630 "gpmmu",
0631 "pp0",
0632 "ppmmu0",
0633 "pp1",
0634 "ppmmu1",
0635 "pp2",
0636 "ppmmu2",
0637 "pp3",
0638 "ppmmu3";
0639 power-domains = <&power RK3188_PD_GPU>;
0640 };
0641
0642 &grf {
0643 compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
0644
0645 io_domains: io-domains {
0646 compatible = "rockchip,rk3188-io-voltage-domain";
0647 status = "disabled";
0648 };
0649
0650 usbphy: usbphy {
0651 compatible = "rockchip,rk3188-usb-phy";
0652 #address-cells = <1>;
0653 #size-cells = <0>;
0654 status = "disabled";
0655
0656 usbphy0: usb-phy@10c {
0657 reg = <0x10c>;
0658 clocks = <&cru SCLK_OTGPHY0>;
0659 clock-names = "phyclk";
0660 #clock-cells = <0>;
0661 #phy-cells = <0>;
0662 };
0663
0664 usbphy1: usb-phy@11c {
0665 reg = <0x11c>;
0666 clocks = <&cru SCLK_OTGPHY1>;
0667 clock-names = "phyclk";
0668 #clock-cells = <0>;
0669 #phy-cells = <0>;
0670 };
0671 };
0672 };
0673
0674 &i2c0 {
0675 compatible = "rockchip,rk3188-i2c";
0676 pinctrl-names = "default";
0677 pinctrl-0 = <&i2c0_xfer>;
0678 };
0679
0680 &i2c1 {
0681 compatible = "rockchip,rk3188-i2c";
0682 pinctrl-names = "default";
0683 pinctrl-0 = <&i2c1_xfer>;
0684 };
0685
0686 &i2c2 {
0687 compatible = "rockchip,rk3188-i2c";
0688 pinctrl-names = "default";
0689 pinctrl-0 = <&i2c2_xfer>;
0690 };
0691
0692 &i2c3 {
0693 compatible = "rockchip,rk3188-i2c";
0694 pinctrl-names = "default";
0695 pinctrl-0 = <&i2c3_xfer>;
0696 };
0697
0698 &i2c4 {
0699 compatible = "rockchip,rk3188-i2c";
0700 pinctrl-names = "default";
0701 pinctrl-0 = <&i2c4_xfer>;
0702 };
0703
0704 &pmu {
0705 power: power-controller {
0706 compatible = "rockchip,rk3188-power-controller";
0707 #power-domain-cells = <1>;
0708 #address-cells = <1>;
0709 #size-cells = <0>;
0710
0711 power-domain@RK3188_PD_VIO {
0712 reg = <RK3188_PD_VIO>;
0713 clocks = <&cru ACLK_LCDC0>,
0714 <&cru ACLK_LCDC1>,
0715 <&cru DCLK_LCDC0>,
0716 <&cru DCLK_LCDC1>,
0717 <&cru HCLK_LCDC0>,
0718 <&cru HCLK_LCDC1>,
0719 <&cru SCLK_CIF0>,
0720 <&cru ACLK_CIF0>,
0721 <&cru HCLK_CIF0>,
0722 <&cru ACLK_IPP>,
0723 <&cru HCLK_IPP>,
0724 <&cru ACLK_RGA>,
0725 <&cru HCLK_RGA>;
0726 pm_qos = <&qos_lcdc0>,
0727 <&qos_lcdc1>,
0728 <&qos_cif0>,
0729 <&qos_ipp>,
0730 <&qos_rga>;
0731 #power-domain-cells = <0>;
0732 };
0733
0734 power-domain@RK3188_PD_VIDEO {
0735 reg = <RK3188_PD_VIDEO>;
0736 clocks = <&cru ACLK_VDPU>,
0737 <&cru ACLK_VEPU>,
0738 <&cru HCLK_VDPU>,
0739 <&cru HCLK_VEPU>;
0740 pm_qos = <&qos_vpu>;
0741 #power-domain-cells = <0>;
0742 };
0743
0744 power-domain@RK3188_PD_GPU {
0745 reg = <RK3188_PD_GPU>;
0746 clocks = <&cru ACLK_GPU>;
0747 pm_qos = <&qos_gpu>;
0748 #power-domain-cells = <0>;
0749 };
0750 };
0751 };
0752
0753 &pwm0 {
0754 pinctrl-names = "default";
0755 pinctrl-0 = <&pwm0_out>;
0756 };
0757
0758 &pwm1 {
0759 pinctrl-names = "default";
0760 pinctrl-0 = <&pwm1_out>;
0761 };
0762
0763 &pwm2 {
0764 pinctrl-names = "default";
0765 pinctrl-0 = <&pwm2_out>;
0766 };
0767
0768 &pwm3 {
0769 pinctrl-names = "default";
0770 pinctrl-0 = <&pwm3_out>;
0771 };
0772
0773 &spi0 {
0774 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
0775 pinctrl-names = "default";
0776 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
0777 };
0778
0779 &spi1 {
0780 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
0781 pinctrl-names = "default";
0782 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
0783 };
0784
0785 &uart0 {
0786 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
0787 pinctrl-names = "default";
0788 pinctrl-0 = <&uart0_xfer>;
0789 };
0790
0791 &uart1 {
0792 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
0793 pinctrl-names = "default";
0794 pinctrl-0 = <&uart1_xfer>;
0795 };
0796
0797 &uart2 {
0798 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
0799 pinctrl-names = "default";
0800 pinctrl-0 = <&uart2_xfer>;
0801 };
0802
0803 &uart3 {
0804 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
0805 pinctrl-names = "default";
0806 pinctrl-0 = <&uart3_xfer>;
0807 };
0808
0809 &vpu {
0810 compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu";
0811 power-domains = <&power RK3188_PD_VIDEO>;
0812 };
0813
0814 &wdt {
0815 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
0816 };
