0001 // SPDX-License-Identifier: GPL-2.0
0002 /dts-v1/;
0003
0004 #include <dt-bindings/interconnect/qcom,msm8974.h>
0005 #include <dt-bindings/interrupt-controller/arm-gic.h>
0006 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
0007 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
0008 #include <dt-bindings/clock/qcom,rpmcc.h>
0009 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
0010 #include <dt-bindings/gpio/gpio.h>
0011
0012 / {
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015 interrupt-parent = <&intc>;
0016
0017 clocks {
0018 xo_board: xo_board {
0019 compatible = "fixed-clock";
0020 #clock-cells = <0>;
0021 clock-frequency = <19200000>;
0022 };
0023
0024 sleep_clk: sleep_clk {
0025 compatible = "fixed-clock";
0026 #clock-cells = <0>;
0027 clock-frequency = <32768>;
0028 };
0029 };
0030
0031 cpus {
0032 #address-cells = <1>;
0033 #size-cells = <0>;
0034 interrupts = <GIC_PPI 9 0xf04>;
0035
0036 CPU0: cpu@0 {
0037 compatible = "qcom,krait";
0038 enable-method = "qcom,kpss-acc-v2";
0039 device_type = "cpu";
0040 reg = <0>;
0041 next-level-cache = <&L2>;
0042 qcom,acc = <&acc0>;
0043 qcom,saw = <&saw0>;
0044 cpu-idle-states = <&CPU_SPC>;
0045 };
0046
0047 CPU1: cpu@1 {
0048 compatible = "qcom,krait";
0049 enable-method = "qcom,kpss-acc-v2";
0050 device_type = "cpu";
0051 reg = <1>;
0052 next-level-cache = <&L2>;
0053 qcom,acc = <&acc1>;
0054 qcom,saw = <&saw1>;
0055 cpu-idle-states = <&CPU_SPC>;
0056 };
0057
0058 CPU2: cpu@2 {
0059 compatible = "qcom,krait";
0060 enable-method = "qcom,kpss-acc-v2";
0061 device_type = "cpu";
0062 reg = <2>;
0063 next-level-cache = <&L2>;
0064 qcom,acc = <&acc2>;
0065 qcom,saw = <&saw2>;
0066 cpu-idle-states = <&CPU_SPC>;
0067 };
0068
0069 CPU3: cpu@3 {
0070 compatible = "qcom,krait";
0071 enable-method = "qcom,kpss-acc-v2";
0072 device_type = "cpu";
0073 reg = <3>;
0074 next-level-cache = <&L2>;
0075 qcom,acc = <&acc3>;
0076 qcom,saw = <&saw3>;
0077 cpu-idle-states = <&CPU_SPC>;
0078 };
0079
0080 L2: l2-cache {
0081 compatible = "cache";
0082 cache-level = <2>;
0083 qcom,saw = <&saw_l2>;
0084 };
0085
0086 idle-states {
0087 CPU_SPC: spc {
0088 compatible = "qcom,idle-state-spc",
0089 "arm,idle-state";
0090 entry-latency-us = <150>;
0091 exit-latency-us = <200>;
0092 min-residency-us = <2000>;
0093 };
0094 };
0095 };
0096
0097 firmware {
0098 scm {
0099 compatible = "qcom,scm-msm8974", "qcom,scm";
0100 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
0101 clock-names = "core", "bus", "iface";
0102 };
0103 };
0104
0105 memory {
0106 device_type = "memory";
0107 reg = <0x0 0x0>;
0108 };
0109
0110 pmu {
0111 compatible = "qcom,krait-pmu";
0112 interrupts = <GIC_PPI 7 0xf04>;
0113 };
0114
0115 reserved-memory {
0116 #address-cells = <1>;
0117 #size-cells = <1>;
0118 ranges;
0119
0120 mpss_region: mpss@8000000 {
0121 reg = <0x08000000 0x5100000>;
0122 no-map;
0123 };
0124
0125 mba_region: mba@d100000 {
0126 reg = <0x0d100000 0x100000>;
0127 no-map;
0128 };
0129
0130 wcnss_region: wcnss@d200000 {
0131 reg = <0x0d200000 0xa00000>;
0132 no-map;
0133 };
0134
0135 adsp_region: adsp@dc00000 {
0136 reg = <0x0dc00000 0x1900000>;
0137 no-map;
0138 };
0139
0140 venus_region: memory@f500000 {
0141 reg = <0x0f500000 0x500000>;
0142 no-map;
0143 };
0144
0145 smem_region: smem@fa00000 {
0146 reg = <0xfa00000 0x200000>;
0147 no-map;
0148 };
0149
0150 tz_region: memory@fc00000 {
0151 reg = <0x0fc00000 0x160000>;
0152 no-map;
0153 };
0154
0155 rfsa_mem: memory@fd60000 {
0156 reg = <0x0fd60000 0x20000>;
0157 no-map;
0158 };
0159
0160 rmtfs@fd80000 {
0161 compatible = "qcom,rmtfs-mem";
0162 reg = <0x0fd80000 0x180000>;
0163 no-map;
0164
0165 qcom,client-id = <1>;
0166 };
0167 };
0168
0169 smem {
0170 compatible = "qcom,smem";
0171
0172 memory-region = <&smem_region>;
0173 qcom,rpm-msg-ram = <&rpm_msg_ram>;
0174
0175 hwlocks = <&tcsr_mutex 3>;
0176 };
0177
0178 smp2p-adsp {
0179 compatible = "qcom,smp2p";
0180 qcom,smem = <443>, <429>;
0181
0182 interrupt-parent = <&intc>;
0183 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
0184
0185 qcom,ipc = <&apcs 8 10>;
0186
0187 qcom,local-pid = <0>;
0188 qcom,remote-pid = <2>;
0189
0190 adsp_smp2p_out: master-kernel {
0191 qcom,entry-name = "master-kernel";
0192 #qcom,smem-state-cells = <1>;
0193 };
0194
0195 adsp_smp2p_in: slave-kernel {
0196 qcom,entry-name = "slave-kernel";
0197
0198 interrupt-controller;
0199 #interrupt-cells = <2>;
0200 };
0201 };
0202
0203 smp2p-modem {
0204 compatible = "qcom,smp2p";
0205 qcom,smem = <435>, <428>;
0206
0207 interrupt-parent = <&intc>;
0208 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
0209
0210 qcom,ipc = <&apcs 8 14>;
0211
0212 qcom,local-pid = <0>;
0213 qcom,remote-pid = <1>;
0214
0215 modem_smp2p_out: master-kernel {
0216 qcom,entry-name = "master-kernel";
0217 #qcom,smem-state-cells = <1>;
0218 };
0219
0220 modem_smp2p_in: slave-kernel {
0221 qcom,entry-name = "slave-kernel";
0222
0223 interrupt-controller;
0224 #interrupt-cells = <2>;
0225 };
0226 };
0227
0228 smp2p-wcnss {
0229 compatible = "qcom,smp2p";
0230 qcom,smem = <451>, <431>;
0231
0232 interrupt-parent = <&intc>;
0233 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
0234
0235 qcom,ipc = <&apcs 8 18>;
0236
0237 qcom,local-pid = <0>;
0238 qcom,remote-pid = <4>;
0239
0240 wcnss_smp2p_out: master-kernel {
0241 qcom,entry-name = "master-kernel";
0242
0243 #qcom,smem-state-cells = <1>;
0244 };
0245
0246 wcnss_smp2p_in: slave-kernel {
0247 qcom,entry-name = "slave-kernel";
0248
0249 interrupt-controller;
0250 #interrupt-cells = <2>;
0251 };
0252 };
0253
0254 smsm {
0255 compatible = "qcom,smsm";
0256
0257 #address-cells = <1>;
0258 #size-cells = <0>;
0259
0260 qcom,ipc-1 = <&apcs 8 13>;
0261 qcom,ipc-2 = <&apcs 8 9>;
0262 qcom,ipc-3 = <&apcs 8 19>;
0263
0264 apps_smsm: apps@0 {
0265 reg = <0>;
0266
0267 #qcom,smem-state-cells = <1>;
0268 };
0269
0270 modem_smsm: modem@1 {
0271 reg = <1>;
0272 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
0273
0274 interrupt-controller;
0275 #interrupt-cells = <2>;
0276 };
0277
0278 adsp_smsm: adsp@2 {
0279 reg = <2>;
0280 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
0281
0282 interrupt-controller;
0283 #interrupt-cells = <2>;
0284 };
0285
0286 wcnss_smsm: wcnss@7 {
0287 reg = <7>;
0288 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
0289
0290 interrupt-controller;
0291 #interrupt-cells = <2>;
0292 };
0293 };
0294
0295 smd {
0296 compatible = "qcom,smd";
0297
0298 rpm {
0299 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
0300 qcom,ipc = <&apcs 8 0>;
0301 qcom,smd-edge = <15>;
0302
0303 rpm_requests: rpm_requests {
0304 compatible = "qcom,rpm-msm8974";
0305 qcom,smd-channels = "rpm_requests";
0306
0307 rpmcc: clock-controller {
0308 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
0309 #clock-cells = <1>;
0310 };
0311 };
0312 };
0313 };
0314
0315 soc: soc {
0316 #address-cells = <1>;
0317 #size-cells = <1>;
0318 ranges;
0319 compatible = "simple-bus";
0320
0321 intc: interrupt-controller@f9000000 {
0322 compatible = "qcom,msm-qgic2";
0323 interrupt-controller;
0324 #interrupt-cells = <3>;
0325 reg = <0xf9000000 0x1000>,
0326 <0xf9002000 0x1000>;
0327 };
0328
0329 apcs: syscon@f9011000 {
0330 compatible = "syscon";
0331 reg = <0xf9011000 0x1000>;
0332 };
0333
0334 timer@f9020000 {
0335 #address-cells = <1>;
0336 #size-cells = <1>;
0337 ranges;
0338 compatible = "arm,armv7-timer-mem";
0339 reg = <0xf9020000 0x1000>;
0340 clock-frequency = <19200000>;
0341
0342 frame@f9021000 {
0343 frame-number = <0>;
0344 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0345 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0346 reg = <0xf9021000 0x1000>,
0347 <0xf9022000 0x1000>;
0348 };
0349
0350 frame@f9023000 {
0351 frame-number = <1>;
0352 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0353 reg = <0xf9023000 0x1000>;
0354 status = "disabled";
0355 };
0356
0357 frame@f9024000 {
0358 frame-number = <2>;
0359 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0360 reg = <0xf9024000 0x1000>;
0361 status = "disabled";
0362 };
0363
0364 frame@f9025000 {
0365 frame-number = <3>;
0366 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0367 reg = <0xf9025000 0x1000>;
0368 status = "disabled";
0369 };
0370
0371 frame@f9026000 {
0372 frame-number = <4>;
0373 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0374 reg = <0xf9026000 0x1000>;
0375 status = "disabled";
0376 };
0377
0378 frame@f9027000 {
0379 frame-number = <5>;
0380 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0381 reg = <0xf9027000 0x1000>;
0382 status = "disabled";
0383 };
0384
0385 frame@f9028000 {
0386 frame-number = <6>;
0387 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0388 reg = <0xf9028000 0x1000>;
0389 status = "disabled";
0390 };
0391 };
0392
0393 saw0: power-controller@f9089000 {
0394 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
0395 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
0396 };
0397
0398 saw1: power-controller@f9099000 {
0399 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
0400 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
0401 };
0402
0403 saw2: power-controller@f90a9000 {
0404 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
0405 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
0406 };
0407
0408 saw3: power-controller@f90b9000 {
0409 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
0410 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
0411 };
0412
0413 saw_l2: power-controller@f9012000 {
0414 compatible = "qcom,saw2";
0415 reg = <0xf9012000 0x1000>;
0416 regulator;
0417 };
0418
0419 acc0: clock-controller@f9088000 {
0420 compatible = "qcom,kpss-acc-v2";
0421 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
0422 };
0423
0424 acc1: clock-controller@f9098000 {
0425 compatible = "qcom,kpss-acc-v2";
0426 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
0427 };
0428
0429 acc2: clock-controller@f90a8000 {
0430 compatible = "qcom,kpss-acc-v2";
0431 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
0432 };
0433
0434 acc3: clock-controller@f90b8000 {
0435 compatible = "qcom,kpss-acc-v2";
0436 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
0437 };
0438
0439 sdhc_1: mmc@f9824900 {
0440 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
0441 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
0442 reg-names = "hc_mem", "core_mem";
0443 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
0444 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
0445 interrupt-names = "hc_irq", "pwr_irq";
0446 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
0447 <&gcc GCC_SDCC1_AHB_CLK>,
0448 <&xo_board>;
0449 clock-names = "core", "iface", "xo";
0450 bus-width = <8>;
0451 non-removable;
0452
0453 status = "disabled";
0454 };
0455
0456 sdhc_3: mmc@f9864900 {
0457 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
0458 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
0459 reg-names = "hc_mem", "core_mem";
0460 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
0461 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
0462 interrupt-names = "hc_irq", "pwr_irq";
0463 clocks = <&gcc GCC_SDCC3_APPS_CLK>,
0464 <&gcc GCC_SDCC3_AHB_CLK>,
0465 <&xo_board>;
0466 clock-names = "core", "iface", "xo";
0467 bus-width = <4>;
0468
0469 #address-cells = <1>;
0470 #size-cells = <0>;
0471
0472 status = "disabled";
0473 };
0474
0475 sdhc_2: mmc@f98a4900 {
0476 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
0477 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
0478 reg-names = "hc_mem", "core_mem";
0479 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
0480 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
0481 interrupt-names = "hc_irq", "pwr_irq";
0482 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
0483 <&gcc GCC_SDCC2_AHB_CLK>,
0484 <&xo_board>;
0485 clock-names = "core", "iface", "xo";
0486 bus-width = <4>;
0487
0488 #address-cells = <1>;
0489 #size-cells = <0>;
0490
0491 status = "disabled";
0492 };
0493
0494 blsp1_uart1: serial@f991d000 {
0495 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0496 reg = <0xf991d000 0x1000>;
0497 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0498 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0499 clock-names = "core", "iface";
0500 status = "disabled";
0501 };
0502
0503 blsp1_uart2: serial@f991e000 {
0504 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0505 reg = <0xf991e000 0x1000>;
0506 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
0507 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0508 clock-names = "core", "iface";
0509 pinctrl-names = "default";
0510 pinctrl-0 = <&blsp1_uart2_default>;
0511 status = "disabled";
0512 };
0513
0514 blsp1_i2c1: i2c@f9923000 {
0515 status = "disabled";
0516 compatible = "qcom,i2c-qup-v2.1.1";
0517 reg = <0xf9923000 0x1000>;
0518 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
0519 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0520 clock-names = "core", "iface";
0521 pinctrl-names = "default", "sleep";
0522 pinctrl-0 = <&blsp1_i2c1_default>;
0523 pinctrl-1 = <&blsp1_i2c1_sleep>;
0524 #address-cells = <1>;
0525 #size-cells = <0>;
0526 };
0527
0528 blsp1_i2c2: i2c@f9924000 {
0529 status = "disabled";
0530 compatible = "qcom,i2c-qup-v2.1.1";
0531 reg = <0xf9924000 0x1000>;
0532 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0533 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0534 clock-names = "core", "iface";
0535 pinctrl-names = "default", "sleep";
0536 pinctrl-0 = <&blsp1_i2c2_default>;
0537 pinctrl-1 = <&blsp1_i2c2_sleep>;
0538 #address-cells = <1>;
0539 #size-cells = <0>;
0540 };
0541
0542 blsp1_i2c3: i2c@f9925000 {
0543 status = "disabled";
0544 compatible = "qcom,i2c-qup-v2.1.1";
0545 reg = <0xf9925000 0x1000>;
0546 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
0547 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0548 clock-names = "core", "iface";
0549 pinctrl-names = "default", "sleep";
0550 pinctrl-0 = <&blsp1_i2c3_default>;
0551 pinctrl-1 = <&blsp1_i2c3_sleep>;
0552 #address-cells = <1>;
0553 #size-cells = <0>;
0554 };
0555
0556 blsp1_i2c6: i2c@f9928000 {
0557 status = "disabled";
0558 compatible = "qcom,i2c-qup-v2.1.1";
0559 reg = <0xf9928000 0x1000>;
0560 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0561 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0562 clock-names = "core", "iface";
0563 pinctrl-names = "default", "sleep";
0564 pinctrl-0 = <&blsp1_i2c6_default>;
0565 pinctrl-1 = <&blsp1_i2c6_sleep>;
0566 #address-cells = <1>;
0567 #size-cells = <0>;
0568 };
0569
0570 blsp2_dma: dma-controller@f9944000 {
0571 compatible = "qcom,bam-v1.4.0";
0572 reg = <0xf9944000 0x19000>;
0573 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
0574 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
0575 clock-names = "bam_clk";
0576 #dma-cells = <1>;
0577 qcom,ee = <0>;
0578 };
0579
0580 blsp2_uart1: serial@f995d000 {
0581 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0582 reg = <0xf995d000 0x1000>;
0583 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
0584 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
0585 clock-names = "core", "iface";
0586 pinctrl-names = "default", "sleep";
0587 pinctrl-0 = <&blsp2_uart1_default>;
0588 pinctrl-1 = <&blsp2_uart1_sleep>;
0589 status = "disabled";
0590 };
0591
0592 blsp2_uart2: serial@f995e000 {
0593 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0594 reg = <0xf995e000 0x1000>;
0595 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0596 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
0597 clock-names = "core", "iface";
0598 status = "disabled";
0599 };
0600
0601 blsp2_uart4: serial@f9960000 {
0602 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0603 reg = <0xf9960000 0x1000>;
0604 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
0605 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
0606 clock-names = "core", "iface";
0607 pinctrl-names = "default";
0608 pinctrl-0 = <&blsp2_uart4_default>;
0609 status = "disabled";
0610 };
0611
0612 blsp2_i2c2: i2c@f9964000 {
0613 status = "disabled";
0614 compatible = "qcom,i2c-qup-v2.1.1";
0615 reg = <0xf9964000 0x1000>;
0616 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
0617 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
0618 clock-names = "core", "iface";
0619 pinctrl-names = "default", "sleep";
0620 pinctrl-0 = <&blsp2_i2c2_default>;
0621 pinctrl-1 = <&blsp2_i2c2_sleep>;
0622 #address-cells = <1>;
0623 #size-cells = <0>;
0624 };
0625
0626 blsp2_i2c5: i2c@f9967000 {
0627 status = "disabled";
0628 compatible = "qcom,i2c-qup-v2.1.1";
0629 reg = <0xf9967000 0x1000>;
0630 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0631 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
0632 clock-names = "core", "iface";
0633 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
0634 dma-names = "tx", "rx";
0635 pinctrl-names = "default", "sleep";
0636 pinctrl-0 = <&blsp2_i2c5_default>;
0637 pinctrl-1 = <&blsp2_i2c5_sleep>;
0638 #address-cells = <1>;
0639 #size-cells = <0>;
0640 };
0641
0642 blsp2_i2c6: i2c@f9968000 {
0643 status = "disabled";
0644 compatible = "qcom,i2c-qup-v2.1.1";
0645 reg = <0xf9968000 0x1000>;
0646 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
0647 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
0648 clock-names = "core", "iface";
0649 pinctrl-names = "default", "sleep";
0650 pinctrl-0 = <&blsp2_i2c6_default>;
0651 pinctrl-1 = <&blsp2_i2c6_sleep>;
0652 #address-cells = <1>;
0653 #size-cells = <0>;
0654 };
0655
0656 otg: usb@f9a55000 {
0657 compatible = "qcom,ci-hdrc";
0658 reg = <0xf9a55000 0x200>,
0659 <0xf9a55200 0x200>;
0660 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
0661 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
0662 <&gcc GCC_USB_HS_SYSTEM_CLK>;
0663 clock-names = "iface", "core";
0664 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
0665 assigned-clock-rates = <75000000>;
0666 resets = <&gcc GCC_USB_HS_BCR>;
0667 reset-names = "core";
0668 phy_type = "ulpi";
0669 dr_mode = "otg";
0670 ahb-burst-config = <0>;
0671 phy-names = "usb-phy";
0672 status = "disabled";
0673 #reset-cells = <1>;
0674
0675 ulpi {
0676 usb_hs1_phy: phy@a {
0677 compatible = "qcom,usb-hs-phy-msm8974",
0678 "qcom,usb-hs-phy";
0679 #phy-cells = <0>;
0680 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
0681 clock-names = "ref", "sleep";
0682 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
0683 reset-names = "phy", "por";
0684 status = "disabled";
0685 };
0686
0687 usb_hs2_phy: phy@b {
0688 compatible = "qcom,usb-hs-phy-msm8974",
0689 "qcom,usb-hs-phy";
0690 #phy-cells = <0>;
0691 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
0692 clock-names = "ref", "sleep";
0693 resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
0694 reset-names = "phy", "por";
0695 status = "disabled";
0696 };
0697 };
0698 };
0699
0700 rng@f9bff000 {
0701 compatible = "qcom,prng";
0702 reg = <0xf9bff000 0x200>;
0703 clocks = <&gcc GCC_PRNG_AHB_CLK>;
0704 clock-names = "core";
0705 };
0706
0707 pronto: remoteproc@fb21b000 {
0708 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
0709 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
0710 reg-names = "ccu", "dxe", "pmu";
0711
0712 memory-region = <&wcnss_region>;
0713
0714 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
0715 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
0716 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
0717 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
0718 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
0719 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
0720
0721 qcom,smem-states = <&wcnss_smp2p_out 0>;
0722 qcom,smem-state-names = "stop";
0723
0724 status = "disabled";
0725
0726 iris {
0727 compatible = "qcom,wcn3680";
0728
0729 clocks = <&rpmcc RPM_SMD_CXO_A2>;
0730 clock-names = "xo";
0731 };
0732
0733 smd-edge {
0734 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
0735
0736 qcom,ipc = <&apcs 8 17>;
0737 qcom,smd-edge = <6>;
0738
0739 wcnss {
0740 compatible = "qcom,wcnss";
0741 qcom,smd-channels = "WCNSS_CTRL";
0742 status = "disabled";
0743
0744 qcom,mmio = <&pronto>;
0745
0746 bt {
0747 compatible = "qcom,wcnss-bt";
0748 };
0749
0750 wifi {
0751 compatible = "qcom,wcnss-wlan";
0752
0753 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
0754 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
0755 interrupt-names = "tx", "rx";
0756
0757 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
0758 qcom,smem-state-names = "tx-enable",
0759 "tx-rings-empty";
0760 };
0761 };
0762 };
0763 };
0764
0765 etf@fc307000 {
0766 compatible = "arm,coresight-tmc", "arm,primecell";
0767 reg = <0xfc307000 0x1000>;
0768
0769 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
0770 clock-names = "apb_pclk", "atclk";
0771
0772 out-ports {
0773 port {
0774 etf_out: endpoint {
0775 remote-endpoint = <&replicator_in>;
0776 };
0777 };
0778 };
0779
0780 in-ports {
0781 port {
0782 etf_in: endpoint {
0783 remote-endpoint = <&merger_out>;
0784 };
0785 };
0786 };
0787 };
0788
0789 tpiu@fc318000 {
0790 compatible = "arm,coresight-tpiu", "arm,primecell";
0791 reg = <0xfc318000 0x1000>;
0792
0793 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
0794 clock-names = "apb_pclk", "atclk";
0795
0796 in-ports {
0797 port {
0798 tpiu_in: endpoint {
0799 remote-endpoint = <&replicator_out1>;
0800 };
0801 };
0802 };
0803 };
0804
0805 funnel@fc31a000 {
0806 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0807 reg = <0xfc31a000 0x1000>;
0808
0809 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
0810 clock-names = "apb_pclk", "atclk";
0811
0812 in-ports {
0813 #address-cells = <1>;
0814 #size-cells = <0>;
0815
0816 /*
0817 * Not described input ports:
0818 * 0 - not-connected
0819 * 1 - connected trought funnel to Multimedia CPU
0820 * 2 - connected to Wireless CPU
0821 * 3 - not-connected
0822 * 4 - not-connected
0823 * 6 - not-connected
0824 * 7 - connected to STM
0825 */
0826 port@5 {
0827 reg = <5>;
0828 funnel1_in5: endpoint {
0829 remote-endpoint = <&kpss_out>;
0830 };
0831 };
0832 };
0833
0834 out-ports {
0835 port {
0836 funnel1_out: endpoint {
0837 remote-endpoint = <&merger_in1>;
0838 };
0839 };
0840 };
0841 };
0842
0843 funnel@fc31b000 {
0844 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0845 reg = <0xfc31b000 0x1000>;
0846
0847 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
0848 clock-names = "apb_pclk", "atclk";
0849
0850 in-ports {
0851 #address-cells = <1>;
0852 #size-cells = <0>;
0853
0854 /*
0855 * Not described input ports:
0856 * 0 - connected trought funnel to Audio, Modem and
0857 * Resource and Power Manager CPU's
0858 * 2...7 - not-connected
0859 */
0860 port@1 {
0861 reg = <1>;
0862 merger_in1: endpoint {
0863 remote-endpoint = <&funnel1_out>;
0864 };
0865 };
0866 };
0867
0868 out-ports {
0869 port {
0870 merger_out: endpoint {
0871 remote-endpoint = <&etf_in>;
0872 };
0873 };
0874 };
0875 };
0876
0877 replicator@fc31c000 {
0878 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
0879 reg = <0xfc31c000 0x1000>;
0880
0881 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
0882 clock-names = "apb_pclk", "atclk";
0883
0884 out-ports {
0885 #address-cells = <1>;
0886 #size-cells = <0>;
0887
0888 port@0 {
0889 reg = <0>;
0890 replicator_out0: endpoint {
0891 remote-endpoint = <&etr_in>;
0892 };
0893 };
0894 port@1 {
0895 reg = <1>;
0896 replicator_out1: endpoint {
0897 remote-endpoint = <&tpiu_in>;
0898 };
0899 };
0900 };
0901
0902 in-ports {
0903 port {
0904 replicator_in: endpoint {
0905 remote-endpoint = <&etf_out>;
0906 };
0907 };
0908 };
0909 };
0910
0911 etr@fc322000 {
0912 compatible = "arm,coresight-tmc", "arm,primecell";
0913 reg = <0xfc322000 0x1000>;
0914
0915 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
0916 clock-names = "apb_pclk", "atclk";
0917
0918 in-ports {
0919 port {
0920 etr_in: endpoint {
0921 remote-endpoint = <&replicator_out0>;
0922 };
0923 };
0924 };
0925 };
0926
0927 etm@fc33c000 {
0928 compatible = "arm,coresight-etm4x", "arm,primecell";
0929 reg = <0xfc33c000 0x1000>;
0930
0931 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
0932 clock-names = "apb_pclk", "atclk";
0933
0934 cpu = <&CPU0>;
0935
0936 out-ports {
0937 port {
0938 etm0_out: endpoint {
0939 remote-endpoint = <&kpss_in0>;
0940 };
0941 };
0942 };
0943 };
0944
0945 etm@fc33d000 {
0946 compatible = "arm,coresight-etm4x", "arm,primecell";
0947 reg = <0xfc33d000 0x1000>;
0948
0949 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
0950 clock-names = "apb_pclk", "atclk";
0951
0952 cpu = <&CPU1>;
0953
0954 out-ports {
0955 port {
0956 etm1_out: endpoint {
0957 remote-endpoint = <&kpss_in1>;
0958 };
0959 };
0960 };
0961 };
0962
0963 etm@fc33e000 {
0964 compatible = "arm,coresight-etm4x", "arm,primecell";
0965 reg = <0xfc33e000 0x1000>;
0966
0967 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
0968 clock-names = "apb_pclk", "atclk";
0969
0970 cpu = <&CPU2>;
0971
0972 out-ports {
0973 port {
0974 etm2_out: endpoint {
0975 remote-endpoint = <&kpss_in2>;
0976 };
0977 };
0978 };
0979 };
0980
0981 etm@fc33f000 {
0982 compatible = "arm,coresight-etm4x", "arm,primecell";
0983 reg = <0xfc33f000 0x1000>;
0984
0985 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
0986 clock-names = "apb_pclk", "atclk";
0987
0988 cpu = <&CPU3>;
0989
0990 out-ports {
0991 port {
0992 etm3_out: endpoint {
0993 remote-endpoint = <&kpss_in3>;
0994 };
0995 };
0996 };
0997 };
0998
0999 /* KPSS funnel, only 4 inputs are used */
1000 funnel@fc345000 {
1001 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1002 reg = <0xfc345000 0x1000>;
1003
1004 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1005 clock-names = "apb_pclk", "atclk";
1006
1007 in-ports {
1008 #address-cells = <1>;
1009 #size-cells = <0>;
1010
1011 port@0 {
1012 reg = <0>;
1013 kpss_in0: endpoint {
1014 remote-endpoint = <&etm0_out>;
1015 };
1016 };
1017 port@1 {
1018 reg = <1>;
1019 kpss_in1: endpoint {
1020 remote-endpoint = <&etm1_out>;
1021 };
1022 };
1023 port@2 {
1024 reg = <2>;
1025 kpss_in2: endpoint {
1026 remote-endpoint = <&etm2_out>;
1027 };
1028 };
1029 port@3 {
1030 reg = <3>;
1031 kpss_in3: endpoint {
1032 remote-endpoint = <&etm3_out>;
1033 };
1034 };
1035 };
1036
1037 out-ports {
1038 port {
1039 kpss_out: endpoint {
1040 remote-endpoint = <&funnel1_in5>;
1041 };
1042 };
1043 };
1044 };
1045
1046 gcc: clock-controller@fc400000 {
1047 compatible = "qcom,gcc-msm8974";
1048 #clock-cells = <1>;
1049 #reset-cells = <1>;
1050 #power-domain-cells = <1>;
1051 reg = <0xfc400000 0x4000>;
1052 };
1053
1054 rpm_msg_ram: memory@fc428000 {
1055 compatible = "qcom,rpm-msg-ram";
1056 reg = <0xfc428000 0x4000>;
1057 };
1058
1059 bimc: interconnect@fc380000 {
1060 reg = <0xfc380000 0x6a000>;
1061 compatible = "qcom,msm8974-bimc";
1062 #interconnect-cells = <1>;
1063 clock-names = "bus", "bus_a";
1064 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
1065 <&rpmcc RPM_SMD_BIMC_A_CLK>;
1066 };
1067
1068 snoc: interconnect@fc460000 {
1069 reg = <0xfc460000 0x4000>;
1070 compatible = "qcom,msm8974-snoc";
1071 #interconnect-cells = <1>;
1072 clock-names = "bus", "bus_a";
1073 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
1074 <&rpmcc RPM_SMD_SNOC_A_CLK>;
1075 };
1076
1077 pnoc: interconnect@fc468000 {
1078 reg = <0xfc468000 0x4000>;
1079 compatible = "qcom,msm8974-pnoc";
1080 #interconnect-cells = <1>;
1081 clock-names = "bus", "bus_a";
1082 clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
1083 <&rpmcc RPM_SMD_PNOC_A_CLK>;
1084 };
1085
1086 ocmemnoc: interconnect@fc470000 {
1087 reg = <0xfc470000 0x4000>;
1088 compatible = "qcom,msm8974-ocmemnoc";
1089 #interconnect-cells = <1>;
1090 clock-names = "bus", "bus_a";
1091 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1092 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
1093 };
1094
1095 mmssnoc: interconnect@fc478000 {
1096 reg = <0xfc478000 0x4000>;
1097 compatible = "qcom,msm8974-mmssnoc";
1098 #interconnect-cells = <1>;
1099 clock-names = "bus", "bus_a";
1100 clocks = <&mmcc MMSS_S0_AXI_CLK>,
1101 <&mmcc MMSS_S0_AXI_CLK>;
1102 };
1103
1104 cnoc: interconnect@fc480000 {
1105 reg = <0xfc480000 0x4000>;
1106 compatible = "qcom,msm8974-cnoc";
1107 #interconnect-cells = <1>;
1108 clock-names = "bus", "bus_a";
1109 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
1110 <&rpmcc RPM_SMD_CNOC_A_CLK>;
1111 };
1112
1113 tsens: thermal-sensor@fc4a9000 {
1114 compatible = "qcom,msm8974-tsens";
1115 reg = <0xfc4a9000 0x1000>, /* TM */
1116 <0xfc4a8000 0x1000>; /* SROT */
1117 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
1118 nvmem-cell-names = "calib", "calib_backup";
1119 #qcom,sensors = <11>;
1120 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1121 interrupt-names = "uplow";
1122 #thermal-sensor-cells = <1>;
1123 };
1124
1125 restart@fc4ab000 {
1126 compatible = "qcom,pshold";
1127 reg = <0xfc4ab000 0x4>;
1128 };
1129
1130 qfprom: qfprom@fc4bc000 {
1131 compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
1132 reg = <0xfc4bc000 0x1000>;
1133 #address-cells = <1>;
1134 #size-cells = <1>;
1135 tsens_calib: calib@d0 {
1136 reg = <0xd0 0x18>;
1137 };
1138 tsens_backup: backup@440 {
1139 reg = <0x440 0x10>;
1140 };
1141 };
1142
1143 spmi_bus: spmi@fc4cf000 {
1144 compatible = "qcom,spmi-pmic-arb";
1145 reg-names = "core", "intr", "cnfg";
1146 reg = <0xfc4cf000 0x1000>,
1147 <0xfc4cb000 0x1000>,
1148 <0xfc4ca000 0x1000>;
1149 interrupt-names = "periph_irq";
1150 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1151 qcom,ee = <0>;
1152 qcom,channel = <0>;
1153 #address-cells = <2>;
1154 #size-cells = <0>;
1155 interrupt-controller;
1156 #interrupt-cells = <4>;
1157 };
1158
1159 bam_dmux_dma: dma-controller@fc834000 {
1160 compatible = "qcom,bam-v1.4.0";
1161 reg = <0xfc834000 0x7000>;
1162 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1163 #dma-cells = <1>;
1164 qcom,ee = <0>;
1165
1166 num-channels = <6>;
1167 qcom,num-ees = <1>;
1168 qcom,powered-remotely;
1169 };
1170
1171 remoteproc_mss: remoteproc@fc880000 {
1172 compatible = "qcom,msm8974-mss-pil";
1173 reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
1174 reg-names = "qdsp6", "rmb";
1175
1176 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1177 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1178 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1179 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1180 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1181 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1182
1183 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1184 <&gcc GCC_MSS_CFG_AHB_CLK>,
1185 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1186 <&xo_board>;
1187 clock-names = "iface", "bus", "mem", "xo";
1188
1189 resets = <&gcc GCC_MSS_RESTART>;
1190 reset-names = "mss_restart";
1191
1192 qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
1193
1194 qcom,smem-states = <&modem_smp2p_out 0>;
1195 qcom,smem-state-names = "stop";
1196
1197 status = "disabled";
1198
1199 mba {
1200 memory-region = <&mba_region>;
1201 };
1202
1203 mpss {
1204 memory-region = <&mpss_region>;
1205 };
1206
1207 bam_dmux: bam-dmux {
1208 compatible = "qcom,bam-dmux";
1209
1210 interrupt-parent = <&modem_smsm>;
1211 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1212 interrupt-names = "pc", "pc-ack";
1213
1214 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1215 qcom,smem-state-names = "pc", "pc-ack";
1216
1217 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1218 dma-names = "tx", "rx";
1219 };
1220
1221 smd-edge {
1222 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1223
1224 qcom,ipc = <&apcs 8 12>;
1225 qcom,smd-edge = <0>;
1226
1227 label = "modem";
1228 };
1229 };
1230
1231 tcsr_mutex_block: syscon@fd484000 {
1232 compatible = "syscon";
1233 reg = <0xfd484000 0x2000>;
1234 };
1235
1236 tcsr: syscon@fd4a0000 {
1237 compatible = "syscon";
1238 reg = <0xfd4a0000 0x10000>;
1239 };
1240
1241 tlmm: pinctrl@fd510000 {
1242 compatible = "qcom,msm8974-pinctrl";
1243 reg = <0xfd510000 0x4000>;
1244 gpio-controller;
1245 gpio-ranges = <&tlmm 0 0 146>;
1246 #gpio-cells = <2>;
1247 interrupt-controller;
1248 #interrupt-cells = <2>;
1249 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1250
1251 sdc1_off: sdc1-off {
1252 clk {
1253 pins = "sdc1_clk";
1254 bias-disable;
1255 drive-strength = <2>;
1256 };
1257
1258 cmd {
1259 pins = "sdc1_cmd";
1260 bias-pull-up;
1261 drive-strength = <2>;
1262 };
1263
1264 data {
1265 pins = "sdc1_data";
1266 bias-pull-up;
1267 drive-strength = <2>;
1268 };
1269 };
1270
1271 sdc2_off: sdc2-off {
1272 clk {
1273 pins = "sdc2_clk";
1274 bias-disable;
1275 drive-strength = <2>;
1276 };
1277
1278 cmd {
1279 pins = "sdc2_cmd";
1280 bias-pull-up;
1281 drive-strength = <2>;
1282 };
1283
1284 data {
1285 pins = "sdc2_data";
1286 bias-pull-up;
1287 drive-strength = <2>;
1288 };
1289
1290 cd {
1291 pins = "gpio54";
1292 bias-disable;
1293 drive-strength = <2>;
1294 };
1295 };
1296
1297 blsp1_uart2_default: blsp1-uart2-default {
1298 rx {
1299 pins = "gpio5";
1300 function = "blsp_uart2";
1301 drive-strength = <2>;
1302 bias-pull-up;
1303 };
1304
1305 tx {
1306 pins = "gpio4";
1307 function = "blsp_uart2";
1308 drive-strength = <4>;
1309 bias-disable;
1310 };
1311 };
1312
1313 blsp2_uart1_default: blsp2-uart1-default {
1314 tx-rts {
1315 pins = "gpio41", "gpio44";
1316 function = "blsp_uart7";
1317 drive-strength = <2>;
1318 bias-disable;
1319 };
1320
1321 rx-cts {
1322 pins = "gpio42", "gpio43";
1323 function = "blsp_uart7";
1324 drive-strength = <2>;
1325 bias-pull-up;
1326 };
1327 };
1328
1329 blsp2_uart1_sleep: blsp2-uart1-sleep {
1330 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1331 function = "gpio";
1332 drive-strength = <2>;
1333 bias-pull-down;
1334 };
1335
1336 blsp2_uart4_default: blsp2-uart4-default {
1337 tx-rts {
1338 pins = "gpio53", "gpio56";
1339 function = "blsp_uart10";
1340 drive-strength = <2>;
1341 bias-disable;
1342 };
1343
1344 rx-cts {
1345 pins = "gpio54", "gpio55";
1346 function = "blsp_uart10";
1347 drive-strength = <2>;
1348 bias-pull-up;
1349 };
1350 };
1351
1352 blsp1_i2c1_default: blsp1-i2c1-default {
1353 pins = "gpio2", "gpio3";
1354 function = "blsp_i2c1";
1355 drive-strength = <2>;
1356 bias-disable;
1357 };
1358
1359 blsp1_i2c1_sleep: blsp1-i2c1-sleep {
1360 pins = "gpio2", "gpio3";
1361 function = "blsp_i2c1";
1362 drive-strength = <2>;
1363 bias-pull-up;
1364 };
1365
1366 blsp1_i2c2_default: blsp1-i2c2-default {
1367 pins = "gpio6", "gpio7";
1368 function = "blsp_i2c2";
1369 drive-strength = <2>;
1370 bias-disable;
1371 };
1372
1373 blsp1_i2c2_sleep: blsp1-i2c2-sleep {
1374 pins = "gpio6", "gpio7";
1375 function = "blsp_i2c2";
1376 drive-strength = <2>;
1377 bias-pull-up;
1378 };
1379
1380 blsp1_i2c3_default: blsp1-i2c3-default {
1381 pins = "gpio10", "gpio11";
1382 function = "blsp_i2c3";
1383 drive-strength = <2>;
1384 bias-disable;
1385 };
1386
1387 blsp1_i2c3_sleep: blsp1-i2c3-sleep {
1388 pins = "gpio10", "gpio11";
1389 function = "blsp_i2c3";
1390 drive-strength = <2>;
1391 bias-pull-up;
1392 };
1393
1394 /* BLSP1_I2C4 info is missing */
1395
1396 /* BLSP1_I2C5 info is missing */
1397
1398 blsp1_i2c6_default: blsp1-i2c6-default {
1399 pins = "gpio29", "gpio30";
1400 function = "blsp_i2c6";
1401 drive-strength = <2>;
1402 bias-disable;
1403 };
1404
1405 blsp1_i2c6_sleep: blsp1-i2c6-sleep {
1406 pins = "gpio29", "gpio30";
1407 function = "blsp_i2c6";
1408 drive-strength = <2>;
1409 bias-pull-up;
1410 };
1411 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1412
1413 /* BLSP2_I2C1 info is missing */
1414
1415 blsp2_i2c2_default: blsp2-i2c2-default {
1416 pins = "gpio47", "gpio48";
1417 function = "blsp_i2c8";
1418 drive-strength = <2>;
1419 bias-disable;
1420 };
1421
1422 blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1423 pins = "gpio47", "gpio48";
1424 function = "blsp_i2c8";
1425 drive-strength = <2>;
1426 bias-pull-up;
1427 };
1428
1429 /* BLSP2_I2C3 info is missing */
1430
1431 /* BLSP2_I2C4 info is missing */
1432
1433 blsp2_i2c5_default: blsp2-i2c5-default {
1434 pins = "gpio83", "gpio84";
1435 function = "blsp_i2c11";
1436 drive-strength = <2>;
1437 bias-disable;
1438 };
1439
1440 blsp2_i2c5_sleep: blsp2-i2c5-sleep {
1441 pins = "gpio83", "gpio84";
1442 function = "blsp_i2c11";
1443 drive-strength = <2>;
1444 bias-pull-up;
1445 };
1446
1447 blsp2_i2c6_default: blsp2-i2c6-default {
1448 pins = "gpio87", "gpio88";
1449 function = "blsp_i2c12";
1450 drive-strength = <2>;
1451 bias-disable;
1452 };
1453
1454 blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1455 pins = "gpio87", "gpio88";
1456 function = "blsp_i2c12";
1457 drive-strength = <2>;
1458 bias-pull-up;
1459 };
1460
1461 spi8_default: spi8_default {
1462 mosi {
1463 pins = "gpio45";
1464 function = "blsp_spi8";
1465 };
1466 miso {
1467 pins = "gpio46";
1468 function = "blsp_spi8";
1469 };
1470 cs {
1471 pins = "gpio47";
1472 function = "blsp_spi8";
1473 };
1474 clk {
1475 pins = "gpio48";
1476 function = "blsp_spi8";
1477 };
1478 };
1479 };
1480
1481 mmcc: clock-controller@fd8c0000 {
1482 compatible = "qcom,mmcc-msm8974";
1483 #clock-cells = <1>;
1484 #reset-cells = <1>;
1485 #power-domain-cells = <1>;
1486 reg = <0xfd8c0000 0x6000>;
1487 };
1488
1489 mdss: mdss@fd900000 {
1490 compatible = "qcom,mdss";
1491 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
1492 reg-names = "mdss_phys", "vbif_phys";
1493
1494 power-domains = <&mmcc MDSS_GDSC>;
1495
1496 clocks = <&mmcc MDSS_AHB_CLK>,
1497 <&mmcc MDSS_AXI_CLK>,
1498 <&mmcc MDSS_VSYNC_CLK>;
1499 clock-names = "iface", "bus", "vsync";
1500
1501 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1502
1503 interrupt-controller;
1504 #interrupt-cells = <1>;
1505
1506 status = "disabled";
1507
1508 #address-cells = <1>;
1509 #size-cells = <1>;
1510 ranges;
1511
1512 mdp: mdp@fd900000 {
1513 compatible = "qcom,mdp5";
1514 reg = <0xfd900100 0x22000>;
1515 reg-names = "mdp_phys";
1516
1517 interrupt-parent = <&mdss>;
1518 interrupts = <0>;
1519
1520 clocks = <&mmcc MDSS_AHB_CLK>,
1521 <&mmcc MDSS_AXI_CLK>,
1522 <&mmcc MDSS_MDP_CLK>,
1523 <&mmcc MDSS_VSYNC_CLK>;
1524 clock-names = "iface", "bus", "core", "vsync";
1525
1526 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
1527 interconnect-names = "mdp0-mem";
1528
1529 ports {
1530 #address-cells = <1>;
1531 #size-cells = <0>;
1532
1533 port@0 {
1534 reg = <0>;
1535 mdp5_intf1_out: endpoint {
1536 remote-endpoint = <&dsi0_in>;
1537 };
1538 };
1539 };
1540 };
1541
1542 dsi0: dsi@fd922800 {
1543 compatible = "qcom,mdss-dsi-ctrl";
1544 reg = <0xfd922800 0x1f8>;
1545 reg-names = "dsi_ctrl";
1546
1547 interrupt-parent = <&mdss>;
1548 interrupts = <4>;
1549
1550 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1551 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
1552
1553 clocks = <&mmcc MDSS_MDP_CLK>,
1554 <&mmcc MDSS_AHB_CLK>,
1555 <&mmcc MDSS_AXI_CLK>,
1556 <&mmcc MDSS_BYTE0_CLK>,
1557 <&mmcc MDSS_PCLK0_CLK>,
1558 <&mmcc MDSS_ESC0_CLK>,
1559 <&mmcc MMSS_MISC_AHB_CLK>;
1560 clock-names = "mdp_core",
1561 "iface",
1562 "bus",
1563 "byte",
1564 "pixel",
1565 "core",
1566 "core_mmss";
1567
1568 phys = <&dsi0_phy>;
1569 phy-names = "dsi-phy";
1570
1571 status = "disabled";
1572
1573 #address-cells = <1>;
1574 #size-cells = <0>;
1575
1576 ports {
1577 #address-cells = <1>;
1578 #size-cells = <0>;
1579
1580 port@0 {
1581 reg = <0>;
1582 dsi0_in: endpoint {
1583 remote-endpoint = <&mdp5_intf1_out>;
1584 };
1585 };
1586
1587 port@1 {
1588 reg = <1>;
1589 dsi0_out: endpoint {
1590 };
1591 };
1592 };
1593 };
1594
1595 dsi0_phy: dsi-phy@fd922a00 {
1596 compatible = "qcom,dsi-phy-28nm-hpm";
1597 reg = <0xfd922a00 0xd4>,
1598 <0xfd922b00 0x280>,
1599 <0xfd922d80 0x30>;
1600 reg-names = "dsi_pll",
1601 "dsi_phy",
1602 "dsi_phy_regulator";
1603
1604 #clock-cells = <1>;
1605 #phy-cells = <0>;
1606
1607 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1608 clock-names = "iface", "ref";
1609
1610 status = "disabled";
1611 };
1612 };
1613
1614 gpu: adreno@fdb00000 {
1615 compatible = "qcom,adreno-330.1", "qcom,adreno";
1616 reg = <0xfdb00000 0x10000>;
1617 reg-names = "kgsl_3d0_reg_memory";
1618
1619 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1620 interrupt-names = "kgsl_3d0_irq";
1621
1622 clocks = <&mmcc OXILI_GFX3D_CLK>,
1623 <&mmcc OXILICX_AHB_CLK>,
1624 <&mmcc OXILICX_AXI_CLK>;
1625 clock-names = "core", "iface", "mem_iface";
1626
1627 sram = <&gmu_sram>;
1628 power-domains = <&mmcc OXILICX_GDSC>;
1629 operating-points-v2 = <&gpu_opp_table>;
1630
1631 interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
1632 <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
1633 interconnect-names = "gfx-mem", "ocmem";
1634
1635 // iommus = <&gpu_iommu 0>;
1636
1637 status = "disabled";
1638
1639 gpu_opp_table: opp-table {
1640 compatible = "operating-points-v2";
1641
1642 opp-320000000 {
1643 opp-hz = /bits/ 64 <320000000>;
1644 };
1645
1646 opp-200000000 {
1647 opp-hz = /bits/ 64 <200000000>;
1648 };
1649
1650 opp-27000000 {
1651 opp-hz = /bits/ 64 <27000000>;
1652 };
1653 };
1654 };
1655
1656 sram@fdd00000 {
1657 compatible = "qcom,msm8974-ocmem";
1658 reg = <0xfdd00000 0x2000>,
1659 <0xfec00000 0x180000>;
1660 reg-names = "ctrl", "mem";
1661 ranges = <0 0xfec00000 0x180000>;
1662 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1663 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
1664 clock-names = "core", "iface";
1665
1666 #address-cells = <1>;
1667 #size-cells = <1>;
1668
1669 gmu_sram: gmu-sram@0 {
1670 reg = <0x0 0x100000>;
1671 };
1672 };
1673
1674 remoteproc_adsp: remoteproc@fe200000 {
1675 compatible = "qcom,msm8974-adsp-pil";
1676 reg = <0xfe200000 0x100>;
1677
1678 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
1679 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1680 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1681 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1682 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1683 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1684
1685 clocks = <&xo_board>;
1686 clock-names = "xo";
1687
1688 memory-region = <&adsp_region>;
1689
1690 qcom,smem-states = <&adsp_smp2p_out 0>;
1691 qcom,smem-state-names = "stop";
1692
1693 status = "disabled";
1694
1695 smd-edge {
1696 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1697
1698 qcom,ipc = <&apcs 8 8>;
1699 qcom,smd-edge = <1>;
1700 label = "lpass";
1701 #address-cells = <1>;
1702 #size-cells = <0>;
1703 };
1704 };
1705
1706 imem: sram@fe805000 {
1707 compatible = "qcom,msm8974-imem", "syscon", "simple-mfd";
1708 reg = <0xfe805000 0x1000>;
1709
1710 reboot-mode {
1711 compatible = "syscon-reboot-mode";
1712 offset = <0x65c>;
1713 };
1714 };
1715 };
1716
1717 tcsr_mutex: tcsr-mutex {
1718 compatible = "qcom,tcsr-mutex";
1719 syscon = <&tcsr_mutex_block 0 0x80>;
1720
1721 #hwlock-cells = <1>;
1722 };
1723
1724 thermal-zones {
1725 cpu0-thermal {
1726 polling-delay-passive = <250>;
1727 polling-delay = <1000>;
1728
1729 thermal-sensors = <&tsens 5>;
1730
1731 trips {
1732 cpu_alert0: trip0 {
1733 temperature = <75000>;
1734 hysteresis = <2000>;
1735 type = "passive";
1736 };
1737 cpu_crit0: trip1 {
1738 temperature = <110000>;
1739 hysteresis = <2000>;
1740 type = "critical";
1741 };
1742 };
1743 };
1744
1745 cpu1-thermal {
1746 polling-delay-passive = <250>;
1747 polling-delay = <1000>;
1748
1749 thermal-sensors = <&tsens 6>;
1750
1751 trips {
1752 cpu_alert1: trip0 {
1753 temperature = <75000>;
1754 hysteresis = <2000>;
1755 type = "passive";
1756 };
1757 cpu_crit1: trip1 {
1758 temperature = <110000>;
1759 hysteresis = <2000>;
1760 type = "critical";
1761 };
1762 };
1763 };
1764
1765 cpu2-thermal {
1766 polling-delay-passive = <250>;
1767 polling-delay = <1000>;
1768
1769 thermal-sensors = <&tsens 7>;
1770
1771 trips {
1772 cpu_alert2: trip0 {
1773 temperature = <75000>;
1774 hysteresis = <2000>;
1775 type = "passive";
1776 };
1777 cpu_crit2: trip1 {
1778 temperature = <110000>;
1779 hysteresis = <2000>;
1780 type = "critical";
1781 };
1782 };
1783 };
1784
1785 cpu3-thermal {
1786 polling-delay-passive = <250>;
1787 polling-delay = <1000>;
1788
1789 thermal-sensors = <&tsens 8>;
1790
1791 trips {
1792 cpu_alert3: trip0 {
1793 temperature = <75000>;
1794 hysteresis = <2000>;
1795 type = "passive";
1796 };
1797 cpu_crit3: trip1 {
1798 temperature = <110000>;
1799 hysteresis = <2000>;
1800 type = "critical";
1801 };
1802 };
1803 };
1804
1805 q6-dsp-thermal {
1806 polling-delay-passive = <250>;
1807 polling-delay = <1000>;
1808
1809 thermal-sensors = <&tsens 1>;
1810
1811 trips {
1812 q6_dsp_alert0: trip-point0 {
1813 temperature = <90000>;
1814 hysteresis = <2000>;
1815 type = "hot";
1816 };
1817 };
1818 };
1819
1820 modemtx-thermal {
1821 polling-delay-passive = <250>;
1822 polling-delay = <1000>;
1823
1824 thermal-sensors = <&tsens 2>;
1825
1826 trips {
1827 modemtx_alert0: trip-point0 {
1828 temperature = <90000>;
1829 hysteresis = <2000>;
1830 type = "hot";
1831 };
1832 };
1833 };
1834
1835 video-thermal {
1836 polling-delay-passive = <250>;
1837 polling-delay = <1000>;
1838
1839 thermal-sensors = <&tsens 3>;
1840
1841 trips {
1842 video_alert0: trip-point0 {
1843 temperature = <95000>;
1844 hysteresis = <2000>;
1845 type = "hot";
1846 };
1847 };
1848 };
1849
1850 wlan-thermal {
1851 polling-delay-passive = <250>;
1852 polling-delay = <1000>;
1853
1854 thermal-sensors = <&tsens 4>;
1855
1856 trips {
1857 wlan_alert0: trip-point0 {
1858 temperature = <105000>;
1859 hysteresis = <2000>;
1860 type = "hot";
1861 };
1862 };
1863 };
1864
1865 gpu-top-thermal {
1866 polling-delay-passive = <250>;
1867 polling-delay = <1000>;
1868
1869 thermal-sensors = <&tsens 9>;
1870
1871 trips {
1872 gpu1_alert0: trip-point0 {
1873 temperature = <90000>;
1874 hysteresis = <2000>;
1875 type = "hot";
1876 };
1877 };
1878 };
1879
1880 gpu-bottom-thermal {
1881 polling-delay-passive = <250>;
1882 polling-delay = <1000>;
1883
1884 thermal-sensors = <&tsens 10>;
1885
1886 trips {
1887 gpu2_alert0: trip-point0 {
1888 temperature = <90000>;
1889 hysteresis = <2000>;
1890 type = "hot";
1891 };
1892 };
1893 };
1894 };
1895
1896 timer {
1897 compatible = "arm,armv7-timer";
1898 interrupts = <GIC_PPI 2 0xf08>,
1899 <GIC_PPI 3 0xf08>,
1900 <GIC_PPI 4 0xf08>,
1901 <GIC_PPI 1 0xf08>;
1902 clock-frequency = <19200000>;
1903 };
1904
1905 vreg_boost: vreg-boost {
1906 compatible = "regulator-fixed";
1907
1908 regulator-name = "vreg-boost";
1909 regulator-min-microvolt = <3150000>;
1910 regulator-max-microvolt = <3150000>;
1911
1912 regulator-always-on;
1913 regulator-boot-on;
1914
1915 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
1916 enable-active-high;
1917
1918 pinctrl-names = "default";
1919 pinctrl-0 = <&boost_bypass_n_pin>;
1920 };
1921
1922 vreg_vph_pwr: vreg-vph-pwr {
1923 compatible = "regulator-fixed";
1924 regulator-name = "vph-pwr";
1925
1926 regulator-min-microvolt = <3600000>;
1927 regulator-max-microvolt = <3600000>;
1928
1929 regulator-always-on;
1930 };
1931 };
