0001 // SPDX-License-Identifier: GPL-2.0
0002 /dts-v1/;
0003
0004 #include <dt-bindings/interrupt-controller/arm-gic.h>
0005 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
0006 #include <dt-bindings/mfd/qcom-rpm.h>
0007 #include <dt-bindings/soc/qcom,gsbi.h>
0008
0009 / {
0010 #address-cells = <1>;
0011 #size-cells = <1>;
0012 model = "Qualcomm MSM8960";
0013 compatible = "qcom,msm8960";
0014 interrupt-parent = <&intc>;
0015
0016 cpus {
0017 #address-cells = <1>;
0018 #size-cells = <0>;
0019 interrupts = <1 14 0x304>;
0020
0021 cpu@0 {
0022 compatible = "qcom,krait";
0023 enable-method = "qcom,kpss-acc-v1";
0024 device_type = "cpu";
0025 reg = <0>;
0026 next-level-cache = <&L2>;
0027 qcom,acc = <&acc0>;
0028 qcom,saw = <&saw0>;
0029 };
0030
0031 cpu@1 {
0032 compatible = "qcom,krait";
0033 enable-method = "qcom,kpss-acc-v1";
0034 device_type = "cpu";
0035 reg = <1>;
0036 next-level-cache = <&L2>;
0037 qcom,acc = <&acc1>;
0038 qcom,saw = <&saw1>;
0039 };
0040
0041 L2: l2-cache {
0042 compatible = "cache";
0043 cache-level = <2>;
0044 };
0045 };
0046
0047 memory {
0048 device_type = "memory";
0049 reg = <0x0 0x0>;
0050 };
0051
0052 cpu-pmu {
0053 compatible = "qcom,krait-pmu";
0054 interrupts = <1 10 0x304>;
0055 qcom,no-pc-write;
0056 };
0057
0058 clocks {
0059 cxo_board {
0060 compatible = "fixed-clock";
0061 #clock-cells = <0>;
0062 clock-frequency = <19200000>;
0063 clock-output-names = "cxo_board";
0064 };
0065
0066 pxo_board {
0067 compatible = "fixed-clock";
0068 #clock-cells = <0>;
0069 clock-frequency = <27000000>;
0070 clock-output-names = "pxo_board";
0071 };
0072
0073 sleep_clk {
0074 compatible = "fixed-clock";
0075 #clock-cells = <0>;
0076 clock-frequency = <32768>;
0077 clock-output-names = "sleep_clk";
0078 };
0079 };
0080
0081 /* Temporary fixed regulator */
0082 vsdcc_fixed: vsdcc-regulator {
0083 compatible = "regulator-fixed";
0084 regulator-name = "SDCC Power";
0085 regulator-min-microvolt = <2700000>;
0086 regulator-max-microvolt = <2700000>;
0087 regulator-always-on;
0088 };
0089
0090 soc: soc {
0091 #address-cells = <1>;
0092 #size-cells = <1>;
0093 ranges;
0094 compatible = "simple-bus";
0095
0096 intc: interrupt-controller@2000000 {
0097 compatible = "qcom,msm-qgic2";
0098 interrupt-controller;
0099 #interrupt-cells = <3>;
0100 reg = <0x02000000 0x1000>,
0101 <0x02002000 0x1000>;
0102 };
0103
0104 timer@200a000 {
0105 compatible = "qcom,kpss-timer",
0106 "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
0107 interrupts = <1 1 0x301>,
0108 <1 2 0x301>,
0109 <1 3 0x301>;
0110 reg = <0x0200a000 0x100>;
0111 clock-frequency = <27000000>,
0112 <32768>;
0113 cpu-offset = <0x80000>;
0114 };
0115
0116 msmgpio: pinctrl@800000 {
0117 compatible = "qcom,msm8960-pinctrl";
0118 gpio-controller;
0119 gpio-ranges = <&msmgpio 0 0 152>;
0120 #gpio-cells = <2>;
0121 interrupts = <0 16 0x4>;
0122 interrupt-controller;
0123 #interrupt-cells = <2>;
0124 reg = <0x800000 0x4000>;
0125 };
0126
0127 gcc: clock-controller@900000 {
0128 compatible = "qcom,gcc-msm8960";
0129 #clock-cells = <1>;
0130 #power-domain-cells = <1>;
0131 #reset-cells = <1>;
0132 reg = <0x900000 0x4000>;
0133 };
0134
0135 lcc: clock-controller@28000000 {
0136 compatible = "qcom,lcc-msm8960";
0137 reg = <0x28000000 0x1000>;
0138 #clock-cells = <1>;
0139 #reset-cells = <1>;
0140 };
0141
0142 clock-controller@4000000 {
0143 compatible = "qcom,mmcc-msm8960";
0144 reg = <0x4000000 0x1000>;
0145 #clock-cells = <1>;
0146 #power-domain-cells = <1>;
0147 #reset-cells = <1>;
0148 };
0149
0150 l2cc: clock-controller@2011000 {
0151 compatible = "qcom,kpss-gcc", "syscon";
0152 reg = <0x2011000 0x1000>;
0153 };
0154
0155 rpm@108000 {
0156 compatible = "qcom,rpm-msm8960";
0157 reg = <0x108000 0x1000>;
0158 qcom,ipc = <&l2cc 0x8 2>;
0159
0160 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
0161 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
0162 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
0163 interrupt-names = "ack", "err", "wakeup";
0164
0165 regulators {
0166 compatible = "qcom,rpm-pm8921-regulators";
0167 };
0168 };
0169
0170 acc0: clock-controller@2088000 {
0171 compatible = "qcom,kpss-acc-v1";
0172 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
0173 };
0174
0175 acc1: clock-controller@2098000 {
0176 compatible = "qcom,kpss-acc-v1";
0177 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
0178 };
0179
0180 saw0: regulator@2089000 {
0181 compatible = "qcom,saw2";
0182 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
0183 regulator;
0184 };
0185
0186 saw1: regulator@2099000 {
0187 compatible = "qcom,saw2";
0188 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
0189 regulator;
0190 };
0191
0192 gsbi5: gsbi@16400000 {
0193 compatible = "qcom,gsbi-v1.0.0";
0194 cell-index = <5>;
0195 reg = <0x16400000 0x100>;
0196 clocks = <&gcc GSBI5_H_CLK>;
0197 clock-names = "iface";
0198 #address-cells = <1>;
0199 #size-cells = <1>;
0200 ranges;
0201
0202 syscon-tcsr = <&tcsr>;
0203
0204 gsbi5_serial: serial@16440000 {
0205 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
0206 reg = <0x16440000 0x1000>,
0207 <0x16400000 0x1000>;
0208 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
0209 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
0210 clock-names = "core", "iface";
0211 status = "disabled";
0212 };
0213 };
0214
0215 qcom,ssbi@500000 {
0216 compatible = "qcom,ssbi";
0217 reg = <0x500000 0x1000>;
0218 qcom,controller-type = "pmic-arbiter";
0219
0220 pmicintc: pmic@0 {
0221 compatible = "qcom,pm8921";
0222 interrupt-parent = <&msmgpio>;
0223 interrupts = <104 8>;
0224 #interrupt-cells = <2>;
0225 interrupt-controller;
0226 #address-cells = <1>;
0227 #size-cells = <0>;
0228
0229 pwrkey@1c {
0230 compatible = "qcom,pm8921-pwrkey";
0231 reg = <0x1c>;
0232 interrupt-parent = <&pmicintc>;
0233 interrupts = <50 1>, <51 1>;
0234 debounce = <15625>;
0235 pull-up;
0236 };
0237
0238 keypad@148 {
0239 compatible = "qcom,pm8921-keypad";
0240 reg = <0x148>;
0241 interrupt-parent = <&pmicintc>;
0242 interrupts = <74 1>, <75 1>;
0243 debounce = <15>;
0244 scan-delay = <32>;
0245 row-hold = <91500>;
0246 };
0247
0248 rtc@11d {
0249 compatible = "qcom,pm8921-rtc";
0250 interrupt-parent = <&pmicintc>;
0251 interrupts = <39 1>;
0252 reg = <0x11d>;
0253 allow-set-time;
0254 };
0255 };
0256 };
0257
0258 rng@1a500000 {
0259 compatible = "qcom,prng";
0260 reg = <0x1a500000 0x200>;
0261 clocks = <&gcc PRNG_CLK>;
0262 clock-names = "core";
0263 };
0264
0265 amba {
0266 compatible = "simple-bus";
0267 #address-cells = <1>;
0268 #size-cells = <1>;
0269 ranges;
0270 sdcc1: mmc@12400000 {
0271 status = "disabled";
0272 compatible = "arm,pl18x", "arm,primecell";
0273 arm,primecell-periphid = <0x00051180>;
0274 reg = <0x12400000 0x8000>;
0275 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
0276 interrupt-names = "cmd_irq";
0277 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
0278 clock-names = "mclk", "apb_pclk";
0279 bus-width = <8>;
0280 max-frequency = <96000000>;
0281 non-removable;
0282 cap-sd-highspeed;
0283 cap-mmc-highspeed;
0284 vmmc-supply = <&vsdcc_fixed>;
0285 };
0286
0287 sdcc3: mmc@12180000 {
0288 compatible = "arm,pl18x", "arm,primecell";
0289 arm,primecell-periphid = <0x00051180>;
0290 status = "disabled";
0291 reg = <0x12180000 0x8000>;
0292 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
0293 interrupt-names = "cmd_irq";
0294 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
0295 clock-names = "mclk", "apb_pclk";
0296 bus-width = <4>;
0297 cap-sd-highspeed;
0298 cap-mmc-highspeed;
0299 max-frequency = <192000000>;
0300 no-1-8-v;
0301 vmmc-supply = <&vsdcc_fixed>;
0302 };
0303 };
0304
0305 tcsr: syscon@1a400000 {
0306 compatible = "qcom,tcsr-msm8960", "syscon";
0307 reg = <0x1a400000 0x100>;
0308 };
0309
0310 gsbi@16000000 {
0311 compatible = "qcom,gsbi-v1.0.0";
0312 cell-index = <1>;
0313 reg = <0x16000000 0x100>;
0314 clocks = <&gcc GSBI1_H_CLK>;
0315 clock-names = "iface";
0316 #address-cells = <1>;
0317 #size-cells = <1>;
0318 ranges;
0319
0320 spi@16080000 {
0321 compatible = "qcom,spi-qup-v1.1.1";
0322 #address-cells = <1>;
0323 #size-cells = <0>;
0324 reg = <0x16080000 0x1000>;
0325 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
0326 spi-max-frequency = <24000000>;
0327 cs-gpios = <&msmgpio 8 0>;
0328
0329 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
0330 clock-names = "core", "iface";
0331 status = "disabled";
0332 };
0333 };
0334 };
0335 };
