0001 // SPDX-License-Identifier: BSD-3-Clause
0002 /*
0003 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
0004 */
0005
0006 /dts-v1/;
0007
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
0010 #include <dt-bindings/gpio/gpio.h>
0011 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
0012
0013 / {
0014 #address-cells = <1>;
0015 #size-cells = <1>;
0016 interrupt-parent = <&intc>;
0017
0018 chosen { };
0019
0020 memory@0 {
0021 device_type = "memory";
0022 reg = <0x0 0x0>;
0023 };
0024
0025 clocks {
0026 xo_board: xo_board {
0027 compatible = "fixed-clock";
0028 #clock-cells = <0>;
0029 clock-frequency = <19200000>;
0030 };
0031
0032 sleep_clk: sleep_clk {
0033 compatible = "fixed-clock";
0034 #clock-cells = <0>;
0035 clock-frequency = <32768>;
0036 };
0037 };
0038
0039 firmware {
0040 scm {
0041 compatible = "qcom,scm-msm8226", "qcom,scm";
0042 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
0043 clock-names = "core", "bus", "iface";
0044 };
0045 };
0046
0047 tcsr_mutex: hwlock {
0048 compatible = "qcom,tcsr-mutex";
0049 syscon = <&tcsr_mutex_block 0 0x80>;
0050
0051 #hwlock-cells = <1>;
0052 };
0053
0054 reserved-memory {
0055 #address-cells = <1>;
0056 #size-cells = <1>;
0057 ranges;
0058
0059 smem_region: smem@3000000 {
0060 reg = <0x3000000 0x100000>;
0061 no-map;
0062 };
0063 };
0064
0065 smd {
0066 compatible = "qcom,smd";
0067
0068 rpm {
0069 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
0070 qcom,ipc = <&apcs 8 0>;
0071 qcom,smd-edge = <15>;
0072
0073 rpm_requests: rpm-requests {
0074 compatible = "qcom,rpm-msm8226";
0075 qcom,smd-channels = "rpm_requests";
0076
0077 rpmpd: power-controller {
0078 compatible = "qcom,msm8226-rpmpd";
0079 #power-domain-cells = <1>;
0080 operating-points-v2 = <&rpmpd_opp_table>;
0081
0082 rpmpd_opp_table: opp-table {
0083 compatible = "operating-points-v2";
0084
0085 rpmpd_opp_ret: opp1 {
0086 opp-level = <1>;
0087 };
0088 rpmpd_opp_svs_krait: opp2 {
0089 opp-level = <2>;
0090 };
0091 rpmpd_opp_svs_soc: opp3 {
0092 opp-level = <3>;
0093 };
0094 rpmpd_opp_nom: opp4 {
0095 opp-level = <4>;
0096 };
0097 rpmpd_opp_turbo: opp5 {
0098 opp-level = <5>;
0099 };
0100 rpmpd_opp_super_turbo: opp6 {
0101 opp-level = <6>;
0102 };
0103 };
0104 };
0105 };
0106 };
0107 };
0108
0109 smem {
0110 compatible = "qcom,smem";
0111
0112 memory-region = <&smem_region>;
0113 qcom,rpm-msg-ram = <&rpm_msg_ram>;
0114
0115 hwlocks = <&tcsr_mutex 3>;
0116 };
0117
0118 soc: soc {
0119 compatible = "simple-bus";
0120 #address-cells = <1>;
0121 #size-cells = <1>;
0122 ranges;
0123
0124 intc: interrupt-controller@f9000000 {
0125 compatible = "qcom,msm-qgic2";
0126 reg = <0xf9000000 0x1000>,
0127 <0xf9002000 0x1000>;
0128 interrupt-controller;
0129 #interrupt-cells = <3>;
0130 };
0131
0132 apcs: syscon@f9011000 {
0133 compatible = "syscon";
0134 reg = <0xf9011000 0x1000>;
0135 };
0136
0137 sdhc_1: mmc@f9824900 {
0138 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
0139 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
0140 reg-names = "hc_mem", "core_mem";
0141 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
0142 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
0143 interrupt-names = "hc_irq", "pwr_irq";
0144 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
0145 <&gcc GCC_SDCC1_AHB_CLK>,
0146 <&xo_board>;
0147 clock-names = "core", "iface", "xo";
0148 pinctrl-names = "default";
0149 pinctrl-0 = <&sdhc1_default_state>;
0150 status = "disabled";
0151 };
0152
0153 sdhc_2: mmc@f98a4900 {
0154 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
0155 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
0156 reg-names = "hc_mem", "core_mem";
0157 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
0158 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
0159 interrupt-names = "hc_irq", "pwr_irq";
0160 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
0161 <&gcc GCC_SDCC2_AHB_CLK>,
0162 <&xo_board>;
0163 clock-names = "core", "iface", "xo";
0164 pinctrl-names = "default";
0165 pinctrl-0 = <&sdhc2_default_state>;
0166 status = "disabled";
0167 };
0168
0169 sdhc_3: mmc@f9864900 {
0170 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
0171 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
0172 reg-names = "hc_mem", "core_mem";
0173 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
0174 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
0175 interrupt-names = "hc_irq", "pwr_irq";
0176 clocks = <&gcc GCC_SDCC3_APPS_CLK>,
0177 <&gcc GCC_SDCC3_AHB_CLK>,
0178 <&xo_board>;
0179 clock-names = "core", "iface", "xo";
0180 pinctrl-names = "default";
0181 pinctrl-0 = <&sdhc3_default_state>;
0182 status = "disabled";
0183 };
0184
0185 blsp1_uart1: serial@f991d000 {
0186 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0187 reg = <0xf991d000 0x1000>;
0188 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0189 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0190 clock-names = "core", "iface";
0191 status = "disabled";
0192 };
0193
0194 blsp1_uart3: serial@f991f000 {
0195 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0196 reg = <0xf991f000 0x1000>;
0197 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
0198 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0199 clock-names = "core", "iface";
0200 status = "disabled";
0201 };
0202
0203 blsp1_uart4: serial@f9920000 {
0204 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0205 reg = <0xf9920000 0x1000>;
0206 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0207 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0208 clock-names = "core", "iface";
0209 status = "disabled";
0210 };
0211
0212 blsp1_i2c1: i2c@f9923000 {
0213 status = "disabled";
0214 compatible = "qcom,i2c-qup-v2.1.1";
0215 reg = <0xf9923000 0x1000>;
0216 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0217 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0218 clock-names = "core", "iface";
0219 pinctrl-names = "default";
0220 pinctrl-0 = <&blsp1_i2c1_pins>;
0221 #address-cells = <1>;
0222 #size-cells = <0>;
0223 };
0224
0225 blsp1_i2c2: i2c@f9924000 {
0226 status = "disabled";
0227 compatible = "qcom,i2c-qup-v2.1.1";
0228 reg = <0xf9924000 0x1000>;
0229 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0230 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0231 clock-names = "core", "iface";
0232 pinctrl-names = "default";
0233 pinctrl-0 = <&blsp1_i2c2_pins>;
0234 #address-cells = <1>;
0235 #size-cells = <0>;
0236 };
0237
0238 blsp1_i2c3: i2c@f9925000 {
0239 status = "disabled";
0240 compatible = "qcom,i2c-qup-v2.1.1";
0241 reg = <0xf9925000 0x1000>;
0242 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0243 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0244 clock-names = "core", "iface";
0245 pinctrl-names = "default";
0246 pinctrl-0 = <&blsp1_i2c3_pins>;
0247 #address-cells = <1>;
0248 #size-cells = <0>;
0249 };
0250
0251 blsp1_i2c4: i2c@f9926000 {
0252 status = "disabled";
0253 compatible = "qcom,i2c-qup-v2.1.1";
0254 reg = <0xf9926000 0x1000>;
0255 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0256 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0257 clock-names = "core", "iface";
0258 pinctrl-names = "default";
0259 pinctrl-0 = <&blsp1_i2c4_pins>;
0260 #address-cells = <1>;
0261 #size-cells = <0>;
0262 };
0263
0264 blsp1_i2c5: i2c@f9927000 {
0265 status = "disabled";
0266 compatible = "qcom,i2c-qup-v2.1.1";
0267 reg = <0xf9927000 0x1000>;
0268 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0269 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0270 clock-names = "core", "iface";
0271 pinctrl-names = "default";
0272 pinctrl-0 = <&blsp1_i2c5_pins>;
0273 #address-cells = <1>;
0274 #size-cells = <0>;
0275 };
0276
0277 usb: usb@f9a55000 {
0278 compatible = "qcom,ci-hdrc";
0279 reg = <0xf9a55000 0x200>,
0280 <0xf9a55200 0x200>;
0281 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
0282 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
0283 <&gcc GCC_USB_HS_SYSTEM_CLK>;
0284 clock-names = "iface", "core";
0285 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
0286 assigned-clock-rates = <75000000>;
0287 resets = <&gcc GCC_USB_HS_BCR>;
0288 reset-names = "core";
0289 phy_type = "ulpi";
0290 dr_mode = "otg";
0291 hnp-disable;
0292 srp-disable;
0293 adp-disable;
0294 ahb-burst-config = <0>;
0295 phy-names = "usb-phy";
0296 phys = <&usb_hs_phy>;
0297 status = "disabled";
0298 #reset-cells = <1>;
0299
0300 ulpi {
0301 usb_hs_phy: phy {
0302 compatible = "qcom,usb-hs-phy-msm8226",
0303 "qcom,usb-hs-phy";
0304 #phy-cells = <0>;
0305 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
0306 clock-names = "ref", "sleep";
0307 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
0308 reset-names = "phy", "por";
0309 qcom,init-seq = /bits/ 8 <0x0 0x44
0310 0x1 0x68 0x2 0x24 0x3 0x13>;
0311 };
0312 };
0313 };
0314
0315 gcc: clock-controller@fc400000 {
0316 compatible = "qcom,gcc-msm8226";
0317 reg = <0xfc400000 0x4000>;
0318 #clock-cells = <1>;
0319 #reset-cells = <1>;
0320 #power-domain-cells = <1>;
0321 };
0322
0323 tlmm: pinctrl@fd510000 {
0324 compatible = "qcom,msm8226-pinctrl";
0325 reg = <0xfd510000 0x4000>;
0326 gpio-controller;
0327 #gpio-cells = <2>;
0328 gpio-ranges = <&tlmm 0 0 117>;
0329 interrupt-controller;
0330 #interrupt-cells = <2>;
0331 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
0332
0333 blsp1_i2c1_pins: blsp1-i2c1 {
0334 pins = "gpio2", "gpio3";
0335 function = "blsp_i2c1";
0336 drive-strength = <2>;
0337 bias-disable;
0338 };
0339
0340 blsp1_i2c2_pins: blsp1-i2c2 {
0341 pins = "gpio6", "gpio7";
0342 function = "blsp_i2c2";
0343 drive-strength = <2>;
0344 bias-disable;
0345 };
0346
0347 blsp1_i2c3_pins: blsp1-i2c3 {
0348 pins = "gpio10", "gpio11";
0349 function = "blsp_i2c3";
0350 drive-strength = <2>;
0351 bias-disable;
0352 };
0353
0354 blsp1_i2c4_pins: blsp1-i2c4 {
0355 pins = "gpio14", "gpio15";
0356 function = "blsp_i2c4";
0357 drive-strength = <2>;
0358 bias-disable;
0359 };
0360
0361 blsp1_i2c5_pins: blsp1-i2c5 {
0362 pins = "gpio18", "gpio19";
0363 function = "blsp_i2c5";
0364 drive-strength = <2>;
0365 bias-disable;
0366 };
0367
0368 sdhc1_default_state: sdhc1-default-state {
0369 clk {
0370 pins = "sdc1_clk";
0371 drive-strength = <10>;
0372 bias-disable;
0373 };
0374
0375 cmd-data {
0376 pins = "sdc1_cmd", "sdc1_data";
0377 drive-strength = <10>;
0378 bias-pull-up;
0379 };
0380 };
0381
0382 sdhc2_default_state: sdhc2-default-state {
0383 clk {
0384 pins = "sdc2_clk";
0385 drive-strength = <10>;
0386 bias-disable;
0387 };
0388
0389 cmd-data {
0390 pins = "sdc2_cmd", "sdc2_data";
0391 drive-strength = <10>;
0392 bias-pull-up;
0393 };
0394 };
0395
0396 sdhc3_default_state: sdhc3-default-state {
0397 clk {
0398 pins = "gpio44";
0399 function = "sdc3";
0400 drive-strength = <8>;
0401 bias-disable;
0402 };
0403
0404 cmd {
0405 pins = "gpio43";
0406 function = "sdc3";
0407 drive-strength = <8>;
0408 bias-pull-up;
0409 };
0410
0411 data {
0412 pins = "gpio39", "gpio40", "gpio41", "gpio42";
0413 function = "sdc3";
0414 drive-strength = <8>;
0415 bias-pull-up;
0416 };
0417 };
0418 };
0419
0420 restart@fc4ab000 {
0421 compatible = "qcom,pshold";
0422 reg = <0xfc4ab000 0x4>;
0423 };
0424
0425 spmi_bus: spmi@fc4cf000 {
0426 compatible = "qcom,spmi-pmic-arb";
0427 reg-names = "core", "intr", "cnfg";
0428 reg = <0xfc4cf000 0x1000>,
0429 <0xfc4cb000 0x1000>,
0430 <0xfc4ca000 0x1000>;
0431 interrupt-names = "periph_irq";
0432 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
0433 qcom,ee = <0>;
0434 qcom,channel = <0>;
0435 #address-cells = <2>;
0436 #size-cells = <0>;
0437 interrupt-controller;
0438 #interrupt-cells = <4>;
0439 };
0440
0441 rng@f9bff000 {
0442 compatible = "qcom,prng";
0443 reg = <0xf9bff000 0x200>;
0444 clocks = <&gcc GCC_PRNG_AHB_CLK>;
0445 clock-names = "core";
0446 };
0447
0448 timer@f9020000 {
0449 compatible = "arm,armv7-timer-mem";
0450 reg = <0xf9020000 0x1000>;
0451 #address-cells = <1>;
0452 #size-cells = <1>;
0453 ranges;
0454
0455 frame@f9021000 {
0456 frame-number = <0>;
0457 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0458 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0459 reg = <0xf9021000 0x1000>,
0460 <0xf9022000 0x1000>;
0461 };
0462
0463 frame@f9023000 {
0464 frame-number = <1>;
0465 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0466 reg = <0xf9023000 0x1000>;
0467 status = "disabled";
0468 };
0469
0470 frame@f9024000 {
0471 frame-number = <2>;
0472 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0473 reg = <0xf9024000 0x1000>;
0474 status = "disabled";
0475 };
0476
0477 frame@f9025000 {
0478 frame-number = <3>;
0479 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0480 reg = <0xf9025000 0x1000>;
0481 status = "disabled";
0482 };
0483
0484 frame@f9026000 {
0485 frame-number = <4>;
0486 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0487 reg = <0xf9026000 0x1000>;
0488 status = "disabled";
0489 };
0490
0491 frame@f9027000 {
0492 frame-number = <5>;
0493 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0494 reg = <0xf9027000 0x1000>;
0495 status = "disabled";
0496 };
0497
0498 frame@f9028000 {
0499 frame-number = <6>;
0500 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0501 reg = <0xf9028000 0x1000>;
0502 status = "disabled";
0503 };
0504 };
0505
0506 rpm_msg_ram: memory@fc428000 {
0507 compatible = "qcom,rpm-msg-ram";
0508 reg = <0xfc428000 0x4000>;
0509 };
0510
0511 tcsr_mutex_block: syscon@fd484000 {
0512 compatible = "syscon";
0513 reg = <0xfd484000 0x2000>;
0514 };
0515 };
0516
0517 timer {
0518 compatible = "arm,armv7-timer";
0519 interrupts = <GIC_PPI 2
0520 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
0521 <GIC_PPI 3
0522 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
0523 <GIC_PPI 4
0524 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
0525 <GIC_PPI 1
0526 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
0527 };
0528 };
