0001 // SPDX-License-Identifier: GPL-2.0 OR MIT
0002 /*
0003 * Copyright 2015 Endless Mobile, Inc.
0004 * Author: Carlo Caione <carlo@endlessm.com>
0005 */
0006
0007 #include <dt-bindings/clock/meson8-ddr-clkc.h>
0008 #include <dt-bindings/clock/meson8b-clkc.h>
0009 #include <dt-bindings/gpio/meson8b-gpio.h>
0010 #include <dt-bindings/power/meson8-power.h>
0011 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
0012 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
0013 #include <dt-bindings/thermal/thermal.h>
0014 #include "meson.dtsi"
0015
0016 / {
0017 cpus {
0018 #address-cells = <1>;
0019 #size-cells = <0>;
0020
0021 cpu0: cpu@200 {
0022 device_type = "cpu";
0023 compatible = "arm,cortex-a5";
0024 next-level-cache = <&L2>;
0025 reg = <0x200>;
0026 enable-method = "amlogic,meson8b-smp";
0027 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
0028 operating-points-v2 = <&cpu_opp_table>;
0029 clocks = <&clkc CLKID_CPUCLK>;
0030 #cooling-cells = <2>; /* min followed by max */
0031 };
0032
0033 cpu1: cpu@201 {
0034 device_type = "cpu";
0035 compatible = "arm,cortex-a5";
0036 next-level-cache = <&L2>;
0037 reg = <0x201>;
0038 enable-method = "amlogic,meson8b-smp";
0039 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
0040 operating-points-v2 = <&cpu_opp_table>;
0041 clocks = <&clkc CLKID_CPUCLK>;
0042 #cooling-cells = <2>; /* min followed by max */
0043 };
0044
0045 cpu2: cpu@202 {
0046 device_type = "cpu";
0047 compatible = "arm,cortex-a5";
0048 next-level-cache = <&L2>;
0049 reg = <0x202>;
0050 enable-method = "amlogic,meson8b-smp";
0051 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
0052 operating-points-v2 = <&cpu_opp_table>;
0053 clocks = <&clkc CLKID_CPUCLK>;
0054 #cooling-cells = <2>; /* min followed by max */
0055 };
0056
0057 cpu3: cpu@203 {
0058 device_type = "cpu";
0059 compatible = "arm,cortex-a5";
0060 next-level-cache = <&L2>;
0061 reg = <0x203>;
0062 enable-method = "amlogic,meson8b-smp";
0063 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
0064 operating-points-v2 = <&cpu_opp_table>;
0065 clocks = <&clkc CLKID_CPUCLK>;
0066 #cooling-cells = <2>; /* min followed by max */
0067 };
0068 };
0069
0070 cpu_opp_table: opp-table {
0071 compatible = "operating-points-v2";
0072 opp-shared;
0073
0074 opp-96000000 {
0075 opp-hz = /bits/ 64 <96000000>;
0076 opp-microvolt = <860000>;
0077 };
0078 opp-192000000 {
0079 opp-hz = /bits/ 64 <192000000>;
0080 opp-microvolt = <860000>;
0081 };
0082 opp-312000000 {
0083 opp-hz = /bits/ 64 <312000000>;
0084 opp-microvolt = <860000>;
0085 };
0086 opp-408000000 {
0087 opp-hz = /bits/ 64 <408000000>;
0088 opp-microvolt = <860000>;
0089 };
0090 opp-504000000 {
0091 opp-hz = /bits/ 64 <504000000>;
0092 opp-microvolt = <860000>;
0093 };
0094 opp-600000000 {
0095 opp-hz = /bits/ 64 <600000000>;
0096 opp-microvolt = <860000>;
0097 };
0098 opp-720000000 {
0099 opp-hz = /bits/ 64 <720000000>;
0100 opp-microvolt = <860000>;
0101 };
0102 opp-816000000 {
0103 opp-hz = /bits/ 64 <816000000>;
0104 opp-microvolt = <900000>;
0105 };
0106 opp-1008000000 {
0107 opp-hz = /bits/ 64 <1008000000>;
0108 opp-microvolt = <1140000>;
0109 };
0110 opp-1200000000 {
0111 opp-hz = /bits/ 64 <1200000000>;
0112 opp-microvolt = <1140000>;
0113 };
0114 opp-1320000000 {
0115 opp-hz = /bits/ 64 <1320000000>;
0116 opp-microvolt = <1140000>;
0117 };
0118 opp-1488000000 {
0119 opp-hz = /bits/ 64 <1488000000>;
0120 opp-microvolt = <1140000>;
0121 };
0122 opp-1536000000 {
0123 opp-hz = /bits/ 64 <1536000000>;
0124 opp-microvolt = <1140000>;
0125 };
0126 };
0127
0128 gpu_opp_table: gpu-opp-table {
0129 compatible = "operating-points-v2";
0130
0131 opp-255000000 {
0132 opp-hz = /bits/ 64 <255000000>;
0133 opp-microvolt = <1100000>;
0134 };
0135 opp-364285714 {
0136 opp-hz = /bits/ 64 <364285714>;
0137 opp-microvolt = <1100000>;
0138 };
0139 opp-425000000 {
0140 opp-hz = /bits/ 64 <425000000>;
0141 opp-microvolt = <1100000>;
0142 };
0143 opp-510000000 {
0144 opp-hz = /bits/ 64 <510000000>;
0145 opp-microvolt = <1100000>;
0146 };
0147 opp-637500000 {
0148 opp-hz = /bits/ 64 <637500000>;
0149 opp-microvolt = <1100000>;
0150 turbo-mode;
0151 };
0152 };
0153
0154 pmu {
0155 compatible = "arm,cortex-a5-pmu";
0156 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
0157 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
0158 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
0159 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
0160 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0161 };
0162
0163 reserved-memory {
0164 #address-cells = <1>;
0165 #size-cells = <1>;
0166 ranges;
0167
0168 /* 2 MiB reserved for Hardware ROM Firmware? */
0169 hwrom@0 {
0170 reg = <0x0 0x200000>;
0171 no-map;
0172 };
0173 };
0174
0175 thermal-zones {
0176 soc {
0177 polling-delay-passive = <250>; /* milliseconds */
0178 polling-delay = <1000>; /* milliseconds */
0179 thermal-sensors = <&thermal_sensor>;
0180
0181 cooling-maps {
0182 map0 {
0183 trip = <&soc_passive>;
0184 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0185 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0186 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0187 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0188 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0189 };
0190
0191 map1 {
0192 trip = <&soc_hot>;
0193 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0194 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0195 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0196 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0197 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0198 };
0199 };
0200
0201 trips {
0202 soc_passive: soc-passive {
0203 temperature = <80000>; /* millicelsius */
0204 hysteresis = <2000>; /* millicelsius */
0205 type = "passive";
0206 };
0207
0208 soc_hot: soc-hot {
0209 temperature = <90000>; /* millicelsius */
0210 hysteresis = <2000>; /* millicelsius */
0211 type = "hot";
0212 };
0213
0214 soc_critical: soc-critical {
0215 temperature = <110000>; /* millicelsius */
0216 hysteresis = <2000>; /* millicelsius */
0217 type = "critical";
0218 };
0219 };
0220 };
0221 };
0222
0223 mmcbus: bus@c8000000 {
0224 compatible = "simple-bus";
0225 reg = <0xc8000000 0x8000>;
0226 #address-cells = <1>;
0227 #size-cells = <1>;
0228 ranges = <0x0 0xc8000000 0x8000>;
0229
0230 ddr_clkc: clock-controller@400 {
0231 compatible = "amlogic,meson8b-ddr-clkc";
0232 reg = <0x400 0x20>;
0233 clocks = <&xtal>;
0234 clock-names = "xtal";
0235 #clock-cells = <1>;
0236 };
0237
0238 dmcbus: bus@6000 {
0239 compatible = "simple-bus";
0240 reg = <0x6000 0x400>;
0241 #address-cells = <1>;
0242 #size-cells = <1>;
0243 ranges = <0x0 0x6000 0x400>;
0244
0245 canvas: video-lut@48 {
0246 compatible = "amlogic,meson8b-canvas",
0247 "amlogic,canvas";
0248 reg = <0x48 0x14>;
0249 };
0250 };
0251 };
0252
0253 apb: bus@d0000000 {
0254 compatible = "simple-bus";
0255 reg = <0xd0000000 0x200000>;
0256 #address-cells = <1>;
0257 #size-cells = <1>;
0258 ranges = <0x0 0xd0000000 0x200000>;
0259
0260 mali: gpu@c0000 {
0261 compatible = "amlogic,meson8b-mali", "arm,mali-450";
0262 reg = <0xc0000 0x40000>;
0263 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
0264 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
0265 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
0266 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
0267 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
0268 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
0269 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
0270 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
0271 interrupt-names = "gp", "gpmmu", "pp", "pmu",
0272 "pp0", "ppmmu0", "pp1", "ppmmu1";
0273 resets = <&reset RESET_MALI>;
0274 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
0275 clock-names = "bus", "core";
0276 operating-points-v2 = <&gpu_opp_table>;
0277 #cooling-cells = <2>; /* min followed by max */
0278 };
0279 };
0280 }; /* end of / */
0281
0282 &aiu {
0283 compatible = "amlogic,aiu-meson8b", "amlogic,aiu";
0284 clocks = <&clkc CLKID_AIU_GLUE>,
0285 <&clkc CLKID_I2S_OUT>,
0286 <&clkc CLKID_AOCLK_GATE>,
0287 <&clkc CLKID_CTS_AMCLK>,
0288 <&clkc CLKID_MIXER_IFACE>,
0289 <&clkc CLKID_IEC958>,
0290 <&clkc CLKID_IEC958_GATE>,
0291 <&clkc CLKID_CTS_MCLK_I958>,
0292 <&clkc CLKID_CTS_I958>;
0293 clock-names = "pclk",
0294 "i2s_pclk",
0295 "i2s_aoclk",
0296 "i2s_mclk",
0297 "i2s_mixer",
0298 "spdif_pclk",
0299 "spdif_aoclk",
0300 "spdif_mclk",
0301 "spdif_mclk_sel";
0302 resets = <&reset RESET_AIU>;
0303 };
0304
0305 &aobus {
0306 pmu: pmu@e0 {
0307 compatible = "amlogic,meson8b-pmu", "syscon";
0308 reg = <0xe0 0x18>;
0309 };
0310
0311 pinctrl_aobus: pinctrl@84 {
0312 compatible = "amlogic,meson8b-aobus-pinctrl";
0313 reg = <0x84 0xc>;
0314 #address-cells = <1>;
0315 #size-cells = <1>;
0316 ranges;
0317
0318 gpio_ao: ao-bank@14 {
0319 reg = <0x14 0x4>,
0320 <0x2c 0x4>,
0321 <0x24 0x8>;
0322 reg-names = "mux", "pull", "gpio";
0323 gpio-controller;
0324 #gpio-cells = <2>;
0325 gpio-ranges = <&pinctrl_aobus 0 0 16>;
0326 };
0327
0328 i2s_am_clk_pins: i2s-am-clk-out {
0329 mux {
0330 groups = "i2s_am_clk_out";
0331 function = "i2s";
0332 bias-disable;
0333 };
0334 };
0335
0336 i2s_out_ao_clk_pins: i2s-ao-clk-out {
0337 mux {
0338 groups = "i2s_ao_clk_out";
0339 function = "i2s";
0340 bias-disable;
0341 };
0342 };
0343
0344 i2s_out_lr_clk_pins: i2s-lr-clk-out {
0345 mux {
0346 groups = "i2s_lr_clk_out";
0347 function = "i2s";
0348 bias-disable;
0349 };
0350 };
0351
0352 i2s_out_ch01_ao_pins: i2s-out-ch01 {
0353 mux {
0354 groups = "i2s_out_01";
0355 function = "i2s";
0356 bias-disable;
0357 };
0358 };
0359
0360 spdif_out_1_pins: spdif-out-1 {
0361 mux {
0362 groups = "spdif_out_1";
0363 function = "spdif_1";
0364 bias-disable;
0365 };
0366 };
0367
0368 uart_ao_a_pins: uart_ao_a {
0369 mux {
0370 groups = "uart_tx_ao_a", "uart_rx_ao_a";
0371 function = "uart_ao";
0372 bias-disable;
0373 };
0374 };
0375
0376 ir_recv_pins: remote {
0377 mux {
0378 groups = "remote_input";
0379 function = "remote";
0380 bias-disable;
0381 };
0382 };
0383 };
0384 };
0385
0386 &ao_arc_rproc {
0387 compatible = "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc";
0388 amlogic,secbus2 = <&secbus2>;
0389 sram = <&ao_arc_sram>;
0390 resets = <&reset RESET_MEDIA_CPU>;
0391 clocks = <&clkc CLKID_AO_MEDIA_CPU>;
0392 };
0393
0394 &cbus {
0395 reset: reset-controller@4404 {
0396 compatible = "amlogic,meson8b-reset";
0397 reg = <0x4404 0x9c>;
0398 #reset-cells = <1>;
0399 };
0400
0401 analog_top: analog-top@81a8 {
0402 compatible = "amlogic,meson8b-analog-top", "syscon";
0403 reg = <0x81a8 0x14>;
0404 };
0405
0406 pwm_ef: pwm@86c0 {
0407 compatible = "amlogic,meson8b-pwm";
0408 reg = <0x86c0 0x10>;
0409 #pwm-cells = <3>;
0410 status = "disabled";
0411 };
0412
0413 clock-measure@8758 {
0414 compatible = "amlogic,meson8b-clk-measure";
0415 reg = <0x8758 0x1c>;
0416 };
0417
0418 pinctrl_cbus: pinctrl@9880 {
0419 compatible = "amlogic,meson8b-cbus-pinctrl";
0420 reg = <0x9880 0x10>;
0421 #address-cells = <1>;
0422 #size-cells = <1>;
0423 ranges;
0424
0425 gpio: banks@80b0 {
0426 reg = <0x80b0 0x28>,
0427 <0x80e8 0x18>,
0428 <0x8120 0x18>,
0429 <0x8030 0x38>;
0430 reg-names = "mux", "pull", "pull-enable", "gpio";
0431 gpio-controller;
0432 #gpio-cells = <2>;
0433 gpio-ranges = <&pinctrl_cbus 0 0 83>;
0434 };
0435
0436 eth_rgmii_pins: eth-rgmii {
0437 mux {
0438 groups = "eth_tx_clk",
0439 "eth_tx_en",
0440 "eth_txd1_0",
0441 "eth_txd0_0",
0442 "eth_rx_clk",
0443 "eth_rx_dv",
0444 "eth_rxd1",
0445 "eth_rxd0",
0446 "eth_mdio_en",
0447 "eth_mdc",
0448 "eth_ref_clk",
0449 "eth_txd2",
0450 "eth_txd3",
0451 "eth_rxd3",
0452 "eth_rxd2";
0453 function = "ethernet";
0454 bias-disable;
0455 };
0456 };
0457
0458 eth_rmii_pins: eth-rmii {
0459 mux {
0460 groups = "eth_tx_en",
0461 "eth_txd1_0",
0462 "eth_txd0_0",
0463 "eth_rx_clk",
0464 "eth_rx_dv",
0465 "eth_rxd1",
0466 "eth_rxd0",
0467 "eth_mdio_en",
0468 "eth_mdc";
0469 function = "ethernet";
0470 bias-disable;
0471 };
0472 };
0473
0474 i2c_a_pins: i2c-a {
0475 mux {
0476 groups = "i2c_sda_a", "i2c_sck_a";
0477 function = "i2c_a";
0478 bias-disable;
0479 };
0480 };
0481
0482 sd_b_pins: sd-b {
0483 mux {
0484 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
0485 "sd_d3_b", "sd_clk_b", "sd_cmd_b";
0486 function = "sd_b";
0487 bias-disable;
0488 };
0489 };
0490
0491 sdxc_c_pins: sdxc-c {
0492 mux {
0493 groups = "sdxc_d0_c", "sdxc_d13_c",
0494 "sdxc_d47_c", "sdxc_clk_c",
0495 "sdxc_cmd_c";
0496 function = "sdxc_c";
0497 bias-pull-up;
0498 };
0499 };
0500
0501 pwm_c1_pins: pwm-c1 {
0502 mux {
0503 groups = "pwm_c1";
0504 function = "pwm_c";
0505 bias-disable;
0506 };
0507 };
0508
0509 pwm_d_pins: pwm-d {
0510 mux {
0511 groups = "pwm_d";
0512 function = "pwm_d";
0513 bias-disable;
0514 };
0515 };
0516
0517 uart_b0_pins: uart-b0 {
0518 mux {
0519 groups = "uart_tx_b0",
0520 "uart_rx_b0";
0521 function = "uart_b";
0522 bias-disable;
0523 };
0524 };
0525
0526 uart_b0_cts_rts_pins: uart-b0-cts-rts {
0527 mux {
0528 groups = "uart_cts_b0",
0529 "uart_rts_b0";
0530 function = "uart_b";
0531 bias-disable;
0532 };
0533 };
0534 };
0535 };
0536
0537 &ahb_sram {
0538 ao_arc_sram: ao-arc-sram@0 {
0539 compatible = "amlogic,meson8b-ao-arc-sram";
0540 reg = <0x0 0x8000>;
0541 pool;
0542 };
0543
0544 smp-sram@1ff80 {
0545 compatible = "amlogic,meson8b-smp-sram";
0546 reg = <0x1ff80 0x8>;
0547 };
0548 };
0549
0550
0551 &efuse {
0552 compatible = "amlogic,meson8b-efuse";
0553 clocks = <&clkc CLKID_EFUSE>;
0554 clock-names = "core";
0555
0556 temperature_calib: calib@1f4 {
0557 /* only the upper two bytes are relevant */
0558 reg = <0x1f4 0x4>;
0559 };
0560 };
0561
0562 ðmac {
0563 compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
0564
0565 reg = <0xc9410000 0x10000
0566 0xc1108140 0x4>;
0567
0568 clocks = <&clkc CLKID_ETH>,
0569 <&clkc CLKID_MPLL2>,
0570 <&clkc CLKID_MPLL2>,
0571 <&clkc CLKID_FCLK_DIV2>;
0572 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
0573 rx-fifo-depth = <4096>;
0574 tx-fifo-depth = <2048>;
0575
0576 resets = <&reset RESET_ETHERNET>;
0577 reset-names = "stmmaceth";
0578
0579 power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
0580 };
0581
0582 &gpio_intc {
0583 compatible = "amlogic,meson-gpio-intc",
0584 "amlogic,meson8b-gpio-intc";
0585 status = "okay";
0586 };
0587
0588 &hhi {
0589 clkc: clock-controller {
0590 compatible = "amlogic,meson8b-clkc";
0591 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
0592 clock-names = "xtal", "ddr_pll";
0593 #clock-cells = <1>;
0594 #reset-cells = <1>;
0595 };
0596
0597 pwrc: power-controller {
0598 compatible = "amlogic,meson8b-pwrc";
0599 #power-domain-cells = <1>;
0600 amlogic,ao-sysctrl = <&pmu>;
0601 resets = <&reset RESET_DBLK>,
0602 <&reset RESET_PIC_DC>,
0603 <&reset RESET_HDMI_APB>,
0604 <&reset RESET_HDMI_SYSTEM_RESET>,
0605 <&reset RESET_VENCI>,
0606 <&reset RESET_VENCP>,
0607 <&reset RESET_VDAC_4>,
0608 <&reset RESET_VENCL>,
0609 <&reset RESET_VIU>,
0610 <&reset RESET_VENC>,
0611 <&reset RESET_RDMA>;
0612 reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system",
0613 "venci", "vencp", "vdac", "vencl", "viu",
0614 "venc", "rdma";
0615 clocks = <&clkc CLKID_VPU>;
0616 clock-names = "vpu";
0617 assigned-clocks = <&clkc CLKID_VPU>;
0618 assigned-clock-rates = <182142857>;
0619 };
0620 };
0621
0622 &hwrng {
0623 compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
0624 clocks = <&clkc CLKID_RNG0>;
0625 clock-names = "core";
0626 };
0627
0628 &i2c_AO {
0629 clocks = <&clkc CLKID_CLK81>;
0630 };
0631
0632 &i2c_A {
0633 clocks = <&clkc CLKID_I2C>;
0634 };
0635
0636 &i2c_B {
0637 clocks = <&clkc CLKID_I2C>;
0638 };
0639
0640 &L2 {
0641 arm,data-latency = <3 3 3>;
0642 arm,tag-latency = <2 2 2>;
0643 arm,filter-ranges = <0x100000 0xc0000000>;
0644 prefetch-data = <1>;
0645 prefetch-instr = <1>;
0646 arm,shared-override;
0647 };
0648
0649 &periph {
0650 scu@0 {
0651 compatible = "arm,cortex-a5-scu";
0652 reg = <0x0 0x100>;
0653 };
0654
0655 timer@200 {
0656 compatible = "arm,cortex-a5-global-timer";
0657 reg = <0x200 0x20>;
0658 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
0659 clocks = <&clkc CLKID_PERIPH>;
0660
0661 /*
0662 * the arm_global_timer driver currently does not handle clock
0663 * rate changes. Keep it disabled for now.
0664 */
0665 status = "disabled";
0666 };
0667
0668 timer@600 {
0669 compatible = "arm,cortex-a5-twd-timer";
0670 reg = <0x600 0x20>;
0671 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
0672 clocks = <&clkc CLKID_PERIPH>;
0673 };
0674 };
0675
0676 &pwm_ab {
0677 compatible = "amlogic,meson8b-pwm";
0678 };
0679
0680 &pwm_cd {
0681 compatible = "amlogic,meson8b-pwm";
0682 };
0683
0684 &rtc {
0685 compatible = "amlogic,meson8b-rtc";
0686 resets = <&reset RESET_RTC>;
0687 };
0688
0689 &saradc {
0690 compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
0691 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
0692 clock-names = "clkin", "core";
0693 amlogic,hhi-sysctrl = <&hhi>;
0694 nvmem-cells = <&temperature_calib>;
0695 nvmem-cell-names = "temperature_calib";
0696 };
0697
0698 &sdhc {
0699 compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
0700 clocks = <&xtal>,
0701 <&clkc CLKID_FCLK_DIV4>,
0702 <&clkc CLKID_FCLK_DIV3>,
0703 <&clkc CLKID_FCLK_DIV5>,
0704 <&clkc CLKID_SDHC>;
0705 clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
0706 };
0707
0708 &secbus {
0709 secbus2: system-controller@4000 {
0710 compatible = "amlogic,meson8b-secbus2", "syscon";
0711 reg = <0x4000 0x2000>;
0712 };
0713 };
0714
0715 &sdio {
0716 compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
0717 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
0718 clock-names = "core", "clkin";
0719 };
0720
0721 &timer_abcde {
0722 clocks = <&xtal>, <&clkc CLKID_CLK81>;
0723 clock-names = "xtal", "pclk";
0724 };
0725
0726 &uart_AO {
0727 compatible = "amlogic,meson8b-uart", "amlogic,meson-ao-uart";
0728 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
0729 clock-names = "xtal", "pclk", "baud";
0730 };
0731
0732 &uart_A {
0733 compatible = "amlogic,meson8b-uart";
0734 clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
0735 clock-names = "xtal", "pclk", "baud";
0736 };
0737
0738 &uart_B {
0739 compatible = "amlogic,meson8b-uart";
0740 clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
0741 clock-names = "xtal", "pclk", "baud";
0742 };
0743
0744 &uart_C {
0745 compatible = "amlogic,meson8b-uart";
0746 clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
0747 clock-names = "xtal", "pclk", "baud";
0748 };
0749
0750 &usb0 {
0751 compatible = "amlogic,meson8b-usb", "snps,dwc2";
0752 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
0753 clock-names = "otg";
0754 };
0755
0756 &usb1 {
0757 compatible = "amlogic,meson8b-usb", "snps,dwc2";
0758 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
0759 clock-names = "otg";
0760 };
0761
0762 &usb0_phy {
0763 compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
0764 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
0765 clock-names = "usb_general", "usb";
0766 resets = <&reset RESET_USB_OTG>;
0767 };
0768
0769 &usb1_phy {
0770 compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
0771 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
0772 clock-names = "usb_general", "usb";
0773 resets = <&reset RESET_USB_OTG>;
0774 };
0775
0776 &wdt {
0777 compatible = "amlogic,meson8b-wdt";
0778 };
