0001 // SPDX-License-Identifier: GPL-2.0 OR MIT
0002 /*
0003 * Copyright 2014 Carlo Caione <carlo@caione.org>
0004 */
0005
0006 #include "meson.dtsi"
0007
0008 / {
0009 model = "Amlogic Meson6 SoC";
0010 compatible = "amlogic,meson6";
0011
0012 cpus {
0013 #address-cells = <1>;
0014 #size-cells = <0>;
0015
0016 cpu@200 {
0017 device_type = "cpu";
0018 compatible = "arm,cortex-a9";
0019 next-level-cache = <&L2>;
0020 reg = <0x200>;
0021 };
0022
0023 cpu@201 {
0024 device_type = "cpu";
0025 compatible = "arm,cortex-a9";
0026 next-level-cache = <&L2>;
0027 reg = <0x201>;
0028 };
0029 };
0030
0031 apb2: bus@d0000000 {
0032 compatible = "simple-bus";
0033 reg = <0xd0000000 0x40000>;
0034 #address-cells = <1>;
0035 #size-cells = <1>;
0036 ranges = <0x0 0xd0000000 0x40000>;
0037 };
0038
0039 clk81: clk@0 {
0040 #clock-cells = <0>;
0041 compatible = "fixed-clock";
0042 clock-frequency = <200000000>;
0043 };
0044 }; /* end of / */
0045
0046 &efuse {
0047 status = "disabled";
0048 };
0049
0050 &timer_abcde {
0051 clocks = <&xtal>, <&clk81>;
0052 clock-names = "xtal", "pclk";
0053 };
0054
0055 &uart_AO {
0056 clocks = <&xtal>, <&clk81>, <&clk81>;
0057 clock-names = "xtal", "pclk", "baud";
0058 };
0059
0060 &uart_A {
0061 clocks = <&xtal>, <&clk81>, <&clk81>;
0062 clock-names = "xtal", "pclk", "baud";
0063 };
0064
0065 &uart_B {
0066 clocks = <&xtal>, <&clk81>, <&clk81>;
0067 clock-names = "xtal", "pclk", "baud";
0068 };
0069
0070 &uart_C {
0071 clocks = <&xtal>, <&clk81>, <&clk81>;
0072 clock-names = "xtal", "pclk", "baud";
0073 };
