0001 // SPDX-License-Identifier: GPL-2.0 OR X11
0002 /*
0003 * Copyright 2017 (C) Priit Laes <plaes@plaes.org>
0004 * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de>
0005 * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de>
0006 *
0007 * Based on initial work by Nikita Yushchenko <nyushchenko at dev.rtsoft.ru>
0008 */
0009
0010 #include <dt-bindings/gpio/gpio.h>
0011 #include <dt-bindings/sound/fsl-imx-audmux.h>
0012
0013 / {
0014 reg_1p0v_s0: regulator-1p0v-s0 {
0015 compatible = "regulator-fixed";
0016 regulator-name = "V_1V0_S0";
0017 regulator-min-microvolt = <1000000>;
0018 regulator-max-microvolt = <1000000>;
0019 regulator-always-on;
0020 regulator-boot-on;
0021 vin-supply = <®_smarc_suppy>;
0022 };
0023
0024 reg_1p35v_vcoredig_s5: regulator-1p35v-vcoredig-s5 {
0025 compatible = "regulator-fixed";
0026 regulator-name = "V_1V35_VCOREDIG_S5";
0027 regulator-min-microvolt = <1350000>;
0028 regulator-max-microvolt = <1350000>;
0029 regulator-always-on;
0030 regulator-boot-on;
0031 vin-supply = <®_3p3v_s5>;
0032 };
0033
0034 reg_1p8v_s5: regulator-1p8v-s5 {
0035 compatible = "regulator-fixed";
0036 regulator-name = "V_1V8_S5";
0037 regulator-min-microvolt = <1800000>;
0038 regulator-max-microvolt = <1800000>;
0039 regulator-always-on;
0040 regulator-boot-on;
0041 vin-supply = <®_3p3v_s5>;
0042 };
0043
0044 reg_3p3v_s0: regulator-3p3v-s0 {
0045 compatible = "regulator-fixed";
0046 regulator-name = "V_3V3_S0";
0047 regulator-min-microvolt = <3300000>;
0048 regulator-max-microvolt = <3300000>;
0049 regulator-always-on;
0050 regulator-boot-on;
0051 vin-supply = <®_3p3v_s5>;
0052 };
0053
0054 reg_3p3v_s5: regulator-3p3v-s5 {
0055 compatible = "regulator-fixed";
0056 regulator-name = "V_3V3_S5";
0057 regulator-min-microvolt = <3300000>;
0058 regulator-max-microvolt = <3300000>;
0059 regulator-always-on;
0060 regulator-boot-on;
0061 vin-supply = <®_smarc_suppy>;
0062 };
0063
0064 reg_smarc_lcdbklt: regulator-smarc-lcdbklt {
0065 compatible = "regulator-fixed";
0066 pinctrl-names = "default";
0067 pinctrl-0 = <&pinctrl_lcdbklt_en>;
0068 regulator-name = "LCD_BKLT_EN";
0069 regulator-min-microvolt = <1800000>;
0070 regulator-max-microvolt = <1800000>;
0071 gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
0072 enable-active-high;
0073 };
0074
0075 reg_smarc_lcdvdd: regulator-smarc-lcdvdd {
0076 compatible = "regulator-fixed";
0077 pinctrl-names = "default";
0078 pinctrl-0 = <&pinctrl_lcdvdd_en>;
0079 regulator-name = "LCD_VDD_EN";
0080 regulator-min-microvolt = <1800000>;
0081 regulator-max-microvolt = <1800000>;
0082 gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
0083 enable-active-high;
0084 };
0085
0086 reg_smarc_rtc: regulator-smarc-rtc {
0087 compatible = "regulator-fixed";
0088 regulator-name = "V_IN_RTC_BATT";
0089 regulator-min-microvolt = <3300000>;
0090 regulator-max-microvolt = <3300000>;
0091 regulator-always-on;
0092 regulator-boot-on;
0093 };
0094
0095 /* Module supply range can be 3.00V ... 5.25V */
0096 reg_smarc_suppy: regulator-smarc-supply {
0097 compatible = "regulator-fixed";
0098 regulator-name = "V_IN_WIDE";
0099 regulator-min-microvolt = <5000000>;
0100 regulator-max-microvolt = <5000000>;
0101 regulator-always-on;
0102 regulator-boot-on;
0103 };
0104
0105 lcd: lcd {
0106 #address-cells = <1>;
0107 #size-cells = <0>;
0108 compatible = "fsl,imx-parallel-display";
0109 pinctrl-names = "default";
0110 pinctrl-0 = <&pinctrl_lcd>;
0111 status = "disabled";
0112
0113 port@0 {
0114 reg = <0>;
0115
0116 lcd_in: endpoint {
0117 };
0118 };
0119
0120 port@1 {
0121 reg = <1>;
0122
0123 lcd_out: endpoint {
0124 };
0125 };
0126 };
0127
0128 lcd_backlight: lcd-backlight {
0129 compatible = "pwm-backlight";
0130 pwms = <&pwm4 0 5000000 0>;
0131 pwm-names = "LCD_BKLT_PWM";
0132
0133 brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
0134 default-brightness-level = <4>;
0135
0136 power-supply = <®_smarc_lcdbklt>;
0137 status = "disabled";
0138 };
0139
0140 i2c_intern: i2c-gpio-intern {
0141 compatible = "i2c-gpio";
0142 pinctrl-names = "default";
0143 pinctrl-0 = <&pinctrl_i2c_gpio_intern>;
0144 sda-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0145 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0146 i2c-gpio,delay-us = <2>; /* ~100 kHz */
0147 #address-cells = <1>;
0148 #size-cells = <0>;
0149 };
0150
0151 i2c_lcd: i2c-gpio-lcd {
0152 compatible = "i2c-gpio";
0153 pinctrl-names = "default";
0154 pinctrl-0 = <&pinctrl_i2c_gpio_lcd>;
0155 sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0156 scl-gpios = <&gpio1 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0157 i2c-gpio,delay-us = <2>; /* ~100 kHz */
0158 #address-cells = <1>;
0159 #size-cells = <0>;
0160 status = "disabled";
0161 };
0162
0163 i2c_cam: i2c-gpio-cam {
0164 compatible = "i2c-gpio";
0165 pinctrl-names = "default";
0166 pinctrl-0 = <&pinctrl_i2c_gpio_cam>;
0167 sda-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0168 scl-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0169 i2c-gpio,delay-us = <2>; /* ~100 kHz */
0170 #address-cells = <1>;
0171 #size-cells = <0>;
0172 status = "disabled";
0173 };
0174 };
0175
0176 /* I2S0, I2S1 */
0177 &audmux {
0178 pinctrl-names = "default";
0179 pinctrl-0 = <&pinctrl_audmux>;
0180
0181 audmux_ssi1 {
0182 fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
0183 fsl,port-config = <
0184 (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT3) |
0185 IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT3) |
0186 IMX_AUDMUX_V2_PTCR_SYN |
0187 IMX_AUDMUX_V2_PTCR_TFSDIR |
0188 IMX_AUDMUX_V2_PTCR_TCLKDIR)
0189 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT3)
0190 >;
0191 };
0192
0193 audmux_adu3 {
0194 fsl,audmux-port = <MX51_AUDMUX_PORT3>;
0195 fsl,port-config = <
0196 IMX_AUDMUX_V2_PTCR_SYN
0197 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
0198 >;
0199 };
0200
0201 audmux_ssi2 {
0202 fsl,audmux-port = <MX51_AUDMUX_PORT2_SSI1>;
0203 fsl,port-config = <
0204 (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
0205 IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) |
0206 IMX_AUDMUX_V2_PTCR_SYN |
0207 IMX_AUDMUX_V2_PTCR_TFSDIR |
0208 IMX_AUDMUX_V2_PTCR_TCLKDIR)
0209 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
0210 >;
0211 };
0212
0213 audmux_adu4 {
0214 fsl,audmux-port = <MX51_AUDMUX_PORT4>;
0215 fsl,port-config = <
0216 IMX_AUDMUX_V2_PTCR_SYN
0217 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT2_SSI1)
0218 >;
0219 };
0220 };
0221
0222 /* CAN0 */
0223 &can1 {
0224 pinctrl-names = "default";
0225 pinctrl-0 = <&pinctrl_flexcan1>;
0226 };
0227
0228 /* CAN1 */
0229 &can2 {
0230 pinctrl-names = "default";
0231 pinctrl-0 = <&pinctrl_flexcan2>;
0232 };
0233
0234 /* SPI1 */
0235 &ecspi2 {
0236 pinctrl-names = "default";
0237 pinctrl-0 = <&pinctrl_ecspi2>;
0238 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>,
0239 <&gpio2 27 GPIO_ACTIVE_LOW>;
0240 };
0241
0242 /* SPI0 */
0243 &ecspi4 {
0244 pinctrl-names = "default";
0245 pinctrl-0 = <&pinctrl_ecspi4>;
0246 cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>,
0247 <&gpio3 29 GPIO_ACTIVE_LOW>;
0248 status = "okay";
0249
0250 /* default boot source: workaround #1 for errata ERR006282 */
0251 smarc_flash: flash@0 {
0252 compatible = "jedec,spi-nor";
0253 reg = <0>;
0254 spi-max-frequency = <20000000>;
0255 };
0256 };
0257
0258 /* GBE */
0259 &fec {
0260 pinctrl-names = "default";
0261 pinctrl-0 = <&pinctrl_enet>;
0262 phy-mode = "rgmii";
0263 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
0264 };
0265
0266 &i2c_intern {
0267 pmic@8 {
0268 compatible = "fsl,pfuze100";
0269 reg = <0x08>;
0270
0271 regulators {
0272 reg_v_core_s0: sw1ab {
0273 regulator-name = "V_CORE_S0";
0274 regulator-min-microvolt = <300000>;
0275 regulator-max-microvolt = <1875000>;
0276 regulator-boot-on;
0277 regulator-always-on;
0278 };
0279
0280 reg_vddsoc_s0: sw1c {
0281 regulator-name = "V_VDDSOC_S0";
0282 regulator-min-microvolt = <300000>;
0283 regulator-max-microvolt = <1875000>;
0284 regulator-boot-on;
0285 regulator-always-on;
0286 };
0287
0288 reg_3p15v_s0: sw2 {
0289 regulator-name = "V_3V15_S0";
0290 regulator-min-microvolt = <800000>;
0291 regulator-max-microvolt = <3300000>;
0292 regulator-boot-on;
0293 regulator-always-on;
0294 };
0295
0296 /* sw3a/b is used in dual mode, but driver does not
0297 * support it. Although, there's no need to control
0298 * DDR power - so just leaving dummy entries for sw3a
0299 * and sw3b for now.
0300 */
0301 sw3a {
0302 regulator-min-microvolt = <400000>;
0303 regulator-max-microvolt = <1975000>;
0304 regulator-boot-on;
0305 regulator-always-on;
0306 };
0307
0308 sw3b {
0309 regulator-min-microvolt = <400000>;
0310 regulator-max-microvolt = <1975000>;
0311 regulator-boot-on;
0312 regulator-always-on;
0313 };
0314
0315 reg_1p8v_s0: sw4 {
0316 regulator-name = "V_1V8_S0";
0317 regulator-min-microvolt = <800000>;
0318 regulator-max-microvolt = <3300000>;
0319 regulator-boot-on;
0320 regulator-always-on;
0321 };
0322
0323 /* Regulator for USB */
0324 reg_5p0v_s0: swbst {
0325 regulator-name = "V_5V0_S0";
0326 regulator-min-microvolt = <5000000>;
0327 regulator-max-microvolt = <5150000>;
0328 regulator-boot-on;
0329 };
0330
0331 reg_vsnvs: vsnvs {
0332 regulator-min-microvolt = <1000000>;
0333 regulator-max-microvolt = <3000000>;
0334 regulator-boot-on;
0335 regulator-always-on;
0336 };
0337
0338 reg_vrefddr: vrefddr {
0339 regulator-boot-on;
0340 regulator-always-on;
0341 };
0342
0343 /*
0344 * Per schematics, of all VGEN's, only VGEN5 has some
0345 * usage ... but even that - over DNI resistor
0346 */
0347 vgen1 {
0348 regulator-min-microvolt = <800000>;
0349 regulator-max-microvolt = <1550000>;
0350 };
0351
0352 vgen2 {
0353 regulator-min-microvolt = <800000>;
0354 regulator-max-microvolt = <1550000>;
0355 };
0356
0357 vgen3 {
0358 regulator-min-microvolt = <1800000>;
0359 regulator-max-microvolt = <3300000>;
0360 };
0361
0362 vgen4 {
0363 regulator-min-microvolt = <1800000>;
0364 regulator-max-microvolt = <3300000>;
0365 };
0366
0367 reg_2p5v_s0: vgen5 {
0368 regulator-name = "V_2V5_S0";
0369 regulator-min-microvolt = <1800000>;
0370 regulator-max-microvolt = <3300000>;
0371 };
0372
0373 vgen6 {
0374 regulator-min-microvolt = <1800000>;
0375 regulator-max-microvolt = <3300000>;
0376 };
0377 };
0378 };
0379 };
0380
0381 /* I2C_GP */
0382 &i2c1 {
0383 clock-frequency = <375000>;
0384 pinctrl-names = "default";
0385 pinctrl-0 = <&pinctrl_i2c1>;
0386 };
0387
0388 /* HDMI_CTRL */
0389 &i2c2 {
0390 clock-frequency = <375000>;
0391 pinctrl-names = "default";
0392 pinctrl-0 = <&pinctrl_i2c2>;
0393 };
0394
0395 /* I2C_PM */
0396 &i2c3 {
0397 clock-frequency = <375000>;
0398 pinctrl-names = "default";
0399 pinctrl-0 = <&pinctrl_i2c3>;
0400 status = "okay";
0401
0402 smarc_eeprom: eeprom@50 {
0403 compatible = "atmel,24c32";
0404 reg = <0x50>;
0405 pagesize = <32>;
0406 };
0407 };
0408
0409 &iomuxc {
0410 pinctrl-names = "default";
0411 pinctrl-0 = <&pinctrl_mgmt_gpios &pinctrl_gpio>;
0412
0413 pinctrl_audmux: audmuxgrp {
0414 fsl,pins = <
0415 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
0416 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0
0417 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
0418 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
0419
0420 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
0421 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
0422 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
0423 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
0424
0425 /* AUDIO MCLK */
0426 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x000b0
0427 >;
0428 };
0429
0430 pinctrl_ecspi2: ecspi2grp {
0431 fsl,pins = <
0432 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
0433 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
0434 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
0435
0436 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 /* CS0 */
0437 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /* CS1 */
0438 >;
0439 };
0440
0441 pinctrl_ecspi4: ecspi4grp {
0442 fsl,pins = <
0443 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
0444 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
0445 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
0446
0447 /* SPI_IMX_CS2# - connected to internal flash */
0448 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0
0449 /* SPI_IMX_CS0# - connected to SMARC SPI0_CS0# */
0450 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
0451 >;
0452 };
0453
0454 pinctrl_flexcan1: flexcan1grp {
0455 fsl,pins = <
0456 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
0457 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
0458 >;
0459 };
0460
0461 pinctrl_flexcan2: flexcan2grp {
0462 fsl,pins = <
0463 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
0464 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
0465 >;
0466 };
0467
0468 pinctrl_gpio: gpiogrp {
0469 fsl,pins = <
0470 MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 /* GPIO0 / CAM0_PWR# */
0471 MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 /* GPIO1 / CAM1_PWR# */
0472 MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 /* GPIO2 / CAM0_RST# */
0473 MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 /* GPIO3 / CAM1_RST# */
0474 MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 /* GPIO4 / HDA_RST# */
0475 MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 /* GPIO5 / PWM_OUT */
0476 MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 /* GPIO6 / TACHIN */
0477 MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 /* GPIO7 / PCAM_FLD */
0478 MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b0 /* GPIO8 / CAN0_ERR# */
0479 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b0 /* GPIO9 / CAN1_ERR# */
0480 MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b0 /* GPIO10 */
0481 MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b0 /* GPIO11 */
0482 >;
0483 };
0484
0485 pinctrl_enet: enetgrp {
0486 fsl,pins = <
0487 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
0488 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
0489 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
0490 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
0491 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
0492 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
0493 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
0494 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
0495 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
0496 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
0497 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
0498 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
0499
0500 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
0501 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
0502 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
0503 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */
0504 >;
0505 };
0506
0507 pinctrl_i2c_gpio_cam: i2c-gpiocamgrp {
0508 fsl,pins = <
0509 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* SCL */
0510 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* SDA */
0511 >;
0512 };
0513
0514 pinctrl_i2c_gpio_intern: i2c-gpiointerngrp {
0515 fsl,pins = <
0516 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */
0517 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* SDA */
0518 >;
0519 };
0520
0521 pinctrl_i2c_gpio_lcd: i2c-gpiolcdgrp {
0522 fsl,pins = <
0523 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 /* SCL */
0524 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 /* SDA */
0525 >;
0526 };
0527
0528 pinctrl_i2c1: i2c1grp {
0529 fsl,pins = <
0530 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
0531 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
0532 >;
0533 };
0534
0535 pinctrl_i2c2: i2c2grp {
0536 fsl,pins = <
0537 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
0538 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
0539 >;
0540 };
0541
0542 pinctrl_i2c3: i2c3grp {
0543 fsl,pins = <
0544 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
0545 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
0546 >;
0547 };
0548
0549 pinctrl_lcd: lcdgrp {
0550 fsl,pins = <
0551 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f1
0552 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f1
0553 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f1
0554 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f1
0555 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f1
0556 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f1
0557 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f1
0558 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f1
0559 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f1
0560 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f1
0561 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f1
0562 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f1
0563 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f1
0564 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f1
0565 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f1
0566 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f1
0567 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f1
0568 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f1
0569 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f1
0570 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f1
0571 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f1
0572 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f1
0573 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f1
0574 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f1
0575
0576 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f1
0577 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f1 /* DE */
0578 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f1 /* HSYNC */
0579 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f1 /* VSYNC */
0580 >;
0581 };
0582
0583 pinctrl_lcdbklt_en: lcdbkltengrp {
0584 fsl,pins = <
0585 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b1
0586 >;
0587 };
0588
0589 pinctrl_lcdvdd_en: lcdvddengrp {
0590 fsl,pins = <
0591 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
0592 >;
0593 };
0594
0595 pinctrl_mipi_csi: mipi-csigrp {
0596 fsl,pins = <
0597 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x000b0 /* CSI0/1 MCLK */
0598 >;
0599 };
0600
0601 pinctrl_mgmt_gpios: mgmt-gpiosgrp {
0602 fsl,pins = <
0603 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 /* LID# */
0604 MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x1b0b0 /* SLEEP# */
0605 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* CHARGING# */
0606 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* CHARGER_PRSNT# */
0607 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 /* CARRIER_STBY# */
0608 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* BATLOW# */
0609 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 /* TEST# */
0610 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 /* VDD_IO_SEL_D# */
0611 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* POWER_BTN# */
0612 >;
0613 };
0614
0615 pinctrl_pcie: pciegrp {
0616 fsl,pins = <
0617 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */
0618 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /* RST_PCIE_A# */
0619 MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* PCIE_WAKE# */
0620 >;
0621 };
0622
0623 pinctrl_pwm4: pwm4grp {
0624 fsl,pins = <
0625 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
0626 >;
0627 };
0628
0629 pinctrl_uart1: uart1grp {
0630 fsl,pins = <
0631 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
0632 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
0633 MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
0634 MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1
0635 >;
0636 };
0637
0638 pinctrl_uart2: uart2grp {
0639 fsl,pins = <
0640 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
0641 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
0642 >;
0643 };
0644
0645 pinctrl_uart4: uart4grp {
0646 fsl,pins = <
0647 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
0648 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
0649 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
0650 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
0651 >;
0652 };
0653
0654 pinctrl_uart5: uart5grp {
0655 fsl,pins = <
0656 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
0657 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
0658 >;
0659 };
0660
0661 pinctrl_usbotg: usbotggrp {
0662 fsl,pins = <
0663 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0
0664 /* power, oc muxed but not used by the driver */
0665 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 /* USB power */
0666 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /* USB OC */
0667 >;
0668 };
0669
0670 pinctrl_usdhc3: usdhc3grp {
0671 fsl,pins = <
0672 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x17059
0673 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
0674 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
0675 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
0676 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
0677 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
0678
0679 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* CD */
0680 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* WP */
0681 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PWR_EN */
0682 >;
0683 };
0684
0685 pinctrl_usdhc4: usdhc4grp {
0686 fsl,pins = <
0687 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
0688 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
0689 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
0690 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
0691 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
0692 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
0693 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
0694 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
0695 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
0696 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
0697 >;
0698 };
0699
0700 pinctrl_wdog1: wdog1rp {
0701 fsl,pins = <
0702 MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
0703 >;
0704 };
0705 };
0706
0707 &mipi_csi {
0708 pinctrl-names = "default";
0709 pinctrl-0 = <&pinctrl_mipi_csi>;
0710 };
0711
0712 &pcie {
0713 pinctrl-names = "default";
0714 pinctrl-0 = <&pinctrl_pcie>;
0715 wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>;
0716 reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
0717 };
0718
0719 /* LCD_BKLT_PWM */
0720 &pwm4 {
0721 pinctrl-names = "default";
0722 pinctrl-0 = <&pinctrl_pwm4>;
0723 };
0724
0725 ®_arm {
0726 vin-supply = <®_v_core_s0>;
0727 };
0728
0729 ®_pu {
0730 vin-supply = <®_vddsoc_s0>;
0731 };
0732
0733 ®_soc {
0734 vin-supply = <®_vddsoc_s0>;
0735 };
0736
0737 /* SER0 */
0738 &uart1 {
0739 pinctrl-names = "default";
0740 pinctrl-0 = <&pinctrl_uart1>;
0741 uart-has-rtscts;
0742 };
0743
0744 /* SER1 */
0745 &uart2 {
0746 pinctrl-names = "default";
0747 pinctrl-0 = <&pinctrl_uart2>;
0748 };
0749
0750 /* SER2 */
0751 &uart4 {
0752 pinctrl-names = "default";
0753 pinctrl-0 = <&pinctrl_uart4>;
0754 uart-has-rtscts;
0755 };
0756
0757 /* SER3 */
0758 &uart5 {
0759 pinctrl-names = "default";
0760 pinctrl-0 = <&pinctrl_uart5>;
0761 };
0762
0763 /* USB0 */
0764 &usbotg {
0765 /*
0766 * no 'imx6-usb-charger-detection'
0767 * since USB_OTG_CHD_B pin is not wired
0768 */
0769 pinctrl-names = "default";
0770 pinctrl-0 = <&pinctrl_usbotg>;
0771 };
0772
0773 /* USB1/2 via hub */
0774 &usbh1 {
0775 vbus-supply = <®_5p0v_s0>;
0776 };
0777
0778 /* SDIO */
0779 &usdhc3 {
0780 pinctrl-names = "default";
0781 pinctrl-0 = <&pinctrl_usdhc3>;
0782 cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
0783 wp-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
0784 no-1-8-v;
0785 };
0786
0787 /* SDMMC */
0788 &usdhc4 {
0789 /* Internal eMMC, optional on some boards */
0790 pinctrl-names = "default";
0791 pinctrl-0 = <&pinctrl_usdhc4>;
0792 bus-width = <8>;
0793 no-sdio;
0794 no-sd;
0795 non-removable;
0796 vmmc-supply = <®_3p3v_s0>;
0797 vqmmc-supply = <®_1p8v_s0>;
0798 };
0799
0800 &wdog1 {
0801 /* CPLD is feeded by watchdog (hardwired) */
0802 pinctrl-names = "default";
0803 pinctrl-0 = <&pinctrl_wdog1>;
0804 status = "okay";
0805 };
