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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * HiSilicon Ltd. HiP04 SoC
0004 *
0005 * Copyright (C) 2013-2014 HiSilicon Ltd.
0006 * Copyright (C) 2013-2014 Linaro Ltd.
0007 *
0008 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
0009 */
0010
0011 / {
0012 /* memory bus is 64-bit */
0013 #address-cells = <2>;
0014 #size-cells = <2>;
0015
0016 aliases {
0017 serial0 = &uart0;
0018 };
0019
0020 bootwrapper {
0021 compatible = "hisilicon,hip04-bootwrapper";
0022 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
0023 };
0024
0025 cpus {
0026 #address-cells = <1>;
0027 #size-cells = <0>;
0028
0029 cpu-map {
0030 cluster0 {
0031 core0 {
0032 cpu = <&CPU0>;
0033 };
0034 core1 {
0035 cpu = <&CPU1>;
0036 };
0037 core2 {
0038 cpu = <&CPU2>;
0039 };
0040 core3 {
0041 cpu = <&CPU3>;
0042 };
0043 };
0044 cluster1 {
0045 core0 {
0046 cpu = <&CPU4>;
0047 };
0048 core1 {
0049 cpu = <&CPU5>;
0050 };
0051 core2 {
0052 cpu = <&CPU6>;
0053 };
0054 core3 {
0055 cpu = <&CPU7>;
0056 };
0057 };
0058 cluster2 {
0059 core0 {
0060 cpu = <&CPU8>;
0061 };
0062 core1 {
0063 cpu = <&CPU9>;
0064 };
0065 core2 {
0066 cpu = <&CPU10>;
0067 };
0068 core3 {
0069 cpu = <&CPU11>;
0070 };
0071 };
0072 cluster3 {
0073 core0 {
0074 cpu = <&CPU12>;
0075 };
0076 core1 {
0077 cpu = <&CPU13>;
0078 };
0079 core2 {
0080 cpu = <&CPU14>;
0081 };
0082 core3 {
0083 cpu = <&CPU15>;
0084 };
0085 };
0086 };
0087 CPU0: cpu@0 {
0088 device_type = "cpu";
0089 compatible = "arm,cortex-a15";
0090 reg = <0>;
0091 };
0092 CPU1: cpu@1 {
0093 device_type = "cpu";
0094 compatible = "arm,cortex-a15";
0095 reg = <1>;
0096 };
0097 CPU2: cpu@2 {
0098 device_type = "cpu";
0099 compatible = "arm,cortex-a15";
0100 reg = <2>;
0101 };
0102 CPU3: cpu@3 {
0103 device_type = "cpu";
0104 compatible = "arm,cortex-a15";
0105 reg = <3>;
0106 };
0107 CPU4: cpu@100 {
0108 device_type = "cpu";
0109 compatible = "arm,cortex-a15";
0110 reg = <0x100>;
0111 };
0112 CPU5: cpu@101 {
0113 device_type = "cpu";
0114 compatible = "arm,cortex-a15";
0115 reg = <0x101>;
0116 };
0117 CPU6: cpu@102 {
0118 device_type = "cpu";
0119 compatible = "arm,cortex-a15";
0120 reg = <0x102>;
0121 };
0122 CPU7: cpu@103 {
0123 device_type = "cpu";
0124 compatible = "arm,cortex-a15";
0125 reg = <0x103>;
0126 };
0127 CPU8: cpu@200 {
0128 device_type = "cpu";
0129 compatible = "arm,cortex-a15";
0130 reg = <0x200>;
0131 };
0132 CPU9: cpu@201 {
0133 device_type = "cpu";
0134 compatible = "arm,cortex-a15";
0135 reg = <0x201>;
0136 };
0137 CPU10: cpu@202 {
0138 device_type = "cpu";
0139 compatible = "arm,cortex-a15";
0140 reg = <0x202>;
0141 };
0142 CPU11: cpu@203 {
0143 device_type = "cpu";
0144 compatible = "arm,cortex-a15";
0145 reg = <0x203>;
0146 };
0147 CPU12: cpu@300 {
0148 device_type = "cpu";
0149 compatible = "arm,cortex-a15";
0150 reg = <0x300>;
0151 };
0152 CPU13: cpu@301 {
0153 device_type = "cpu";
0154 compatible = "arm,cortex-a15";
0155 reg = <0x301>;
0156 };
0157 CPU14: cpu@302 {
0158 device_type = "cpu";
0159 compatible = "arm,cortex-a15";
0160 reg = <0x302>;
0161 };
0162 CPU15: cpu@303 {
0163 device_type = "cpu";
0164 compatible = "arm,cortex-a15";
0165 reg = <0x303>;
0166 };
0167 };
0168
0169 timer {
0170 compatible = "arm,armv7-timer";
0171 interrupt-parent = <&gic>;
0172 interrupts = <1 13 0xf08>,
0173 <1 14 0xf08>,
0174 <1 11 0xf08>,
0175 <1 10 0xf08>;
0176 };
0177
0178 clk_50m: clk_50m {
0179 #clock-cells = <0>;
0180 compatible = "fixed-clock";
0181 clock-frequency = <50000000>;
0182 };
0183
0184 clk_168m: clk_168m {
0185 #clock-cells = <0>;
0186 compatible = "fixed-clock";
0187 clock-frequency = <168000000>;
0188 };
0189
0190 clk_375m: clk_375m {
0191 #clock-cells = <0>;
0192 compatible = "fixed-clock";
0193 clock-frequency = <375000000>;
0194 };
0195
0196 soc {
0197 /* It's a 32-bit SoC. */
0198 #address-cells = <1>;
0199 #size-cells = <1>;
0200 compatible = "simple-bus";
0201 interrupt-parent = <&gic>;
0202 ranges = <0 0 0xe0000000 0x10000000>;
0203
0204 gic: interrupt-controller@c01000 {
0205 compatible = "hisilicon,hip04-intc";
0206 #interrupt-cells = <3>;
0207 #address-cells = <0>;
0208 interrupt-controller;
0209 interrupts = <1 9 0xf04>;
0210
0211 reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
0212 <0xc04000 0x2000>, <0xc06000 0x2000>;
0213 };
0214
0215 sysctrl: sysctrl {
0216 compatible = "hisilicon,sysctrl", "syscon";
0217 reg = <0x3e00000 0x00100000>;
0218 };
0219
0220 fabric: fabric {
0221 compatible = "hisilicon,hip04-fabric";
0222 reg = <0x302a000 0x1000>;
0223 };
0224
0225 dual_timer0: dual_timer@3000000 {
0226 compatible = "arm,sp804", "arm,primecell";
0227 reg = <0x3000000 0x1000>;
0228 interrupts = <0 224 4>;
0229 clocks = <&clk_50m>, <&clk_50m>, <&clk_50m>;
0230 clock-names = "timer0clk", "timer1clk", "apb_pclk";
0231 };
0232
0233 arm-pmu {
0234 compatible = "arm,cortex-a15-pmu";
0235 interrupts = <0 64 4>,
0236 <0 65 4>,
0237 <0 66 4>,
0238 <0 67 4>,
0239 <0 68 4>,
0240 <0 69 4>,
0241 <0 70 4>,
0242 <0 71 4>,
0243 <0 72 4>,
0244 <0 73 4>,
0245 <0 74 4>,
0246 <0 75 4>,
0247 <0 76 4>,
0248 <0 77 4>,
0249 <0 78 4>,
0250 <0 79 4>;
0251 };
0252
0253 uart0: serial@4007000 {
0254 compatible = "snps,dw-apb-uart";
0255 reg = <0x4007000 0x1000>;
0256 interrupts = <0 381 4>;
0257 clocks = <&clk_168m>, <&clk_168m>;
0258 clock-names = "baudclk", "apb_pclk";
0259 reg-shift = <2>;
0260 status = "disabled";
0261 };
0262
0263 sata0: sata@a000000 {
0264 compatible = "hisilicon,hisi-ahci";
0265 reg = <0xa000000 0x1000000>;
0266 interrupts = <0 372 4>;
0267 };
0268
0269 };
0270
0271 etb@0,e3c42000 {
0272 compatible = "arm,coresight-etb10", "arm,primecell";
0273 reg = <0 0xe3c42000 0 0x1000>;
0274
0275 clocks = <&clk_375m>;
0276 clock-names = "apb_pclk";
0277 in-ports {
0278 port {
0279 etb0_in_port: endpoint@0 {
0280 remote-endpoint = <&replicator0_out_port0>;
0281 };
0282 };
0283 };
0284 };
0285
0286 etb@0,e3c82000 {
0287 compatible = "arm,coresight-etb10", "arm,primecell";
0288 reg = <0 0xe3c82000 0 0x1000>;
0289
0290 clocks = <&clk_375m>;
0291 clock-names = "apb_pclk";
0292 in-ports {
0293 port {
0294 etb1_in_port: endpoint@0 {
0295 remote-endpoint = <&replicator1_out_port0>;
0296 };
0297 };
0298 };
0299 };
0300
0301 etb@0,e3cc2000 {
0302 compatible = "arm,coresight-etb10", "arm,primecell";
0303 reg = <0 0xe3cc2000 0 0x1000>;
0304
0305 clocks = <&clk_375m>;
0306 clock-names = "apb_pclk";
0307 in-ports {
0308 port {
0309 etb2_in_port: endpoint@0 {
0310 remote-endpoint = <&replicator2_out_port0>;
0311 };
0312 };
0313 };
0314 };
0315
0316 etb@0,e3d02000 {
0317 compatible = "arm,coresight-etb10", "arm,primecell";
0318 reg = <0 0xe3d02000 0 0x1000>;
0319
0320 clocks = <&clk_375m>;
0321 clock-names = "apb_pclk";
0322 in-ports {
0323 port {
0324 etb3_in_port: endpoint@0 {
0325 remote-endpoint = <&replicator3_out_port0>;
0326 };
0327 };
0328 };
0329 };
0330
0331 tpiu@0,e3c05000 {
0332 compatible = "arm,coresight-tpiu", "arm,primecell";
0333 reg = <0 0xe3c05000 0 0x1000>;
0334
0335 clocks = <&clk_375m>;
0336 clock-names = "apb_pclk";
0337 in-ports {
0338 port {
0339 tpiu_in_port: endpoint@0 {
0340 remote-endpoint = <&funnel4_out_port0>;
0341 };
0342 };
0343 };
0344 };
0345
0346 replicator0 {
0347 /* non-configurable replicators don't show up on the
0348 * AMBA bus. As such no need to add "arm,primecell".
0349 */
0350 compatible = "arm,coresight-static-replicator";
0351
0352 out-ports {
0353 #address-cells = <1>;
0354 #size-cells = <0>;
0355
0356 /* replicator output ports */
0357 port@0 {
0358 reg = <0>;
0359 replicator0_out_port0: endpoint {
0360 remote-endpoint = <&etb0_in_port>;
0361 };
0362 };
0363
0364 port@1 {
0365 reg = <1>;
0366 replicator0_out_port1: endpoint {
0367 remote-endpoint = <&funnel4_in_port0>;
0368 };
0369 };
0370 };
0371
0372 in-ports {
0373 port {
0374 replicator0_in_port0: endpoint {
0375 remote-endpoint = <&funnel0_out_port0>;
0376 };
0377 };
0378 };
0379 };
0380
0381 replicator1 {
0382 /* non-configurable replicators don't show up on the
0383 * AMBA bus. As such no need to add "arm,primecell".
0384 */
0385 compatible = "arm,coresight-static-replicator";
0386
0387 out-ports {
0388 #address-cells = <1>;
0389 #size-cells = <0>;
0390
0391 /* replicator output ports */
0392 port@0 {
0393 reg = <0>;
0394 replicator1_out_port0: endpoint {
0395 remote-endpoint = <&etb1_in_port>;
0396 };
0397 };
0398
0399 port@1 {
0400 reg = <1>;
0401 replicator1_out_port1: endpoint {
0402 remote-endpoint = <&funnel4_in_port1>;
0403 };
0404 };
0405 };
0406
0407 in-ports {
0408 port {
0409 replicator1_in_port0: endpoint {
0410 remote-endpoint = <&funnel1_out_port0>;
0411 };
0412 };
0413 };
0414 };
0415
0416 replicator2 {
0417 /* non-configurable replicators don't show up on the
0418 * AMBA bus. As such no need to add "arm,primecell".
0419 */
0420 compatible = "arm,coresight-static-replicator";
0421
0422 out-ports {
0423 #address-cells = <1>;
0424 #size-cells = <0>;
0425
0426 port@0 {
0427 reg = <0>;
0428 replicator2_out_port0: endpoint {
0429 remote-endpoint = <&etb2_in_port>;
0430 };
0431 };
0432
0433 port@1 {
0434 reg = <1>;
0435 replicator2_out_port1: endpoint {
0436 remote-endpoint = <&funnel4_in_port2>;
0437 };
0438 };
0439 };
0440
0441 in-ports {
0442 port {
0443 replicator2_in_port0: endpoint {
0444 remote-endpoint = <&funnel2_out_port0>;
0445 };
0446 };
0447 };
0448 };
0449
0450 replicator3 {
0451 /* non-configurable replicators don't show up on the
0452 * AMBA bus. As such no need to add "arm,primecell".
0453 */
0454 compatible = "arm,coresight-static-replicator";
0455
0456 out-ports {
0457 #address-cells = <1>;
0458 #size-cells = <0>;
0459
0460 port@0 {
0461 reg = <0>;
0462 replicator3_out_port0: endpoint {
0463 remote-endpoint = <&etb3_in_port>;
0464 };
0465 };
0466
0467 port@1 {
0468 reg = <1>;
0469 replicator3_out_port1: endpoint {
0470 remote-endpoint = <&funnel4_in_port3>;
0471 };
0472 };
0473 };
0474
0475 in-ports {
0476 port {
0477 replicator3_in_port0: endpoint {
0478 remote-endpoint = <&funnel3_out_port0>;
0479 };
0480 };
0481 };
0482 };
0483
0484 funnel@0,e3c41000 {
0485 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0486 reg = <0 0xe3c41000 0 0x1000>;
0487
0488 clocks = <&clk_375m>;
0489 clock-names = "apb_pclk";
0490 out-ports {
0491 port {
0492 funnel0_out_port0: endpoint {
0493 remote-endpoint =
0494 <&replicator0_in_port0>;
0495 };
0496 };
0497 };
0498
0499 in-ports {
0500 #address-cells = <1>;
0501 #size-cells = <0>;
0502
0503 port@0 {
0504 reg = <0>;
0505 funnel0_in_port0: endpoint {
0506 remote-endpoint = <&ptm0_out_port>;
0507 };
0508 };
0509
0510 port@1 {
0511 reg = <1>;
0512 funnel0_in_port1: endpoint {
0513 remote-endpoint = <&ptm1_out_port>;
0514 };
0515 };
0516
0517 port@2 {
0518 reg = <2>;
0519 funnel0_in_port2: endpoint {
0520 remote-endpoint = <&ptm2_out_port>;
0521 };
0522 };
0523
0524 port@3 {
0525 reg = <3>;
0526 funnel0_in_port3: endpoint {
0527 remote-endpoint = <&ptm3_out_port>;
0528 };
0529 };
0530 };
0531 };
0532
0533 funnel@0,e3c81000 {
0534 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0535 reg = <0 0xe3c81000 0 0x1000>;
0536
0537 clocks = <&clk_375m>;
0538 clock-names = "apb_pclk";
0539 out-ports {
0540 port {
0541 funnel1_out_port0: endpoint {
0542 remote-endpoint =
0543 <&replicator1_in_port0>;
0544 };
0545 };
0546 };
0547
0548 in-ports {
0549 #address-cells = <1>;
0550 #size-cells = <0>;
0551
0552 port@0 {
0553 reg = <0>;
0554 funnel1_in_port0: endpoint {
0555 remote-endpoint = <&ptm4_out_port>;
0556 };
0557 };
0558
0559 port@1 {
0560 reg = <1>;
0561 funnel1_in_port1: endpoint {
0562 remote-endpoint = <&ptm5_out_port>;
0563 };
0564 };
0565
0566 port@2 {
0567 reg = <2>;
0568 funnel1_in_port2: endpoint {
0569 remote-endpoint = <&ptm6_out_port>;
0570 };
0571 };
0572
0573 port@3 {
0574 reg = <3>;
0575 funnel1_in_port3: endpoint {
0576 remote-endpoint = <&ptm7_out_port>;
0577 };
0578 };
0579 };
0580 };
0581
0582 funnel@0,e3cc1000 {
0583 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0584 reg = <0 0xe3cc1000 0 0x1000>;
0585
0586 clocks = <&clk_375m>;
0587 clock-names = "apb_pclk";
0588 out-ports {
0589 port {
0590 funnel2_out_port0: endpoint {
0591 remote-endpoint =
0592 <&replicator2_in_port0>;
0593 };
0594 };
0595 };
0596
0597 in-ports {
0598 #address-cells = <1>;
0599 #size-cells = <0>;
0600
0601 port@0 {
0602 reg = <0>;
0603 funnel2_in_port0: endpoint {
0604 remote-endpoint = <&ptm8_out_port>;
0605 };
0606 };
0607
0608 port@1 {
0609 reg = <1>;
0610 funnel2_in_port1: endpoint {
0611 remote-endpoint = <&ptm9_out_port>;
0612 };
0613 };
0614
0615 port@2 {
0616 reg = <2>;
0617 funnel2_in_port2: endpoint {
0618 remote-endpoint = <&ptm10_out_port>;
0619 };
0620 };
0621
0622 port@3 {
0623 reg = <3>;
0624 funnel2_in_port3: endpoint {
0625 remote-endpoint = <&ptm11_out_port>;
0626 };
0627 };
0628 };
0629 };
0630
0631 funnel@0,e3d01000 {
0632 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0633 reg = <0 0xe3d01000 0 0x1000>;
0634
0635 clocks = <&clk_375m>;
0636 clock-names = "apb_pclk";
0637 out-ports {
0638 port {
0639 funnel3_out_port0: endpoint {
0640 remote-endpoint =
0641 <&replicator3_in_port0>;
0642 };
0643 };
0644 };
0645
0646 in-ports {
0647 #address-cells = <1>;
0648 #size-cells = <0>;
0649
0650 port@0 {
0651 reg = <0>;
0652 funnel3_in_port0: endpoint {
0653 remote-endpoint = <&ptm12_out_port>;
0654 };
0655 };
0656
0657 port@1 {
0658 reg = <1>;
0659 funnel3_in_port1: endpoint {
0660 remote-endpoint = <&ptm13_out_port>;
0661 };
0662 };
0663
0664 port@2 {
0665 reg = <2>;
0666 funnel3_in_port2: endpoint {
0667 remote-endpoint = <&ptm14_out_port>;
0668 };
0669 };
0670
0671 port@3 {
0672 reg = <3>;
0673 funnel3_in_port3: endpoint {
0674 remote-endpoint = <&ptm15_out_port>;
0675 };
0676 };
0677 };
0678 };
0679
0680 funnel@0,e3c04000 {
0681 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0682 reg = <0 0xe3c04000 0 0x1000>;
0683
0684 clocks = <&clk_375m>;
0685 clock-names = "apb_pclk";
0686 out-ports {
0687 port {
0688 funnel4_out_port0: endpoint {
0689 remote-endpoint = <&tpiu_in_port>;
0690 };
0691 };
0692 };
0693
0694 in-ports {
0695 #address-cells = <1>;
0696 #size-cells = <0>;
0697
0698 port@0 {
0699 reg = <0>;
0700 funnel4_in_port0: endpoint {
0701 remote-endpoint =
0702 <&replicator0_out_port1>;
0703 };
0704 };
0705
0706 port@1 {
0707 reg = <1>;
0708 funnel4_in_port1: endpoint {
0709 remote-endpoint =
0710 <&replicator1_out_port1>;
0711 };
0712 };
0713
0714 port@2 {
0715 reg = <2>;
0716 funnel4_in_port2: endpoint {
0717 remote-endpoint =
0718 <&replicator2_out_port1>;
0719 };
0720 };
0721
0722 port@3 {
0723 reg = <3>;
0724 funnel4_in_port3: endpoint {
0725 remote-endpoint =
0726 <&replicator3_out_port1>;
0727 };
0728 };
0729 };
0730 };
0731
0732 ptm@0,e3c7c000 {
0733 compatible = "arm,coresight-etm3x", "arm,primecell";
0734 reg = <0 0xe3c7c000 0 0x1000>;
0735
0736 clocks = <&clk_375m>;
0737 clock-names = "apb_pclk";
0738 cpu = <&CPU0>;
0739 out-ports {
0740 port {
0741 ptm0_out_port: endpoint {
0742 remote-endpoint = <&funnel0_in_port0>;
0743 };
0744 };
0745 };
0746 };
0747
0748 ptm@0,e3c7d000 {
0749 compatible = "arm,coresight-etm3x", "arm,primecell";
0750 reg = <0 0xe3c7d000 0 0x1000>;
0751
0752 clocks = <&clk_375m>;
0753 clock-names = "apb_pclk";
0754 cpu = <&CPU1>;
0755 out-ports {
0756 port {
0757 ptm1_out_port: endpoint {
0758 remote-endpoint = <&funnel0_in_port1>;
0759 };
0760 };
0761 };
0762 };
0763
0764 ptm@0,e3c7e000 {
0765 compatible = "arm,coresight-etm3x", "arm,primecell";
0766 reg = <0 0xe3c7e000 0 0x1000>;
0767
0768 clocks = <&clk_375m>;
0769 clock-names = "apb_pclk";
0770 cpu = <&CPU2>;
0771 out-ports {
0772 port {
0773 ptm2_out_port: endpoint {
0774 remote-endpoint = <&funnel0_in_port2>;
0775 };
0776 };
0777 };
0778 };
0779
0780 ptm@0,e3c7f000 {
0781 compatible = "arm,coresight-etm3x", "arm,primecell";
0782 reg = <0 0xe3c7f000 0 0x1000>;
0783
0784 clocks = <&clk_375m>;
0785 clock-names = "apb_pclk";
0786 cpu = <&CPU3>;
0787 out-ports {
0788 port {
0789 ptm3_out_port: endpoint {
0790 remote-endpoint = <&funnel0_in_port3>;
0791 };
0792 };
0793 };
0794 };
0795
0796 ptm@0,e3cbc000 {
0797 compatible = "arm,coresight-etm3x", "arm,primecell";
0798 reg = <0 0xe3cbc000 0 0x1000>;
0799
0800 clocks = <&clk_375m>;
0801 clock-names = "apb_pclk";
0802 cpu = <&CPU4>;
0803 out-ports {
0804 port {
0805 ptm4_out_port: endpoint {
0806 remote-endpoint = <&funnel1_in_port0>;
0807 };
0808 };
0809 };
0810 };
0811
0812 ptm@0,e3cbd000 {
0813 compatible = "arm,coresight-etm3x", "arm,primecell";
0814 reg = <0 0xe3cbd000 0 0x1000>;
0815
0816 clocks = <&clk_375m>;
0817 clock-names = "apb_pclk";
0818 cpu = <&CPU5>;
0819 out-ports {
0820 port {
0821 ptm5_out_port: endpoint {
0822 remote-endpoint = <&funnel1_in_port1>;
0823 };
0824 };
0825 };
0826 };
0827
0828 ptm@0,e3cbe000 {
0829 compatible = "arm,coresight-etm3x", "arm,primecell";
0830 reg = <0 0xe3cbe000 0 0x1000>;
0831
0832 clocks = <&clk_375m>;
0833 clock-names = "apb_pclk";
0834 cpu = <&CPU6>;
0835 out-ports {
0836 port {
0837 ptm6_out_port: endpoint {
0838 remote-endpoint = <&funnel1_in_port2>;
0839 };
0840 };
0841 };
0842 };
0843
0844 ptm@0,e3cbf000 {
0845 compatible = "arm,coresight-etm3x", "arm,primecell";
0846 reg = <0 0xe3cbf000 0 0x1000>;
0847
0848 clocks = <&clk_375m>;
0849 clock-names = "apb_pclk";
0850 cpu = <&CPU7>;
0851 out-ports {
0852 port {
0853 ptm7_out_port: endpoint {
0854 remote-endpoint = <&funnel1_in_port3>;
0855 };
0856 };
0857 };
0858 };
0859
0860 ptm@0,e3cfc000 {
0861 compatible = "arm,coresight-etm3x", "arm,primecell";
0862 reg = <0 0xe3cfc000 0 0x1000>;
0863
0864 clocks = <&clk_375m>;
0865 clock-names = "apb_pclk";
0866 cpu = <&CPU8>;
0867 out-ports {
0868 port {
0869 ptm8_out_port: endpoint {
0870 remote-endpoint = <&funnel2_in_port0>;
0871 };
0872 };
0873 };
0874 };
0875
0876 ptm@0,e3cfd000 {
0877 compatible = "arm,coresight-etm3x", "arm,primecell";
0878 reg = <0 0xe3cfd000 0 0x1000>;
0879 clocks = <&clk_375m>;
0880 clock-names = "apb_pclk";
0881 cpu = <&CPU9>;
0882 out-ports {
0883 port {
0884 ptm9_out_port: endpoint {
0885 remote-endpoint = <&funnel2_in_port1>;
0886 };
0887 };
0888 };
0889 };
0890
0891 ptm@0,e3cfe000 {
0892 compatible = "arm,coresight-etm3x", "arm,primecell";
0893 reg = <0 0xe3cfe000 0 0x1000>;
0894
0895 clocks = <&clk_375m>;
0896 clock-names = "apb_pclk";
0897 cpu = <&CPU10>;
0898 out-ports {
0899 port {
0900 ptm10_out_port: endpoint {
0901 remote-endpoint = <&funnel2_in_port2>;
0902 };
0903 };
0904 };
0905 };
0906
0907 ptm@0,e3cff000 {
0908 compatible = "arm,coresight-etm3x", "arm,primecell";
0909 reg = <0 0xe3cff000 0 0x1000>;
0910
0911 clocks = <&clk_375m>;
0912 clock-names = "apb_pclk";
0913 cpu = <&CPU11>;
0914 out-ports {
0915 port {
0916 ptm11_out_port: endpoint {
0917 remote-endpoint = <&funnel2_in_port3>;
0918 };
0919 };
0920 };
0921 };
0922
0923 ptm@0,e3d3c000 {
0924 compatible = "arm,coresight-etm3x", "arm,primecell";
0925 reg = <0 0xe3d3c000 0 0x1000>;
0926
0927 clocks = <&clk_375m>;
0928 clock-names = "apb_pclk";
0929 cpu = <&CPU12>;
0930 out-ports {
0931 port {
0932 ptm12_out_port: endpoint {
0933 remote-endpoint = <&funnel3_in_port0>;
0934 };
0935 };
0936 };
0937 };
0938
0939 ptm@0,e3d3d000 {
0940 compatible = "arm,coresight-etm3x", "arm,primecell";
0941 reg = <0 0xe3d3d000 0 0x1000>;
0942
0943 clocks = <&clk_375m>;
0944 clock-names = "apb_pclk";
0945 cpu = <&CPU13>;
0946 out-ports {
0947 port {
0948 ptm13_out_port: endpoint {
0949 remote-endpoint = <&funnel3_in_port1>;
0950 };
0951 };
0952 };
0953 };
0954
0955 ptm@0,e3d3e000 {
0956 compatible = "arm,coresight-etm3x", "arm,primecell";
0957 reg = <0 0xe3d3e000 0 0x1000>;
0958
0959 clocks = <&clk_375m>;
0960 clock-names = "apb_pclk";
0961 cpu = <&CPU14>;
0962 out-ports {
0963 port {
0964 ptm14_out_port: endpoint {
0965 remote-endpoint = <&funnel3_in_port2>;
0966 };
0967 };
0968 };
0969 };
0970
0971 ptm@0,e3d3f000 {
0972 compatible = "arm,coresight-etm3x", "arm,primecell";
0973 reg = <0 0xe3d3f000 0 0x1000>;
0974
0975 clocks = <&clk_375m>;
0976 clock-names = "apb_pclk";
0977 cpu = <&CPU15>;
0978 out-ports {
0979 port {
0980 ptm15_out_port: endpoint {
0981 remote-endpoint = <&funnel3_in_port3>;
0982 };
0983 };
0984 };
0985 };
0986 };
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