0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung's Exynos4412 SoC device tree source
0004 *
0005 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
0006 * http://www.samsung.com
0007 *
0008 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
0009 * based board files can include this file and provide values for board specfic
0010 * bindings.
0011 *
0012 * Note: This file does not include device nodes for all the controllers in
0013 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
0014 * nodes can be added to this file.
0015 */
0016
0017 #include "exynos4.dtsi"
0018
0019 #include "exynos4-cpu-thermal.dtsi"
0020
0021 / {
0022 compatible = "samsung,exynos4412", "samsung,exynos4";
0023
0024 aliases {
0025 pinctrl0 = &pinctrl_0;
0026 pinctrl1 = &pinctrl_1;
0027 pinctrl2 = &pinctrl_2;
0028 pinctrl3 = &pinctrl_3;
0029 fimc-lite0 = &fimc_lite_0;
0030 fimc-lite1 = &fimc_lite_1;
0031 mshc0 = &mshc_0;
0032 };
0033
0034 cpus {
0035 #address-cells = <1>;
0036 #size-cells = <0>;
0037
0038 cpu-map {
0039 cluster0 {
0040 core0 {
0041 cpu = <&cpu0>;
0042 };
0043 core1 {
0044 cpu = <&cpu1>;
0045 };
0046 core2 {
0047 cpu = <&cpu2>;
0048 };
0049 core3 {
0050 cpu = <&cpu3>;
0051 };
0052 };
0053 };
0054
0055 cpu0: cpu@a00 {
0056 device_type = "cpu";
0057 compatible = "arm,cortex-a9";
0058 reg = <0xA00>;
0059 clocks = <&clock CLK_ARM_CLK>;
0060 clock-names = "cpu";
0061 operating-points-v2 = <&cpu0_opp_table>;
0062 #cooling-cells = <2>; /* min followed by max */
0063 };
0064
0065 cpu1: cpu@a01 {
0066 device_type = "cpu";
0067 compatible = "arm,cortex-a9";
0068 reg = <0xA01>;
0069 clocks = <&clock CLK_ARM_CLK>;
0070 clock-names = "cpu";
0071 operating-points-v2 = <&cpu0_opp_table>;
0072 #cooling-cells = <2>; /* min followed by max */
0073 };
0074
0075 cpu2: cpu@a02 {
0076 device_type = "cpu";
0077 compatible = "arm,cortex-a9";
0078 reg = <0xA02>;
0079 clocks = <&clock CLK_ARM_CLK>;
0080 clock-names = "cpu";
0081 operating-points-v2 = <&cpu0_opp_table>;
0082 #cooling-cells = <2>; /* min followed by max */
0083 };
0084
0085 cpu3: cpu@a03 {
0086 device_type = "cpu";
0087 compatible = "arm,cortex-a9";
0088 reg = <0xA03>;
0089 clocks = <&clock CLK_ARM_CLK>;
0090 clock-names = "cpu";
0091 operating-points-v2 = <&cpu0_opp_table>;
0092 #cooling-cells = <2>; /* min followed by max */
0093 };
0094 };
0095
0096 cpu0_opp_table: opp-table0 {
0097 compatible = "operating-points-v2";
0098 opp-shared;
0099
0100 opp-200000000 {
0101 opp-hz = /bits/ 64 <200000000>;
0102 opp-microvolt = <900000>;
0103 clock-latency-ns = <200000>;
0104 };
0105 opp-300000000 {
0106 opp-hz = /bits/ 64 <300000000>;
0107 opp-microvolt = <900000>;
0108 clock-latency-ns = <200000>;
0109 };
0110 opp-400000000 {
0111 opp-hz = /bits/ 64 <400000000>;
0112 opp-microvolt = <925000>;
0113 clock-latency-ns = <200000>;
0114 };
0115 opp-500000000 {
0116 opp-hz = /bits/ 64 <500000000>;
0117 opp-microvolt = <950000>;
0118 clock-latency-ns = <200000>;
0119 };
0120 opp-600000000 {
0121 opp-hz = /bits/ 64 <600000000>;
0122 opp-microvolt = <975000>;
0123 clock-latency-ns = <200000>;
0124 };
0125 opp-700000000 {
0126 opp-hz = /bits/ 64 <700000000>;
0127 opp-microvolt = <987500>;
0128 clock-latency-ns = <200000>;
0129 };
0130 opp-800000000 {
0131 opp-hz = /bits/ 64 <800000000>;
0132 opp-microvolt = <1000000>;
0133 clock-latency-ns = <200000>;
0134 opp-suspend;
0135 };
0136 opp-900000000 {
0137 opp-hz = /bits/ 64 <900000000>;
0138 opp-microvolt = <1037500>;
0139 clock-latency-ns = <200000>;
0140 };
0141 opp-1000000000 {
0142 opp-hz = /bits/ 64 <1000000000>;
0143 opp-microvolt = <1087500>;
0144 clock-latency-ns = <200000>;
0145 };
0146 opp-1100000000 {
0147 opp-hz = /bits/ 64 <1100000000>;
0148 opp-microvolt = <1137500>;
0149 clock-latency-ns = <200000>;
0150 };
0151 opp-1200000000 {
0152 opp-hz = /bits/ 64 <1200000000>;
0153 opp-microvolt = <1187500>;
0154 clock-latency-ns = <200000>;
0155 };
0156 opp-1300000000 {
0157 opp-hz = /bits/ 64 <1300000000>;
0158 opp-microvolt = <1250000>;
0159 clock-latency-ns = <200000>;
0160 };
0161 opp-1400000000 {
0162 opp-hz = /bits/ 64 <1400000000>;
0163 opp-microvolt = <1287500>;
0164 clock-latency-ns = <200000>;
0165 };
0166 cpu0_opp_1500: opp-1500000000 {
0167 opp-hz = /bits/ 64 <1500000000>;
0168 opp-microvolt = <1350000>;
0169 clock-latency-ns = <200000>;
0170 turbo-mode;
0171 };
0172 };
0173
0174
0175 soc: soc {
0176
0177 pinctrl_0: pinctrl@11400000 {
0178 compatible = "samsung,exynos4x12-pinctrl";
0179 reg = <0x11400000 0x1000>;
0180 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
0181 };
0182
0183 pinctrl_1: pinctrl@11000000 {
0184 compatible = "samsung,exynos4x12-pinctrl";
0185 reg = <0x11000000 0x1000>;
0186 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0187
0188 wakup_eint: wakeup-interrupt-controller {
0189 compatible = "samsung,exynos4210-wakeup-eint";
0190 interrupt-parent = <&gic>;
0191 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0192 };
0193 };
0194
0195 pinctrl_2: pinctrl@3860000 {
0196 compatible = "samsung,exynos4x12-pinctrl";
0197 reg = <0x03860000 0x1000>;
0198 interrupt-parent = <&combiner>;
0199 interrupts = <10 0>;
0200 };
0201
0202 pinctrl_3: pinctrl@106e0000 {
0203 compatible = "samsung,exynos4x12-pinctrl";
0204 reg = <0x106E0000 0x1000>;
0205 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0206 };
0207
0208 sram@2020000 {
0209 compatible = "mmio-sram";
0210 reg = <0x02020000 0x40000>;
0211 #address-cells = <1>;
0212 #size-cells = <1>;
0213 ranges = <0 0x02020000 0x40000>;
0214
0215 smp-sram@0 {
0216 compatible = "samsung,exynos4210-sysram";
0217 reg = <0x0 0x1000>;
0218 };
0219
0220 smp-sram@2f000 {
0221 compatible = "samsung,exynos4210-sysram-ns";
0222 reg = <0x2f000 0x1000>;
0223 };
0224 };
0225
0226 pd_isp: power-domain@10023ca0 {
0227 compatible = "samsung,exynos4210-pd";
0228 reg = <0x10023CA0 0x20>;
0229 #power-domain-cells = <0>;
0230 label = "ISP";
0231 };
0232
0233 l2c: cache-controller@10502000 {
0234 compatible = "arm,pl310-cache";
0235 reg = <0x10502000 0x1000>;
0236 cache-unified;
0237 cache-level = <2>;
0238 prefetch-data = <1>;
0239 prefetch-instr = <1>;
0240 arm,tag-latency = <2 2 1>;
0241 arm,data-latency = <3 2 1>;
0242 arm,double-linefill = <1>;
0243 arm,double-linefill-incr = <0>;
0244 arm,double-linefill-wrap = <1>;
0245 arm,prefetch-drop = <1>;
0246 arm,prefetch-offset = <7>;
0247 };
0248
0249 clock: clock-controller@10030000 {
0250 compatible = "samsung,exynos4412-clock";
0251 reg = <0x10030000 0x18000>;
0252 #clock-cells = <1>;
0253 };
0254
0255 isp_clock: clock-controller@10048000 {
0256 compatible = "samsung,exynos4412-isp-clock";
0257 reg = <0x10048000 0x1000>;
0258 #clock-cells = <1>;
0259 power-domains = <&pd_isp>;
0260 clocks = <&clock CLK_ACLK200>,
0261 <&clock CLK_ACLK400_MCUISP>;
0262 clock-names = "aclk200", "aclk400_mcuisp";
0263 };
0264
0265 timer@10050000 {
0266 compatible = "samsung,exynos4412-mct";
0267 reg = <0x10050000 0x800>;
0268 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
0269 clock-names = "fin_pll", "mct";
0270 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
0271 <&combiner 12 5>,
0272 <&combiner 12 6>,
0273 <&combiner 12 7>,
0274 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
0275 };
0276
0277 watchdog: watchdog@10060000 {
0278 compatible = "samsung,exynos5250-wdt";
0279 reg = <0x10060000 0x100>;
0280 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
0281 clocks = <&clock CLK_WDT>;
0282 clock-names = "watchdog";
0283 samsung,syscon-phandle = <&pmu_system_controller>;
0284 };
0285
0286 adc: adc@126c0000 {
0287 compatible = "samsung,exynos4212-adc";
0288 reg = <0x126C0000 0x100>;
0289 interrupt-parent = <&combiner>;
0290 interrupts = <10 3>;
0291 clocks = <&clock CLK_TSADC>;
0292 clock-names = "adc";
0293 #io-channel-cells = <1>;
0294 samsung,syscon-phandle = <&pmu_system_controller>;
0295 status = "disabled";
0296 };
0297
0298 g2d: g2d@10800000 {
0299 compatible = "samsung,exynos4212-g2d";
0300 reg = <0x10800000 0x1000>;
0301 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0302 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
0303 clock-names = "sclk_fimg2d", "fimg2d";
0304 iommus = <&sysmmu_g2d>;
0305 };
0306
0307 mshc_0: mmc@12550000 {
0308 compatible = "samsung,exynos4412-dw-mshc";
0309 reg = <0x12550000 0x1000>;
0310 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0311 #address-cells = <1>;
0312 #size-cells = <0>;
0313 fifo-depth = <0x80>;
0314 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
0315 clock-names = "biu", "ciu";
0316 status = "disabled";
0317 };
0318
0319 sysmmu_g2d: sysmmu@10a40000 {
0320 compatible = "samsung,exynos-sysmmu";
0321 reg = <0x10A40000 0x1000>;
0322 interrupt-parent = <&combiner>;
0323 interrupts = <4 7>;
0324 clock-names = "sysmmu", "master";
0325 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
0326 #iommu-cells = <0>;
0327 };
0328
0329 sysmmu_fimc_isp: sysmmu@12260000 {
0330 compatible = "samsung,exynos-sysmmu";
0331 reg = <0x12260000 0x1000>;
0332 interrupt-parent = <&combiner>;
0333 interrupts = <16 2>;
0334 power-domains = <&pd_isp>;
0335 clock-names = "sysmmu";
0336 clocks = <&isp_clock CLK_ISP_SMMU_ISP>;
0337 #iommu-cells = <0>;
0338 };
0339
0340 sysmmu_fimc_drc: sysmmu@12270000 {
0341 compatible = "samsung,exynos-sysmmu";
0342 reg = <0x12270000 0x1000>;
0343 interrupt-parent = <&combiner>;
0344 interrupts = <16 3>;
0345 power-domains = <&pd_isp>;
0346 clock-names = "sysmmu";
0347 clocks = <&isp_clock CLK_ISP_SMMU_DRC>;
0348 #iommu-cells = <0>;
0349 };
0350
0351 sysmmu_fimc_fd: sysmmu@122a0000 {
0352 compatible = "samsung,exynos-sysmmu";
0353 reg = <0x122A0000 0x1000>;
0354 interrupt-parent = <&combiner>;
0355 interrupts = <16 4>;
0356 power-domains = <&pd_isp>;
0357 clock-names = "sysmmu";
0358 clocks = <&isp_clock CLK_ISP_SMMU_FD>;
0359 #iommu-cells = <0>;
0360 };
0361
0362 sysmmu_fimc_mcuctl: sysmmu@122b0000 {
0363 compatible = "samsung,exynos-sysmmu";
0364 reg = <0x122B0000 0x1000>;
0365 interrupt-parent = <&combiner>;
0366 interrupts = <16 5>;
0367 power-domains = <&pd_isp>;
0368 clock-names = "sysmmu";
0369 clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>;
0370 #iommu-cells = <0>;
0371 };
0372
0373 sysmmu_fimc_lite0: sysmmu@123b0000 {
0374 compatible = "samsung,exynos-sysmmu";
0375 reg = <0x123B0000 0x1000>;
0376 interrupt-parent = <&combiner>;
0377 interrupts = <16 0>;
0378 power-domains = <&pd_isp>;
0379 clock-names = "sysmmu", "master";
0380 clocks = <&isp_clock CLK_ISP_SMMU_LITE0>,
0381 <&isp_clock CLK_ISP_FIMC_LITE0>;
0382 #iommu-cells = <0>;
0383 };
0384
0385 sysmmu_fimc_lite1: sysmmu@123c0000 {
0386 compatible = "samsung,exynos-sysmmu";
0387 reg = <0x123C0000 0x1000>;
0388 interrupt-parent = <&combiner>;
0389 interrupts = <16 1>;
0390 power-domains = <&pd_isp>;
0391 clock-names = "sysmmu", "master";
0392 clocks = <&isp_clock CLK_ISP_SMMU_LITE1>,
0393 <&isp_clock CLK_ISP_FIMC_LITE1>;
0394 #iommu-cells = <0>;
0395 };
0396
0397 bus_dmc: bus-dmc {
0398 compatible = "samsung,exynos-bus";
0399 clocks = <&clock CLK_DIV_DMC>;
0400 clock-names = "bus";
0401 operating-points-v2 = <&bus_dmc_opp_table>;
0402 samsung,data-clock-ratio = <4>;
0403 #interconnect-cells = <0>;
0404 status = "disabled";
0405 };
0406
0407 bus_acp: bus-acp {
0408 compatible = "samsung,exynos-bus";
0409 clocks = <&clock CLK_DIV_ACP>;
0410 clock-names = "bus";
0411 operating-points-v2 = <&bus_acp_opp_table>;
0412 status = "disabled";
0413 };
0414
0415 bus_c2c: bus-c2c {
0416 compatible = "samsung,exynos-bus";
0417 clocks = <&clock CLK_DIV_C2C>;
0418 clock-names = "bus";
0419 operating-points-v2 = <&bus_dmc_opp_table>;
0420 status = "disabled";
0421 };
0422
0423 bus_dmc_opp_table: opp-table1 {
0424 compatible = "operating-points-v2";
0425
0426 opp-100000000 {
0427 opp-hz = /bits/ 64 <100000000>;
0428 opp-microvolt = <900000>;
0429 };
0430 opp-134000000 {
0431 opp-hz = /bits/ 64 <134000000>;
0432 opp-microvolt = <900000>;
0433 };
0434 opp-160000000 {
0435 opp-hz = /bits/ 64 <160000000>;
0436 opp-microvolt = <900000>;
0437 };
0438 opp-267000000 {
0439 opp-hz = /bits/ 64 <267000000>;
0440 opp-microvolt = <950000>;
0441 };
0442 opp-400000000 {
0443 opp-hz = /bits/ 64 <400000000>;
0444 opp-microvolt = <1050000>;
0445 opp-suspend;
0446 };
0447 };
0448
0449 bus_acp_opp_table: opp-table2 {
0450 compatible = "operating-points-v2";
0451
0452 opp-100000000 {
0453 opp-hz = /bits/ 64 <100000000>;
0454 };
0455 opp-134000000 {
0456 opp-hz = /bits/ 64 <134000000>;
0457 };
0458 opp-160000000 {
0459 opp-hz = /bits/ 64 <160000000>;
0460 };
0461 opp-267000000 {
0462 opp-hz = /bits/ 64 <267000000>;
0463 };
0464 };
0465
0466 bus_leftbus: bus-leftbus {
0467 compatible = "samsung,exynos-bus";
0468 clocks = <&clock CLK_DIV_GDL>;
0469 clock-names = "bus";
0470 operating-points-v2 = <&bus_leftbus_opp_table>;
0471 interconnects = <&bus_dmc>;
0472 #interconnect-cells = <0>;
0473 status = "disabled";
0474 };
0475
0476 bus_rightbus: bus-rightbus {
0477 compatible = "samsung,exynos-bus";
0478 clocks = <&clock CLK_DIV_GDR>;
0479 clock-names = "bus";
0480 operating-points-v2 = <&bus_leftbus_opp_table>;
0481 status = "disabled";
0482 };
0483
0484 bus_display: bus-display {
0485 compatible = "samsung,exynos-bus";
0486 clocks = <&clock CLK_ACLK160>;
0487 clock-names = "bus";
0488 operating-points-v2 = <&bus_display_opp_table>;
0489 interconnects = <&bus_leftbus &bus_dmc>;
0490 #interconnect-cells = <0>;
0491 status = "disabled";
0492 };
0493
0494 bus_fsys: bus-fsys {
0495 compatible = "samsung,exynos-bus";
0496 clocks = <&clock CLK_ACLK133>;
0497 clock-names = "bus";
0498 operating-points-v2 = <&bus_fsys_opp_table>;
0499 status = "disabled";
0500 };
0501
0502 bus_peri: bus-peri {
0503 compatible = "samsung,exynos-bus";
0504 clocks = <&clock CLK_ACLK100>;
0505 clock-names = "bus";
0506 operating-points-v2 = <&bus_peri_opp_table>;
0507 status = "disabled";
0508 };
0509
0510 bus_mfc: bus-mfc {
0511 compatible = "samsung,exynos-bus";
0512 clocks = <&clock CLK_SCLK_MFC>;
0513 clock-names = "bus";
0514 operating-points-v2 = <&bus_leftbus_opp_table>;
0515 status = "disabled";
0516 };
0517
0518 bus_leftbus_opp_table: opp-table3 {
0519 compatible = "operating-points-v2";
0520
0521 opp-100000000 {
0522 opp-hz = /bits/ 64 <100000000>;
0523 opp-microvolt = <900000>;
0524 };
0525 opp-134000000 {
0526 opp-hz = /bits/ 64 <134000000>;
0527 opp-microvolt = <925000>;
0528 };
0529 opp-160000000 {
0530 opp-hz = /bits/ 64 <160000000>;
0531 opp-microvolt = <950000>;
0532 };
0533 opp-200000000 {
0534 opp-hz = /bits/ 64 <200000000>;
0535 opp-microvolt = <1000000>;
0536 opp-suspend;
0537 };
0538 };
0539
0540 bus_display_opp_table: opp-table4 {
0541 compatible = "operating-points-v2";
0542
0543 opp-160000000 {
0544 opp-hz = /bits/ 64 <160000000>;
0545 };
0546 opp-200000000 {
0547 opp-hz = /bits/ 64 <200000000>;
0548 };
0549 };
0550
0551 bus_fsys_opp_table: opp-table5 {
0552 compatible = "operating-points-v2";
0553
0554 opp-100000000 {
0555 opp-hz = /bits/ 64 <100000000>;
0556 };
0557 opp-134000000 {
0558 opp-hz = /bits/ 64 <134000000>;
0559 };
0560 };
0561
0562 bus_peri_opp_table: opp-table6 {
0563 compatible = "operating-points-v2";
0564
0565 opp-50000000 {
0566 opp-hz = /bits/ 64 <50000000>;
0567 };
0568 opp-100000000 {
0569 opp-hz = /bits/ 64 <100000000>;
0570 };
0571 };
0572 };
0573 };
0574
0575 &combiner {
0576 samsung,combiner-nr = <20>;
0577 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0578 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0579 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0580 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0581 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0582 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0583 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0584 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0585 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0586 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0587 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0588 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0589 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0590 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0591 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0592 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0593 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
0594 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
0595 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
0596 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0597 };
0598
0599 &camera {
0600 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
0601 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
0602 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
0603
0604 /* fimc_[0-3] are configured outside, under phandles */
0605 fimc_lite_0: fimc-lite@12390000 {
0606 compatible = "samsung,exynos4212-fimc-lite";
0607 reg = <0x12390000 0x1000>;
0608 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0609 power-domains = <&pd_isp>;
0610 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
0611 clock-names = "flite";
0612 iommus = <&sysmmu_fimc_lite0>;
0613 status = "disabled";
0614 };
0615
0616 fimc_lite_1: fimc-lite@123a0000 {
0617 compatible = "samsung,exynos4212-fimc-lite";
0618 reg = <0x123A0000 0x1000>;
0619 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0620 power-domains = <&pd_isp>;
0621 clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
0622 clock-names = "flite";
0623 iommus = <&sysmmu_fimc_lite1>;
0624 status = "disabled";
0625 };
0626
0627 fimc_is: fimc-is@12000000 {
0628 compatible = "samsung,exynos4212-fimc-is";
0629 reg = <0x12000000 0x260000>;
0630 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
0631 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0632 power-domains = <&pd_isp>;
0633 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
0634 <&isp_clock CLK_ISP_FIMC_LITE1>,
0635 <&isp_clock CLK_ISP_PPMUISPX>,
0636 <&isp_clock CLK_ISP_PPMUISPMX>,
0637 <&isp_clock CLK_ISP_FIMC_ISP>,
0638 <&isp_clock CLK_ISP_FIMC_DRC>,
0639 <&isp_clock CLK_ISP_FIMC_FD>,
0640 <&isp_clock CLK_ISP_MCUISP>,
0641 <&isp_clock CLK_ISP_GICISP>,
0642 <&isp_clock CLK_ISP_MCUCTL_ISP>,
0643 <&isp_clock CLK_ISP_PWM_ISP>,
0644 <&isp_clock CLK_ISP_DIV_ISP0>,
0645 <&isp_clock CLK_ISP_DIV_ISP1>,
0646 <&isp_clock CLK_ISP_DIV_MCUISP0>,
0647 <&isp_clock CLK_ISP_DIV_MCUISP1>,
0648 <&clock CLK_MOUT_MPLL_USER_T>,
0649 <&clock CLK_ACLK200>,
0650 <&clock CLK_ACLK400_MCUISP>,
0651 <&clock CLK_DIV_ACLK200>,
0652 <&clock CLK_DIV_ACLK400_MCUISP>,
0653 <&clock CLK_UART_ISP_SCLK>;
0654 clock-names = "lite0", "lite1", "ppmuispx",
0655 "ppmuispmx", "isp",
0656 "drc", "fd", "mcuisp",
0657 "gicisp", "mcuctl_isp", "pwm_isp",
0658 "ispdiv0", "ispdiv1", "mcuispdiv0",
0659 "mcuispdiv1", "mpll", "aclk200",
0660 "aclk400mcuisp", "div_aclk200",
0661 "div_aclk400mcuisp", "uart";
0662 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
0663 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
0664 iommu-names = "isp", "drc", "fd", "mcuctl";
0665 #address-cells = <1>;
0666 #size-cells = <1>;
0667 ranges;
0668 status = "disabled";
0669
0670 pmu@10020000 {
0671 reg = <0x10020000 0x3000>;
0672 };
0673
0674 i2c1_isp: i2c-isp@12140000 {
0675 compatible = "samsung,exynos4212-i2c-isp";
0676 reg = <0x12140000 0x100>;
0677 clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
0678 clock-names = "i2c_isp";
0679 #address-cells = <1>;
0680 #size-cells = <0>;
0681 };
0682 };
0683 };
0684
0685 &exynos_usbphy {
0686 compatible = "samsung,exynos4x12-usb2-phy";
0687 samsung,sysreg-phandle = <&sys_reg>;
0688 };
0689
0690 &fimc_0 {
0691 compatible = "samsung,exynos4212-fimc";
0692 samsung,pix-limits = <4224 8192 1920 4224>;
0693 samsung,mainscaler-ext;
0694 samsung,isp-wb;
0695 samsung,cam-if;
0696 };
0697
0698 &fimc_1 {
0699 compatible = "samsung,exynos4212-fimc";
0700 samsung,pix-limits = <4224 8192 1920 4224>;
0701 samsung,mainscaler-ext;
0702 samsung,isp-wb;
0703 samsung,cam-if;
0704 };
0705
0706 &fimc_2 {
0707 compatible = "samsung,exynos4212-fimc";
0708 samsung,pix-limits = <4224 8192 1920 4224>;
0709 samsung,mainscaler-ext;
0710 samsung,isp-wb;
0711 samsung,lcd-wb;
0712 samsung,cam-if;
0713 };
0714
0715 &fimc_3 {
0716 compatible = "samsung,exynos4212-fimc";
0717 samsung,pix-limits = <1920 8192 1366 1920>;
0718 samsung,rotators = <0>;
0719 samsung,mainscaler-ext;
0720 samsung,isp-wb;
0721 samsung,lcd-wb;
0722 };
0723
0724 &gic {
0725 cpu-offset = <0x4000>;
0726 };
0727
0728 &gpu {
0729 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
0730 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
0731 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
0732 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
0733 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
0734 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
0735 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
0736 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0737 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
0738 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
0739 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0740 interrupt-names = "gp",
0741 "gpmmu",
0742 "pp0",
0743 "ppmmu0",
0744 "pp1",
0745 "ppmmu1",
0746 "pp2",
0747 "ppmmu2",
0748 "pp3",
0749 "ppmmu3",
0750 "pmu";
0751 operating-points-v2 = <&gpu_opp_table>;
0752
0753 gpu_opp_table: opp-table {
0754 compatible = "operating-points-v2";
0755
0756 opp-160000000 {
0757 opp-hz = /bits/ 64 <160000000>;
0758 opp-microvolt = <875000>;
0759 };
0760 opp-267000000 {
0761 opp-hz = /bits/ 64 <267000000>;
0762 opp-microvolt = <900000>;
0763 };
0764 opp-350000000 {
0765 opp-hz = /bits/ 64 <350000000>;
0766 opp-microvolt = <950000>;
0767 };
0768 opp-440000000 {
0769 opp-hz = /bits/ 64 <440000000>;
0770 opp-microvolt = <1025000>;
0771 };
0772 };
0773 };
0774
0775 &hdmi {
0776 compatible = "samsung,exynos4212-hdmi";
0777 };
0778
0779 &jpeg_codec {
0780 compatible = "samsung,exynos4212-jpeg";
0781 };
0782
0783 &rotator {
0784 compatible = "samsung,exynos4212-rotator";
0785 };
0786
0787 &mixer {
0788 compatible = "samsung,exynos4212-mixer";
0789 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
0790 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
0791 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
0792 interconnects = <&bus_display &bus_dmc>;
0793 };
0794
0795 &pmu {
0796 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
0797 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0798 status = "okay";
0799 };
0800
0801 &pmu_system_controller {
0802 compatible = "samsung,exynos4412-pmu", "syscon";
0803 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
0804 "clkout4", "clkout8", "clkout9";
0805 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
0806 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
0807 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
0808 #clock-cells = <1>;
0809 };
0810
0811 &tmu {
0812 compatible = "samsung,exynos4412-tmu";
0813 interrupt-parent = <&combiner>;
0814 interrupts = <2 4>;
0815 reg = <0x100C0000 0x100>;
0816 clocks = <&clock CLK_TMU_APBIF>;
0817 clock-names = "tmu_apbif";
0818 status = "disabled";
0819 };
0820
0821 #include "exynos4412-pinctrl.dtsi"
