0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <dt-bindings/interrupt-controller/arm-gic.h>
0003
0004 / {
0005 #address-cells = <2>;
0006 #size-cells = <2>;
0007 model = "Broadcom STB (bcm7445)";
0008 compatible = "brcm,bcm7445", "brcm,brcmstb";
0009 interrupt-parent = <&gic>;
0010
0011 chosen {
0012 bootargs = "console=ttyS0,115200 earlyprintk";
0013 };
0014
0015 cpus {
0016 #address-cells = <1>;
0017 #size-cells = <0>;
0018
0019 cpu@0 {
0020 compatible = "brcm,brahma-b15";
0021 device_type = "cpu";
0022 enable-method = "brcm,brahma-b15";
0023 reg = <0>;
0024 };
0025
0026 cpu@1 {
0027 compatible = "brcm,brahma-b15";
0028 device_type = "cpu";
0029 enable-method = "brcm,brahma-b15";
0030 reg = <1>;
0031 };
0032
0033 cpu@2 {
0034 compatible = "brcm,brahma-b15";
0035 device_type = "cpu";
0036 enable-method = "brcm,brahma-b15";
0037 reg = <2>;
0038 };
0039
0040 cpu@3 {
0041 compatible = "brcm,brahma-b15";
0042 device_type = "cpu";
0043 enable-method = "brcm,brahma-b15";
0044 reg = <3>;
0045 };
0046 };
0047
0048 gic: interrupt-controller@ffd00000 {
0049 compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic";
0050 reg = <0x00 0xffd01000 0x00 0x1000>,
0051 <0x00 0xffd02000 0x00 0x2000>,
0052 <0x00 0xffd04000 0x00 0x2000>,
0053 <0x00 0xffd06000 0x00 0x2000>;
0054 interrupt-controller;
0055 #interrupt-cells = <3>;
0056 };
0057
0058 timer {
0059 compatible = "arm,armv7-timer";
0060 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
0061 <GIC_PPI 14 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
0062 <GIC_PPI 11 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
0063 <GIC_PPI 10 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
0064 };
0065
0066 rdb@f0000000 {
0067 #address-cells = <1>;
0068 #size-cells = <1>;
0069 compatible = "simple-bus";
0070 ranges = <0 0x00 0xf0000000 0x1000000>;
0071
0072 serial@40ab00 {
0073 compatible = "ns16550a";
0074 reg = <0x40ab00 0x20>;
0075 reg-shift = <2>;
0076 reg-io-width = <4>;
0077 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0078 clock-frequency = <81000000>;
0079 };
0080
0081 sun_top_ctrl: syscon@404000 {
0082 compatible = "brcm,bcm7445-sun-top-ctrl",
0083 "syscon";
0084 reg = <0x404000 0x51c>;
0085 };
0086
0087 hif_cpubiuctrl: syscon@3e2400 {
0088 compatible = "brcm,bcm7445-hif-cpubiuctrl",
0089 "syscon";
0090 reg = <0x3e2400 0x5b4>;
0091 };
0092
0093 hif_continuation: syscon@452000 {
0094 compatible = "brcm,bcm7445-hif-continuation",
0095 "syscon";
0096 reg = <0x452000 0x100>;
0097 };
0098
0099 irq0_intc: interrupt-controller@40a780 {
0100 compatible = "brcm,bcm7120-l2-intc";
0101 interrupt-parent = <&gic>;
0102 #interrupt-cells = <1>;
0103 reg = <0x40a780 0x8>;
0104 interrupt-controller;
0105 interrupts = <GIC_SPI 0x45 0x0>,
0106 <GIC_SPI 0x43 0x0>;
0107 brcm,int-map-mask = <0x25c>, <0x7000000>;
0108 brcm,int-fwd-mask = <0x70000>;
0109 };
0110
0111 irq0_aon_intc: interrupt-controller@417280 {
0112 compatible = "brcm,bcm7120-l2-intc";
0113 reg = <0x417280 0x8>;
0114 interrupt-parent = <&gic>;
0115 #interrupt-cells = <1>;
0116 interrupt-controller;
0117 interrupts = <GIC_SPI 0x46 0x0>,
0118 <GIC_SPI 0x44 0x0>,
0119 <GIC_SPI 0x49 0x0>;
0120 brcm,int-map-mask = <0x1e3 0x18000000 0x100000>;
0121 brcm,int-fwd-mask = <0x0>;
0122 brcm,irq-can-wake;
0123 };
0124
0125 hif_intr2_intc: interrupt-controller@3e1000 {
0126 compatible = "brcm,l2-intc";
0127 reg = <0x3e1000 0x30>;
0128 interrupt-controller;
0129 #interrupt-cells = <1>;
0130 interrupts = <GIC_SPI 0x20 0x0>;
0131 interrupt-parent = <&gic>;
0132 interrupt-names = "hif";
0133 };
0134
0135 aon_pm_l2_intc: interrupt-controller@410640 {
0136 compatible = "brcm,l2-intc";
0137 reg = <0x410640 0x30>;
0138 interrupt-controller;
0139 #interrupt-cells = <1>;
0140 interrupts = <GIC_SPI 0x40 0x0>;
0141 interrupt-parent = <&gic>;
0142 brcm,irq-can-wake;
0143 };
0144
0145 aon-ctrl@410000 {
0146 compatible = "brcm,brcmstb-aon-ctrl";
0147 reg = <0x410000 0x200>, <0x410200 0x400>;
0148 reg-names = "aon-ctrl", "aon-sram";
0149 };
0150
0151 nand_controller: nand-controller@3e2800 {
0152 status = "disabled";
0153 #address-cells = <1>;
0154 #size-cells = <0>;
0155 compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand";
0156 reg-names = "nand", "flash-dma";
0157 reg = <0x3e2800 0x600>, <0x3e3000 0x2c>;
0158 interrupt-parent = <&hif_intr2_intc>;
0159 interrupts = <24>, <4>;
0160 interrupt-names = "nand_ctlrdy", "flash_dma_done";
0161 };
0162
0163 sata@45a000 {
0164 compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
0165 reg-names = "ahci", "top-ctrl";
0166 reg = <0x45a000 0xa9c>, <0x458040 0x24>;
0167 interrupts = <GIC_SPI 30 0>;
0168 #address-cells = <1>;
0169 #size-cells = <0>;
0170
0171 sata0: sata-port@0 {
0172 reg = <0>;
0173 phys = <&sata_phy0>;
0174 };
0175
0176 sata1: sata-port@1 {
0177 reg = <1>;
0178 phys = <&sata_phy1>;
0179 };
0180 };
0181
0182 sata_phy: sata-phy@458100 {
0183 compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3";
0184 reg = <0x458100 0x1f00>;
0185 reg-names = "phy";
0186 #address-cells = <0x1>;
0187 #size-cells = <0x0>;
0188
0189 sata_phy0: sata-phy@0 {
0190 reg = <0>;
0191 #phy-cells = <0>;
0192 };
0193
0194 sata_phy1: sata-phy@1 {
0195 reg = <1>;
0196 #phy-cells = <0>;
0197 };
0198 };
0199
0200 upg_gio: gpio@40a700 {
0201 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
0202 reg = <0x40a700 0x80>;
0203 #gpio-cells = <2>;
0204 #interrupt-cells = <2>;
0205 gpio-controller;
0206 interrupt-controller;
0207 interrupt-parent = <&irq0_intc>;
0208 interrupts = <6>;
0209 brcm,gpio-bank-widths = <32 32 32 24>;
0210 };
0211
0212 upg_gio_aon: gpio@4172c0 {
0213 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
0214 reg = <0x4172c0 0x40>;
0215 #gpio-cells = <2>;
0216 #interrupt-cells = <2>;
0217 gpio-controller;
0218 interrupt-controller;
0219 interrupts-extended = <&irq0_aon_intc 0x6>,
0220 <&aon_pm_l2_intc 0x5>;
0221 wakeup-source;
0222 brcm,gpio-bank-widths = <18 4>;
0223 };
0224
0225 };
0226
0227 memory_controllers@f1100000 {
0228 compatible = "simple-bus";
0229 ranges = <0x0 0x0 0xf1100000 0x200000>;
0230 #address-cells = <1>;
0231 #size-cells = <1>;
0232
0233 memc@0 {
0234 compatible = "brcm,brcmstb-memc", "simple-bus";
0235 #address-cells = <1>;
0236 #size-cells = <1>;
0237 ranges = <0x0 0x0 0x80000>;
0238
0239 memc-ddr@2000 {
0240 compatible = "brcm,brcmstb-memc-ddr";
0241 reg = <0x2000 0x800>;
0242 };
0243
0244 ddr-phy@6000 {
0245 compatible = "brcm,brcmstb-ddr-phy-v240.1";
0246 reg = <0x6000 0x21c>;
0247 };
0248
0249 shimphy@8000 {
0250 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
0251 reg = <0x8000 0xe4>;
0252 };
0253 };
0254
0255 memc@80000 {
0256 compatible = "brcm,brcmstb-memc", "simple-bus";
0257 #address-cells = <1>;
0258 #size-cells = <1>;
0259 ranges = <0x0 0x80000 0x80000>;
0260
0261 memc-ddr@2000 {
0262 compatible = "brcm,brcmstb-memc-ddr";
0263 reg = <0x2000 0x800>;
0264 };
0265
0266 ddr-phy@6000 {
0267 compatible = "brcm,brcmstb-ddr-phy-v240.1";
0268 reg = <0x6000 0x21c>;
0269 };
0270
0271 shimphy@8000 {
0272 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
0273 reg = <0x8000 0xe4>;
0274 };
0275 };
0276
0277 memc@100000 {
0278 compatible = "brcm,brcmstb-memc", "simple-bus";
0279 #address-cells = <1>;
0280 #size-cells = <1>;
0281 ranges = <0x0 0x100000 0x80000>;
0282
0283 memc-ddr@2000 {
0284 compatible = "brcm,brcmstb-memc-ddr";
0285 reg = <0x2000 0x800>;
0286 };
0287
0288 ddr-phy@6000 {
0289 compatible = "brcm,brcmstb-ddr-phy-v240.1";
0290 reg = <0x6000 0x21c>;
0291 };
0292
0293 shimphy@8000 {
0294 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
0295 reg = <0x8000 0xe4>;
0296 };
0297 };
0298 };
0299
0300 sram@ffe00000 {
0301 compatible = "brcm,boot-sram", "mmio-sram";
0302 reg = <0x0 0xffe00000 0x0 0x10000>;
0303 };
0304
0305 smpboot {
0306 compatible = "brcm,brcmstb-smpboot";
0307 syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
0308 syscon-cont = <&hif_continuation>;
0309 };
0310
0311 reboot {
0312 compatible = "brcm,brcmstb-reboot";
0313 syscon = <&sun_top_ctrl 0x304 0x308>;
0314 };
0315 };
