0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2022 Broadcom Ltd.
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/interrupt-controller/irq.h>
0008
0009 / {
0010 compatible = "brcm,bcm6846", "brcm,bcmbca";
0011 #address-cells = <1>;
0012 #size-cells = <1>;
0013
0014 interrupt-parent = <&gic>;
0015
0016 cpus {
0017 #address-cells = <1>;
0018 #size-cells = <0>;
0019
0020 CA7_0: cpu@0 {
0021 device_type = "cpu";
0022 compatible = "arm,cortex-a7";
0023 reg = <0x0>;
0024 next-level-cache = <&L2_0>;
0025 enable-method = "psci";
0026 };
0027
0028 CA7_1: cpu@1 {
0029 device_type = "cpu";
0030 compatible = "arm,cortex-a7";
0031 reg = <0x1>;
0032 next-level-cache = <&L2_0>;
0033 enable-method = "psci";
0034 };
0035
0036 L2_0: l2-cache0 {
0037 compatible = "cache";
0038 };
0039 };
0040
0041 timer {
0042 compatible = "arm,armv7-timer";
0043 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0044 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0045 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0046 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
0047 arm,cpu-registers-not-fw-configured;
0048 };
0049
0050 pmu: pmu {
0051 compatible = "arm,cortex-a7-pmu";
0052 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0053 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0054 interrupt-affinity = <&CA7_0>, <&CA7_1>;
0055 };
0056
0057 clocks: clocks {
0058 periph_clk: periph-clk {
0059 compatible = "fixed-clock";
0060 #clock-cells = <0>;
0061 clock-frequency = <200000000>;
0062 };
0063 };
0064
0065 psci {
0066 compatible = "arm,psci-0.2";
0067 method = "smc";
0068 };
0069
0070 axi@81000000 {
0071 compatible = "simple-bus";
0072 #address-cells = <1>;
0073 #size-cells = <1>;
0074 ranges = <0 0x81000000 0x8000>;
0075
0076 gic: interrupt-controller@1000 {
0077 compatible = "arm,cortex-a7-gic";
0078 #interrupt-cells = <3>;
0079 interrupt-controller;
0080 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
0081 reg = <0x1000 0x1000>,
0082 <0x2000 0x2000>,
0083 <0x4000 0x2000>,
0084 <0x6000 0x2000>;
0085 };
0086 };
0087
0088 bus@ff800000 {
0089 compatible = "simple-bus";
0090 #address-cells = <1>;
0091 #size-cells = <1>;
0092 ranges = <0 0xff800000 0x800000>;
0093
0094 uart0: serial@640 {
0095 compatible = "brcm,bcm6345-uart";
0096 reg = <0x640 0x1b>;
0097 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0098 clocks = <&periph_clk>;
0099 clock-names = "refclk";
0100 status = "disabled";
0101 };
0102 };
0103 };
