0001 #include "bcm283x.dtsi"
0002 #include "bcm2835-common.dtsi"
0003 #include "bcm2835-rpi-common.dtsi"
0004
0005 / {
0006 compatible = "brcm,bcm2837";
0007
0008 soc {
0009 ranges = <0x7e000000 0x3f000000 0x1000000>,
0010 <0x40000000 0x40000000 0x00001000>;
0011 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
0012
0013 local_intc: local_intc@40000000 {
0014 compatible = "brcm,bcm2836-l1-intc";
0015 reg = <0x40000000 0x100>;
0016 interrupt-controller;
0017 #interrupt-cells = <2>;
0018 interrupt-parent = <&local_intc>;
0019 };
0020 };
0021
0022 arm-pmu {
0023 compatible = "arm,cortex-a53-pmu";
0024 interrupt-parent = <&local_intc>;
0025 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
0026 };
0027
0028 timer {
0029 compatible = "arm,armv7-timer";
0030 interrupt-parent = <&local_intc>;
0031 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
0032 <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
0033 <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
0034 <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
0035 always-on;
0036 };
0037
0038 cpus: cpus {
0039 #address-cells = <1>;
0040 #size-cells = <0>;
0041 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
0042
0043 /* Source for d/i-cache-line-size and d/i-cache-sets
0044 * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
0045 * /about-the-l1-memory-system?lang=en
0046 *
0047 * Source for d/i-cache-size
0048 * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
0049 */
0050 cpu0: cpu@0 {
0051 device_type = "cpu";
0052 compatible = "arm,cortex-a53";
0053 reg = <0>;
0054 enable-method = "spin-table";
0055 cpu-release-addr = <0x0 0x000000d8>;
0056 d-cache-size = <0x8000>;
0057 d-cache-line-size = <64>;
0058 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
0059 i-cache-size = <0x8000>;
0060 i-cache-line-size = <64>;
0061 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
0062 next-level-cache = <&l2>;
0063 };
0064
0065 cpu1: cpu@1 {
0066 device_type = "cpu";
0067 compatible = "arm,cortex-a53";
0068 reg = <1>;
0069 enable-method = "spin-table";
0070 cpu-release-addr = <0x0 0x000000e0>;
0071 d-cache-size = <0x8000>;
0072 d-cache-line-size = <64>;
0073 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
0074 i-cache-size = <0x8000>;
0075 i-cache-line-size = <64>;
0076 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
0077 next-level-cache = <&l2>;
0078 };
0079
0080 cpu2: cpu@2 {
0081 device_type = "cpu";
0082 compatible = "arm,cortex-a53";
0083 reg = <2>;
0084 enable-method = "spin-table";
0085 cpu-release-addr = <0x0 0x000000e8>;
0086 d-cache-size = <0x8000>;
0087 d-cache-line-size = <64>;
0088 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
0089 i-cache-size = <0x8000>;
0090 i-cache-line-size = <64>;
0091 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
0092 next-level-cache = <&l2>;
0093 };
0094
0095 cpu3: cpu@3 {
0096 device_type = "cpu";
0097 compatible = "arm,cortex-a53";
0098 reg = <3>;
0099 enable-method = "spin-table";
0100 cpu-release-addr = <0x0 0x000000f0>;
0101 d-cache-size = <0x8000>;
0102 d-cache-line-size = <64>;
0103 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
0104 i-cache-size = <0x8000>;
0105 i-cache-line-size = <64>;
0106 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
0107 next-level-cache = <&l2>;
0108 };
0109
0110 /* Source for cache-line-size + cache-sets
0111 * https://developer.arm.com/documentation/ddi0500
0112 * /e/level-2-memory-system/about-the-l2-memory-system?lang=en
0113 * Source for cache-size
0114 * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf
0115 */
0116 l2: l2-cache0 {
0117 compatible = "cache";
0118 cache-size = <0x80000>;
0119 cache-line-size = <64>;
0120 cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
0121 cache-level = <2>;
0122 };
0123 };
0124 };
0125
0126 /* Make the BCM2835-style global interrupt controller be a child of the
0127 * CPU-local interrupt controller.
0128 */
0129 &intc {
0130 compatible = "brcm,bcm2836-armctrl-ic";
0131 reg = <0x7e00b200 0x200>;
0132 interrupt-parent = <&local_intc>;
0133 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
0134 };
0135
0136 &cpu_thermal {
0137 coefficients = <(-538) 412000>;
0138 };
0139
0140 /* enable thermal sensor with the correct compatible property set */
0141 &thermal {
0142 compatible = "brcm,bcm2837-thermal";
0143 status = "okay";
0144 };
