0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for AM33xx clock data
0004 *
0005 * Copyright (C) 2013 Texas Instruments, Inc.
0006 */
0007 &scm_clocks {
0008 sys_clkin_ck: clock-sys-clkin-22@40 {
0009 #clock-cells = <0>;
0010 compatible = "ti,mux-clock";
0011 clock-output-names = "sys_clkin_ck";
0012 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
0013 ti,bit-shift = <22>;
0014 reg = <0x0040>;
0015 };
0016
0017 adc_tsc_fck: clock-adc-tsc-fck {
0018 #clock-cells = <0>;
0019 compatible = "fixed-factor-clock";
0020 clock-output-names = "adc_tsc_fck";
0021 clocks = <&sys_clkin_ck>;
0022 clock-mult = <1>;
0023 clock-div = <1>;
0024 };
0025
0026 dcan0_fck: clock-dcan0-fck {
0027 #clock-cells = <0>;
0028 compatible = "fixed-factor-clock";
0029 clock-output-names = "dcan0_fck";
0030 clocks = <&sys_clkin_ck>;
0031 clock-mult = <1>;
0032 clock-div = <1>;
0033 };
0034
0035 dcan1_fck: clock-dcan1-fck {
0036 #clock-cells = <0>;
0037 compatible = "fixed-factor-clock";
0038 clock-output-names = "dcan1_fck";
0039 clocks = <&sys_clkin_ck>;
0040 clock-mult = <1>;
0041 clock-div = <1>;
0042 };
0043
0044 mcasp0_fck: clock-mcasp0-fck {
0045 #clock-cells = <0>;
0046 compatible = "fixed-factor-clock";
0047 clock-output-names = "mcasp0_fck";
0048 clocks = <&sys_clkin_ck>;
0049 clock-mult = <1>;
0050 clock-div = <1>;
0051 };
0052
0053 mcasp1_fck: clock-mcasp1-fck {
0054 #clock-cells = <0>;
0055 compatible = "fixed-factor-clock";
0056 clock-output-names = "mcasp1_fck";
0057 clocks = <&sys_clkin_ck>;
0058 clock-mult = <1>;
0059 clock-div = <1>;
0060 };
0061
0062 smartreflex0_fck: clock-smartreflex0-fck {
0063 #clock-cells = <0>;
0064 compatible = "fixed-factor-clock";
0065 clock-output-names = "smartreflex0_fck";
0066 clocks = <&sys_clkin_ck>;
0067 clock-mult = <1>;
0068 clock-div = <1>;
0069 };
0070
0071 smartreflex1_fck: clock-smartreflex1-fck {
0072 #clock-cells = <0>;
0073 compatible = "fixed-factor-clock";
0074 clock-output-names = "smartreflex1_fck";
0075 clocks = <&sys_clkin_ck>;
0076 clock-mult = <1>;
0077 clock-div = <1>;
0078 };
0079
0080 sha0_fck: clock-sha0-fck {
0081 #clock-cells = <0>;
0082 compatible = "fixed-factor-clock";
0083 clock-output-names = "sha0_fck";
0084 clocks = <&sys_clkin_ck>;
0085 clock-mult = <1>;
0086 clock-div = <1>;
0087 };
0088
0089 aes0_fck: clock-aes0-fck {
0090 #clock-cells = <0>;
0091 compatible = "fixed-factor-clock";
0092 clock-output-names = "aes0_fck";
0093 clocks = <&sys_clkin_ck>;
0094 clock-mult = <1>;
0095 clock-div = <1>;
0096 };
0097
0098 rng_fck: clock-rng-fck {
0099 #clock-cells = <0>;
0100 compatible = "fixed-factor-clock";
0101 clock-output-names = "rng_fck";
0102 clocks = <&sys_clkin_ck>;
0103 clock-mult = <1>;
0104 clock-div = <1>;
0105 };
0106
0107 clock@664 {
0108 compatible = "ti,clksel";
0109 reg = <0x664>;
0110 #clock-cells = <2>;
0111 #address-cells = <0>;
0112
0113 ehrpwm0_tbclk: clock-ehrpwm0-tbclk {
0114 #clock-cells = <0>;
0115 compatible = "ti,gate-clock";
0116 clock-output-names = "ehrpwm0_tbclk";
0117 clocks = <&l4ls_gclk>;
0118 ti,bit-shift = <0>;
0119 };
0120
0121 ehrpwm1_tbclk: clock-ehrpwm1-tbclk {
0122 #clock-cells = <0>;
0123 compatible = "ti,gate-clock";
0124 clock-output-names = "ehrpwm1_tbclk";
0125 clocks = <&l4ls_gclk>;
0126 ti,bit-shift = <1>;
0127 };
0128
0129 ehrpwm2_tbclk: clock-ehrpwm2-tbclk {
0130 #clock-cells = <0>;
0131 compatible = "ti,gate-clock";
0132 clock-output-names = "ehrpwm2_tbclk";
0133 clocks = <&l4ls_gclk>;
0134 ti,bit-shift = <2>;
0135 };
0136 };
0137 };
0138 &prcm_clocks {
0139 clk_32768_ck: clock-clk-32768 {
0140 #clock-cells = <0>;
0141 compatible = "fixed-clock";
0142 clock-output-names = "clk_32768_ck";
0143 clock-frequency = <32768>;
0144 };
0145
0146 clk_rc32k_ck: clock-clk-rc32k {
0147 #clock-cells = <0>;
0148 compatible = "fixed-clock";
0149 clock-output-names = "clk_rc32k_ck";
0150 clock-frequency = <32000>;
0151 };
0152
0153 virt_19200000_ck: clock-virt-19200000 {
0154 #clock-cells = <0>;
0155 compatible = "fixed-clock";
0156 clock-output-names = "virt_19200000_ck";
0157 clock-frequency = <19200000>;
0158 };
0159
0160 virt_24000000_ck: clock-virt-24000000 {
0161 #clock-cells = <0>;
0162 compatible = "fixed-clock";
0163 clock-output-names = "virt_24000000_ck";
0164 clock-frequency = <24000000>;
0165 };
0166
0167 virt_25000000_ck: clock-virt-25000000 {
0168 #clock-cells = <0>;
0169 compatible = "fixed-clock";
0170 clock-output-names = "virt_25000000_ck";
0171 clock-frequency = <25000000>;
0172 };
0173
0174 virt_26000000_ck: clock-virt-26000000 {
0175 #clock-cells = <0>;
0176 compatible = "fixed-clock";
0177 clock-output-names = "virt_26000000_ck";
0178 clock-frequency = <26000000>;
0179 };
0180
0181 tclkin_ck: clock-tclkin {
0182 #clock-cells = <0>;
0183 compatible = "fixed-clock";
0184 clock-output-names = "tclkin_ck";
0185 clock-frequency = <12000000>;
0186 };
0187
0188 dpll_core_ck: clock@490 {
0189 #clock-cells = <0>;
0190 compatible = "ti,am3-dpll-core-clock";
0191 clock-output-names = "dpll_core_ck";
0192 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
0193 reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
0194 };
0195
0196 dpll_core_x2_ck: clock-dpll-core-x2 {
0197 #clock-cells = <0>;
0198 compatible = "ti,am3-dpll-x2-clock";
0199 clock-output-names = "dpll_core_x2_ck";
0200 clocks = <&dpll_core_ck>;
0201 };
0202
0203 dpll_core_m4_ck: clock-dpll-core-m4@480 {
0204 #clock-cells = <0>;
0205 compatible = "ti,divider-clock";
0206 clock-output-names = "dpll_core_m4_ck";
0207 clocks = <&dpll_core_x2_ck>;
0208 ti,max-div = <31>;
0209 reg = <0x0480>;
0210 ti,index-starts-at-one;
0211 };
0212
0213 dpll_core_m5_ck: clock-dpll-core-m5@484 {
0214 #clock-cells = <0>;
0215 compatible = "ti,divider-clock";
0216 clock-output-names = "dpll_core_m5_ck";
0217 clocks = <&dpll_core_x2_ck>;
0218 ti,max-div = <31>;
0219 reg = <0x0484>;
0220 ti,index-starts-at-one;
0221 };
0222
0223 dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
0224 #clock-cells = <0>;
0225 compatible = "ti,divider-clock";
0226 clock-output-names = "dpll_core_m6_ck";
0227 clocks = <&dpll_core_x2_ck>;
0228 ti,max-div = <31>;
0229 reg = <0x04d8>;
0230 ti,index-starts-at-one;
0231 };
0232
0233 dpll_mpu_ck: clock@488 {
0234 #clock-cells = <0>;
0235 compatible = "ti,am3-dpll-clock";
0236 clock-output-names = "dpll_mpu_ck";
0237 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
0238 reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
0239 };
0240
0241 dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
0242 #clock-cells = <0>;
0243 compatible = "ti,divider-clock";
0244 clock-output-names = "dpll_mpu_m2_ck";
0245 clocks = <&dpll_mpu_ck>;
0246 ti,max-div = <31>;
0247 reg = <0x04a8>;
0248 ti,index-starts-at-one;
0249 };
0250
0251 dpll_ddr_ck: clock@494 {
0252 #clock-cells = <0>;
0253 compatible = "ti,am3-dpll-no-gate-clock";
0254 clock-output-names = "dpll_ddr_ck";
0255 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
0256 reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
0257 };
0258
0259 dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
0260 #clock-cells = <0>;
0261 compatible = "ti,divider-clock";
0262 clock-output-names = "dpll_ddr_m2_ck";
0263 clocks = <&dpll_ddr_ck>;
0264 ti,max-div = <31>;
0265 reg = <0x04a0>;
0266 ti,index-starts-at-one;
0267 };
0268
0269 dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 {
0270 #clock-cells = <0>;
0271 compatible = "fixed-factor-clock";
0272 clock-output-names = "dpll_ddr_m2_div2_ck";
0273 clocks = <&dpll_ddr_m2_ck>;
0274 clock-mult = <1>;
0275 clock-div = <2>;
0276 };
0277
0278 dpll_disp_ck: clock@498 {
0279 #clock-cells = <0>;
0280 compatible = "ti,am3-dpll-no-gate-clock";
0281 clock-output-names = "dpll_disp_ck";
0282 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
0283 reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
0284 };
0285
0286 dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 {
0287 #clock-cells = <0>;
0288 compatible = "ti,divider-clock";
0289 clock-output-names = "dpll_disp_m2_ck";
0290 clocks = <&dpll_disp_ck>;
0291 ti,max-div = <31>;
0292 reg = <0x04a4>;
0293 ti,index-starts-at-one;
0294 ti,set-rate-parent;
0295 };
0296
0297 dpll_per_ck: clock@48c {
0298 #clock-cells = <0>;
0299 compatible = "ti,am3-dpll-no-gate-j-type-clock";
0300 clock-output-names = "dpll_per_ck";
0301 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
0302 reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
0303 };
0304
0305 dpll_per_m2_ck: clock-dpll-per-m2@4ac {
0306 #clock-cells = <0>;
0307 compatible = "ti,divider-clock";
0308 clock-output-names = "dpll_per_m2_ck";
0309 clocks = <&dpll_per_ck>;
0310 ti,max-div = <31>;
0311 reg = <0x04ac>;
0312 ti,index-starts-at-one;
0313 };
0314
0315 dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
0316 #clock-cells = <0>;
0317 compatible = "fixed-factor-clock";
0318 clock-output-names = "dpll_per_m2_div4_wkupdm_ck";
0319 clocks = <&dpll_per_m2_ck>;
0320 clock-mult = <1>;
0321 clock-div = <4>;
0322 };
0323
0324 dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
0325 #clock-cells = <0>;
0326 compatible = "fixed-factor-clock";
0327 clock-output-names = "dpll_per_m2_div4_ck";
0328 clocks = <&dpll_per_m2_ck>;
0329 clock-mult = <1>;
0330 clock-div = <4>;
0331 };
0332
0333 clk_24mhz: clock-clk-24mhz {
0334 #clock-cells = <0>;
0335 compatible = "fixed-factor-clock";
0336 clock-output-names = "clk_24mhz";
0337 clocks = <&dpll_per_m2_ck>;
0338 clock-mult = <1>;
0339 clock-div = <8>;
0340 };
0341
0342 clkdiv32k_ck: clock-clkdiv32k {
0343 #clock-cells = <0>;
0344 compatible = "fixed-factor-clock";
0345 clock-output-names = "clkdiv32k_ck";
0346 clocks = <&clk_24mhz>;
0347 clock-mult = <1>;
0348 clock-div = <732>;
0349 };
0350
0351 l3_gclk: clock-l3-gclk {
0352 #clock-cells = <0>;
0353 compatible = "fixed-factor-clock";
0354 clock-output-names = "l3_gclk";
0355 clocks = <&dpll_core_m4_ck>;
0356 clock-mult = <1>;
0357 clock-div = <1>;
0358 };
0359
0360 pruss_ocp_gclk: clock-pruss-ocp-gclk@530 {
0361 #clock-cells = <0>;
0362 compatible = "ti,mux-clock";
0363 clock-output-names = "pruss_ocp_gclk";
0364 clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
0365 reg = <0x0530>;
0366 };
0367
0368 mmu_fck: clock-mmu-fck-1@914 {
0369 #clock-cells = <0>;
0370 compatible = "ti,gate-clock";
0371 clock-output-names = "mmu_fck";
0372 clocks = <&dpll_core_m4_ck>;
0373 ti,bit-shift = <1>;
0374 reg = <0x0914>;
0375 };
0376
0377 timer1_fck: clock-timer1-fck@528 {
0378 #clock-cells = <0>;
0379 compatible = "ti,mux-clock";
0380 clock-output-names = "timer1_fck";
0381 clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
0382 reg = <0x0528>;
0383 };
0384
0385 timer2_fck: clock-timer2-fck@508 {
0386 #clock-cells = <0>;
0387 compatible = "ti,mux-clock";
0388 clock-output-names = "timer2_fck";
0389 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
0390 reg = <0x0508>;
0391 };
0392
0393 timer3_fck: clock-timer3-fck@50c {
0394 #clock-cells = <0>;
0395 compatible = "ti,mux-clock";
0396 clock-output-names = "timer3_fck";
0397 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
0398 reg = <0x050c>;
0399 };
0400
0401 timer4_fck: clock-timer4-fck@510 {
0402 #clock-cells = <0>;
0403 compatible = "ti,mux-clock";
0404 clock-output-names = "timer4_fck";
0405 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
0406 reg = <0x0510>;
0407 };
0408
0409 timer5_fck: clock-timer5-fck@518 {
0410 #clock-cells = <0>;
0411 compatible = "ti,mux-clock";
0412 clock-output-names = "timer5_fck";
0413 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
0414 reg = <0x0518>;
0415 };
0416
0417 timer6_fck: clock-timer6-fck@51c {
0418 #clock-cells = <0>;
0419 compatible = "ti,mux-clock";
0420 clock-output-names = "timer6_fck";
0421 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
0422 reg = <0x051c>;
0423 };
0424
0425 timer7_fck: clock-timer7-fck@504 {
0426 #clock-cells = <0>;
0427 compatible = "ti,mux-clock";
0428 clock-output-names = "timer7_fck";
0429 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
0430 reg = <0x0504>;
0431 };
0432
0433 usbotg_fck: clock-usbotg-fck-8@47c {
0434 #clock-cells = <0>;
0435 compatible = "ti,gate-clock";
0436 clock-output-names = "usbotg_fck";
0437 clocks = <&dpll_per_ck>;
0438 ti,bit-shift = <8>;
0439 reg = <0x047c>;
0440 };
0441
0442 dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
0443 #clock-cells = <0>;
0444 compatible = "fixed-factor-clock";
0445 clock-output-names = "dpll_core_m4_div2_ck";
0446 clocks = <&dpll_core_m4_ck>;
0447 clock-mult = <1>;
0448 clock-div = <2>;
0449 };
0450
0451 ieee5000_fck: clock-ieee5000-fck-1@e4 {
0452 #clock-cells = <0>;
0453 compatible = "ti,gate-clock";
0454 clock-output-names = "ieee5000_fck";
0455 clocks = <&dpll_core_m4_div2_ck>;
0456 ti,bit-shift = <1>;
0457 reg = <0x00e4>;
0458 };
0459
0460 wdt1_fck: clock-wdt1-fck@538 {
0461 #clock-cells = <0>;
0462 compatible = "ti,mux-clock";
0463 clock-output-names = "wdt1_fck";
0464 clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
0465 reg = <0x0538>;
0466 };
0467
0468 l4_rtc_gclk: clock-l4-rtc-gclk {
0469 #clock-cells = <0>;
0470 compatible = "fixed-factor-clock";
0471 clock-output-names = "l4_rtc_gclk";
0472 clocks = <&dpll_core_m4_ck>;
0473 clock-mult = <1>;
0474 clock-div = <2>;
0475 };
0476
0477 l4hs_gclk: clock-l4hs-gclk {
0478 #clock-cells = <0>;
0479 compatible = "fixed-factor-clock";
0480 clock-output-names = "l4hs_gclk";
0481 clocks = <&dpll_core_m4_ck>;
0482 clock-mult = <1>;
0483 clock-div = <1>;
0484 };
0485
0486 l3s_gclk: clock-l3s-gclk {
0487 #clock-cells = <0>;
0488 compatible = "fixed-factor-clock";
0489 clock-output-names = "l3s_gclk";
0490 clocks = <&dpll_core_m4_div2_ck>;
0491 clock-mult = <1>;
0492 clock-div = <1>;
0493 };
0494
0495 l4fw_gclk: clock-l4fw-gclk {
0496 #clock-cells = <0>;
0497 compatible = "fixed-factor-clock";
0498 clock-output-names = "l4fw_gclk";
0499 clocks = <&dpll_core_m4_div2_ck>;
0500 clock-mult = <1>;
0501 clock-div = <1>;
0502 };
0503
0504 l4ls_gclk: clock-l4ls-gclk {
0505 #clock-cells = <0>;
0506 compatible = "fixed-factor-clock";
0507 clock-output-names = "l4ls_gclk";
0508 clocks = <&dpll_core_m4_div2_ck>;
0509 clock-mult = <1>;
0510 clock-div = <1>;
0511 };
0512
0513 sysclk_div_ck: clock-sysclk-div {
0514 #clock-cells = <0>;
0515 compatible = "fixed-factor-clock";
0516 clock-output-names = "sysclk_div_ck";
0517 clocks = <&dpll_core_m4_ck>;
0518 clock-mult = <1>;
0519 clock-div = <1>;
0520 };
0521
0522 cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
0523 #clock-cells = <0>;
0524 compatible = "fixed-factor-clock";
0525 clock-output-names = "cpsw_125mhz_gclk";
0526 clocks = <&dpll_core_m5_ck>;
0527 clock-mult = <1>;
0528 clock-div = <2>;
0529 };
0530
0531 cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 {
0532 #clock-cells = <0>;
0533 compatible = "ti,mux-clock";
0534 clock-output-names = "cpsw_cpts_rft_clk";
0535 clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
0536 reg = <0x0520>;
0537 };
0538
0539 gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c {
0540 #clock-cells = <0>;
0541 compatible = "ti,mux-clock";
0542 clock-output-names = "gpio0_dbclk_mux_ck";
0543 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
0544 reg = <0x053c>;
0545 };
0546
0547 lcd_gclk: clock-lcd-gclk@534 {
0548 #clock-cells = <0>;
0549 compatible = "ti,mux-clock";
0550 clock-output-names = "lcd_gclk";
0551 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
0552 reg = <0x0534>;
0553 ti,set-rate-parent;
0554 };
0555
0556 mmc_clk: clock-mmc {
0557 #clock-cells = <0>;
0558 compatible = "fixed-factor-clock";
0559 clock-output-names = "mmc_clk";
0560 clocks = <&dpll_per_m2_ck>;
0561 clock-mult = <1>;
0562 clock-div = <2>;
0563 };
0564
0565 clock@52c {
0566 compatible = "ti,clksel";
0567 reg = <0x52c>;
0568 #clock-cells = <2>;
0569 #address-cells = <0>;
0570
0571 gfx_fclk_clksel_ck: clock-gfx-fclk-clksel {
0572 #clock-cells = <0>;
0573 compatible = "ti,mux-clock";
0574 clock-output-names = "gfx_fclk_clksel_ck";
0575 clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
0576 ti,bit-shift = <1>;
0577 };
0578
0579 gfx_fck_div_ck: clock-gfx-fck-div {
0580 #clock-cells = <0>;
0581 compatible = "ti,divider-clock";
0582 clock-output-names = "gfx_fck_div_ck";
0583 clocks = <&gfx_fclk_clksel_ck>;
0584 ti,max-div = <2>;
0585 };
0586 };
0587
0588 clock@700 {
0589 compatible = "ti,clksel";
0590 reg = <0x700>;
0591 #clock-cells = <2>;
0592 #address-cells = <0>;
0593
0594 sysclkout_pre_ck: clock-sysclkout-pre {
0595 #clock-cells = <0>;
0596 compatible = "ti,mux-clock";
0597 clock-output-names = "sysclkout_pre_ck";
0598 clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
0599 };
0600
0601 clkout2_div_ck: clock-clkout2-div {
0602 #clock-cells = <0>;
0603 compatible = "ti,divider-clock";
0604 clock-output-names = "clkout2_div_ck";
0605 clocks = <&sysclkout_pre_ck>;
0606 ti,bit-shift = <3>;
0607 ti,max-div = <8>;
0608 };
0609
0610 clkout2_ck: clock-clkout2 {
0611 #clock-cells = <0>;
0612 compatible = "ti,gate-clock";
0613 clock-output-names = "clkout2_ck";
0614 clocks = <&clkout2_div_ck>;
0615 ti,bit-shift = <7>;
0616 };
0617 };
0618 };
0619
0620 &prcm {
0621 per_cm: clock@0 {
0622 compatible = "ti,omap4-cm";
0623 clock-output-names = "per_cm";
0624 reg = <0x0 0x400>;
0625 #address-cells = <1>;
0626 #size-cells = <1>;
0627 ranges = <0 0x0 0x400>;
0628
0629 l4ls_clkctrl: clock@38 {
0630 compatible = "ti,clkctrl";
0631 clock-output-names = "l4ls_clkctrl";
0632 reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
0633 #clock-cells = <2>;
0634 };
0635
0636 l3s_clkctrl: clock@1c {
0637 compatible = "ti,clkctrl";
0638 clock-output-names = "l3s_clkctrl";
0639 reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
0640 #clock-cells = <2>;
0641 };
0642
0643 l3_clkctrl: clock@24 {
0644 compatible = "ti,clkctrl";
0645 clock-output-names = "l3_clkctrl";
0646 reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
0647 #clock-cells = <2>;
0648 };
0649
0650 l4hs_clkctrl: clock@120 {
0651 compatible = "ti,clkctrl";
0652 clock-output-names = "l4hs_clkctrl";
0653 reg = <0x120 0x4>;
0654 #clock-cells = <2>;
0655 };
0656
0657 pruss_ocp_clkctrl: clock@e8 {
0658 compatible = "ti,clkctrl";
0659 clock-output-names = "pruss_ocp_clkctrl";
0660 reg = <0xe8 0x4>;
0661 #clock-cells = <2>;
0662 };
0663
0664 cpsw_125mhz_clkctrl: clock@0 {
0665 compatible = "ti,clkctrl";
0666 clock-output-names = "cpsw_125mhz_clkctrl";
0667 reg = <0x0 0x18>;
0668 #clock-cells = <2>;
0669 };
0670
0671 lcdc_clkctrl: clock@18 {
0672 compatible = "ti,clkctrl";
0673 clock-output-names = "lcdc_clkctrl";
0674 reg = <0x18 0x4>;
0675 #clock-cells = <2>;
0676 };
0677
0678 clk_24mhz_clkctrl: clock@14c {
0679 compatible = "ti,clkctrl";
0680 clock-output-names = "clk_24mhz_clkctrl";
0681 reg = <0x14c 0x4>;
0682 #clock-cells = <2>;
0683 };
0684 };
0685
0686 wkup_cm: clock@400 {
0687 compatible = "ti,omap4-cm";
0688 clock-output-names = "wkup_cm";
0689 reg = <0x400 0x100>;
0690 #address-cells = <1>;
0691 #size-cells = <1>;
0692 ranges = <0 0x400 0x100>;
0693
0694 l4_wkup_clkctrl: clock@0 {
0695 compatible = "ti,clkctrl";
0696 clock-output-names = "l4_wkup_clkctrl";
0697 reg = <0x0 0x10>, <0xb4 0x24>;
0698 #clock-cells = <2>;
0699 };
0700
0701 l3_aon_clkctrl: clock@14 {
0702 compatible = "ti,clkctrl";
0703 clock-output-names = "l3_aon_clkctrl";
0704 reg = <0x14 0x4>;
0705 #clock-cells = <2>;
0706 };
0707
0708 l4_wkup_aon_clkctrl: clock@b0 {
0709 compatible = "ti,clkctrl";
0710 clock-output-names = "l4_wkup_aon_clkctrl";
0711 reg = <0xb0 0x4>;
0712 #clock-cells = <2>;
0713 };
0714 };
0715
0716 mpu_cm: clock@600 {
0717 compatible = "ti,omap4-cm";
0718 clock-output-names = "mpu_cm";
0719 reg = <0x600 0x100>;
0720 #address-cells = <1>;
0721 #size-cells = <1>;
0722 ranges = <0 0x600 0x100>;
0723
0724 mpu_clkctrl: clock@0 {
0725 compatible = "ti,clkctrl";
0726 clock-output-names = "mpu_clkctrl";
0727 reg = <0x0 0x8>;
0728 #clock-cells = <2>;
0729 };
0730 };
0731
0732 l4_rtc_cm: clock@800 {
0733 compatible = "ti,omap4-cm";
0734 clock-output-names = "l4_rtc_cm";
0735 reg = <0x800 0x100>;
0736 #address-cells = <1>;
0737 #size-cells = <1>;
0738 ranges = <0 0x800 0x100>;
0739
0740 l4_rtc_clkctrl: clock@0 {
0741 compatible = "ti,clkctrl";
0742 clock-output-names = "l4_rtc_clkctrl";
0743 reg = <0x0 0x4>;
0744 #clock-cells = <2>;
0745 };
0746 };
0747
0748 gfx_l3_cm: clock@900 {
0749 compatible = "ti,omap4-cm";
0750 clock-output-names = "gfx_l3_cm";
0751 reg = <0x900 0x100>;
0752 #address-cells = <1>;
0753 #size-cells = <1>;
0754 ranges = <0 0x900 0x100>;
0755
0756 gfx_l3_clkctrl: clock@0 {
0757 compatible = "ti,clkctrl";
0758 clock-output-names = "gfx_l3_clkctrl";
0759 reg = <0x0 0x8>;
0760 #clock-cells = <2>;
0761 };
0762 };
0763
0764 l4_cefuse_cm: clock@a00 {
0765 compatible = "ti,omap4-cm";
0766 clock-output-names = "l4_cefuse_cm";
0767 reg = <0xa00 0x100>;
0768 #address-cells = <1>;
0769 #size-cells = <1>;
0770 ranges = <0 0xa00 0x100>;
0771
0772 l4_cefuse_clkctrl: clock@0 {
0773 compatible = "ti,clkctrl";
0774 clock-output-names = "l4_cefuse_clkctrl";
0775 reg = <0x0 0x24>;
0776 #clock-cells = <2>;
0777 };
0778 };
0779 };
