0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Support for peripherals on the AXS10x mainboard (VDK version)
0004 *
0005 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
0006 */
0007
0008 / {
0009 axs10x_mb_vdk {
0010 compatible = "simple-bus";
0011 #address-cells = <1>;
0012 #size-cells = <1>;
0013 ranges = <0x00000000 0xe0000000 0x10000000>;
0014 interrupt-parent = <&mb_intc>;
0015
0016 clocks {
0017 apbclk: apbclk {
0018 compatible = "fixed-clock";
0019 clock-frequency = <50000000>;
0020 #clock-cells = <0>;
0021 };
0022
0023 mmcclk: mmcclk {
0024 compatible = "fixed-clock";
0025 clock-frequency = <50000000>;
0026 #clock-cells = <0>;
0027 };
0028
0029 pguclk: pguclk {
0030 #clock-cells = <0>;
0031 compatible = "fixed-clock";
0032 clock-frequency = <25175000>;
0033 };
0034 };
0035
0036 ethernet@18000 {
0037 #interrupt-cells = <1>;
0038 compatible = "snps,dwmac";
0039 reg = < 0x18000 0x2000 >;
0040 interrupts = < 4 >;
0041 interrupt-names = "macirq";
0042 phy-mode = "rgmii";
0043 snps,phy-addr = < 0 >; // VDK model phy address is 0
0044 snps,pbl = < 32 >;
0045 clocks = <&apbclk>;
0046 clock-names = "stmmaceth";
0047 };
0048
0049 ehci@40000 {
0050 compatible = "generic-ehci";
0051 reg = < 0x40000 0x100 >;
0052 interrupts = < 8 >;
0053 };
0054
0055 uart@20000 {
0056 compatible = "snps,dw-apb-uart";
0057 reg = <0x20000 0x100>;
0058 clock-frequency = <2403200>;
0059 interrupts = <17>;
0060 baud = <115200>;
0061 reg-shift = <2>;
0062 reg-io-width = <4>;
0063 };
0064
0065 uart@21000 {
0066 compatible = "snps,dw-apb-uart";
0067 reg = <0x21000 0x100>;
0068 clock-frequency = <2403200>;
0069 interrupts = <18>;
0070 baud = <115200>;
0071 reg-shift = <2>;
0072 reg-io-width = <4>;
0073 };
0074
0075 uart@22000 {
0076 compatible = "snps,dw-apb-uart";
0077 reg = <0x22000 0x100>;
0078 clock-frequency = <2403200>;
0079 interrupts = <19>;
0080 baud = <115200>;
0081 reg-shift = <2>;
0082 reg-io-width = <4>;
0083 };
0084
0085 /* PGU output directly sent to virtual LCD screen; hdmi controller not modelled */
0086 pgu@17000 {
0087 compatible = "snps,arcpgu";
0088 reg = <0x17000 0x400>;
0089 clocks = <&pguclk>;
0090 clock-names = "pxlclk";
0091 };
0092
0093 /* VDK has additional ps2 keyboard/mouse interface integrated in LCD screen model */
0094 ps2: ps2@e0017400 {
0095 compatible = "snps,arc_ps2";
0096 reg = <0x17400 0x14>;
0097 interrupts = <5>;
0098 interrupt-names = "arc_ps2_irq";
0099 };
0100
0101 mmc@15000 {
0102 compatible = "snps,dw-mshc";
0103 reg = <0x15000 0x400>;
0104 fifo-depth = <1024>;
0105 card-detect-delay = <200>;
0106 clocks = <&apbclk>, <&mmcclk>;
0107 clock-names = "biu", "ciu";
0108 interrupts = <7>;
0109 bus-width = <4>;
0110 };
0111 };
0112
0113 /*
0114 * Embedded Vision subsystem UIO mappings; only relevant for EV VDK
0115 *
0116 * This node is intentionally put outside of MB above becase
0117 * it maps areas outside of MB's 0xez-0xfz.
0118 */
0119 uio_ev: uio@d0000000 {
0120 compatible = "generic-uio";
0121 reg = <0xd0000000 0x2000 0xd1000000 0x2000 0x90000000 0x10000000 0xc0000000 0x10000000>;
0122 reg-names = "ev_gsa", "ev_ctrl", "ev_shared_mem", "ev_code_mem";
0123 interrupt-parent = <&mb_intc>;
0124 interrupts = <23>;
0125 };
0126 };
