0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
0004 */
0005
0006 /*
0007 * Device tree for AXC003 CPU card:
0008 * HS38x2 (Dual Core) with IDU intc (VDK version)
0009 */
0010
0011 /include/ "skeleton_hs_idu.dtsi"
0012
0013 / {
0014 compatible = "snps,arc";
0015 #address-cells = <1>;
0016 #size-cells = <1>;
0017
0018 cpu_card {
0019 compatible = "simple-bus";
0020 #address-cells = <1>;
0021 #size-cells = <1>;
0022
0023 ranges = <0x00000000 0xf0000000 0x10000000>;
0024
0025 core_clk: core_clk {
0026 #clock-cells = <0>;
0027 compatible = "fixed-clock";
0028 clock-frequency = <50000000>;
0029 };
0030
0031 core_intc: archs-intc@cpu {
0032 compatible = "snps,archs-intc";
0033 interrupt-controller;
0034 #interrupt-cells = <1>;
0035 };
0036
0037 idu_intc: idu-interrupt-controller {
0038 compatible = "snps,archs-idu-intc";
0039 interrupt-controller;
0040 interrupt-parent = <&core_intc>;
0041 #interrupt-cells = <1>;
0042 };
0043
0044 debug_uart: dw-apb-uart@5000 {
0045 compatible = "snps,dw-apb-uart";
0046 reg = <0x5000 0x100>;
0047 clock-frequency = <2403200>;
0048 interrupt-parent = <&idu_intc>;
0049 interrupts = <2>;
0050 baud = <115200>;
0051 reg-shift = <2>;
0052 reg-io-width = <4>;
0053 };
0054
0055 };
0056
0057 mb_intc: interrupt-controller@e0012000 {
0058 #interrupt-cells = <1>;
0059 compatible = "snps,dw-apb-ictl";
0060 reg = < 0xe0012000 0x200 >;
0061 interrupt-controller;
0062 interrupt-parent = <&idu_intc>;
0063 interrupts = <0>;
0064 };
0065
0066 memory {
0067 #address-cells = <1>;
0068 #size-cells = <1>;
0069 ranges = <0x00000000 0x80000000 0x40000000>;
0070 device_type = "memory";
0071 reg = <0x80000000 0x20000000>; /* 512MiB */
0072 };
0073 };
