0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2013, 2014 Synopsys, Inc. (www.synopsys.com)
0004 */
0005
0006 /*
0007 * Device tree for AXC003 CPU card: HS38x UP configuration (VDK version)
0008 */
0009
0010 /include/ "skeleton_hs.dtsi"
0011
0012 / {
0013 compatible = "snps,arc";
0014 #address-cells = <1>;
0015 #size-cells = <1>;
0016
0017 cpu_card {
0018 compatible = "simple-bus";
0019 #address-cells = <1>;
0020 #size-cells = <1>;
0021
0022 ranges = <0x00000000 0xf0000000 0x10000000>;
0023
0024 core_clk: core_clk {
0025 #clock-cells = <0>;
0026 compatible = "fixed-clock";
0027 clock-frequency = <50000000>;
0028 };
0029
0030 core_intc: archs-intc@cpu {
0031 compatible = "snps,archs-intc";
0032 interrupt-controller;
0033 #interrupt-cells = <1>;
0034 };
0035
0036 debug_uart: dw-apb-uart@5000 {
0037 compatible = "snps,dw-apb-uart";
0038 reg = <0x5000 0x100>;
0039 clock-frequency = <2403200>;
0040 interrupt-parent = <&core_intc>;
0041 interrupts = <19>;
0042 baud = <115200>;
0043 reg-shift = <2>;
0044 reg-io-width = <4>;
0045 };
0046
0047 };
0048
0049 mb_intc: interrupt-controller@e0012000 {
0050 #interrupt-cells = <1>;
0051 compatible = "snps,dw-apb-ictl";
0052 reg = < 0xe0012000 0x200 >;
0053 interrupt-controller;
0054 interrupt-parent = <&core_intc>;
0055 interrupts = < 18 >;
0056 };
0057
0058 memory {
0059 #address-cells = <1>;
0060 #size-cells = <1>;
0061 ranges = <0x00000000 0x80000000 0x40000000>;
0062 device_type = "memory";
0063 reg = <0x80000000 0x20000000>; /* 512MiB */
0064 };
0065 };
