0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
0004 */
0005 /dts-v1/;
0006
0007 /include/ "skeleton_hs_idu.dtsi"
0008
0009 / {
0010 model = "snps,nsimosci_hs-smp";
0011 compatible = "snps,nsimosci_hs";
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 interrupt-parent = <&core_intc>;
0015
0016 chosen {
0017 /* this is for console on serial */
0018 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24 print-fatal-signals=1";
0019 };
0020
0021 aliases {
0022 serial0 = &uart0;
0023 };
0024
0025 fpga {
0026 compatible = "simple-bus";
0027 #address-cells = <1>;
0028 #size-cells = <1>;
0029
0030 /* child and parent address space 1:1 mapped */
0031 ranges;
0032
0033 core_clk: core_clk {
0034 #clock-cells = <0>;
0035 compatible = "fixed-clock";
0036 clock-frequency = <5000000>;
0037 };
0038
0039 core_intc: core-interrupt-controller {
0040 compatible = "snps,archs-intc";
0041 interrupt-controller;
0042 #interrupt-cells = <1>;
0043 };
0044
0045 idu_intc: idu-interrupt-controller {
0046 compatible = "snps,archs-idu-intc";
0047 interrupt-controller;
0048 interrupt-parent = <&core_intc>;
0049 #interrupt-cells = <1>;
0050 };
0051
0052 uart0: serial@f0000000 {
0053 compatible = "ns8250";
0054 reg = <0xf0000000 0x2000>;
0055 interrupt-parent = <&idu_intc>;
0056 interrupts = <0>;
0057 clock-frequency = <3686400>;
0058 baud = <115200>;
0059 reg-shift = <2>;
0060 reg-io-width = <4>;
0061 no-loopback-test = <1>;
0062 };
0063
0064 pguclk: pguclk {
0065 #clock-cells = <0>;
0066 compatible = "fixed-clock";
0067 clock-frequency = <25175000>;
0068 };
0069
0070 pgu@f9000000 {
0071 compatible = "snps,arcpgu";
0072 reg = <0xf9000000 0x400>;
0073 clocks = <&pguclk>;
0074 clock-names = "pxlclk";
0075 };
0076
0077 ps2: ps2@f9001000 {
0078 compatible = "snps,arc_ps2";
0079 reg = <0xf9000400 0x14>;
0080 interrupts = <3>;
0081 interrupt-parent = <&idu_intc>;
0082 interrupt-names = "arc_ps2_irq";
0083 };
0084
0085 eth0: ethernet@f0003000 {
0086 compatible = "ezchip,nps-mgt-enet";
0087 reg = <0xf0003000 0x44>;
0088 interrupt-parent = <&idu_intc>;
0089 interrupts = <1>;
0090 };
0091
0092 arcpct0: pct {
0093 compatible = "snps,archs-pct";
0094 #interrupt-cells = <1>;
0095 interrupts = <20>;
0096 };
0097 };
0098 };
