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OSCL-LXR

 
 

    


0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
0004  */
0005 /dts-v1/;
0006 
0007 /include/ "skeleton_hs.dtsi"
0008 
0009 / {
0010         model = "snps,nsimosci_hs";
0011         compatible = "snps,nsimosci_hs";
0012         #address-cells = <1>;
0013         #size-cells = <1>;
0014         interrupt-parent = <&core_intc>;
0015 
0016         chosen {
0017                 /* this is for console on PGU */
0018                 /* bootargs = "console=tty0 consoleblank=0"; */
0019                 /* this is for console on serial */
0020                 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1";
0021         };
0022 
0023         aliases {
0024                 serial0 = &uart0;
0025         };
0026 
0027         fpga {
0028                 compatible = "simple-bus";
0029                 #address-cells = <1>;
0030                 #size-cells = <1>;
0031 
0032                 /* child and parent address space 1:1 mapped */
0033                 ranges;
0034 
0035                 core_clk: core_clk {
0036                         #clock-cells = <0>;
0037                         compatible = "fixed-clock";
0038                         clock-frequency = <20000000>;
0039                 };
0040 
0041                 core_intc: core-interrupt-controller {
0042                         compatible = "snps,archs-intc";
0043                         interrupt-controller;
0044                         #interrupt-cells = <1>;
0045                 };
0046 
0047                 uart0: serial@f0000000 {
0048                         compatible = "ns8250";
0049                         reg = <0xf0000000 0x2000>;
0050                         interrupts = <24>;
0051                         clock-frequency = <3686400>;
0052                         baud = <115200>;
0053                         reg-shift = <2>;
0054                         reg-io-width = <4>;
0055                         no-loopback-test = <1>;
0056                 };
0057 
0058                 pguclk: pguclk {
0059                         #clock-cells = <0>;
0060                         compatible = "fixed-clock";
0061                         clock-frequency = <25175000>;
0062                 };
0063 
0064                 pgu@f9000000 {
0065                         compatible = "snps,arcpgu";
0066                         reg = <0xf9000000 0x400>;
0067                         clocks = <&pguclk>;
0068                         clock-names = "pxlclk";
0069                 };
0070 
0071                 ps2: ps2@f9001000 {
0072                         compatible = "snps,arc_ps2";
0073                         reg = <0xf9000400 0x14>;
0074                         interrupts = <27>;
0075                         interrupt-names = "arc_ps2_irq";
0076                 };
0077 
0078                 eth0: ethernet@f0003000 {
0079                         compatible = "ezchip,nps-mgt-enet";
0080                         reg = <0xf0003000 0x44>;
0081                         interrupts = <25>;
0082                 };
0083 
0084                 arcpct0: pct {
0085                         compatible = "snps,archs-pct";
0086                         #interrupt-cells = <1>;
0087                         interrupts = <20>;
0088                 };
0089         };
0090 };