0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
0004 */
0005
0006 /*
0007 * Device Tree for ARC HS Development Kit
0008 */
0009 /dts-v1/;
0010
0011 #include <dt-bindings/gpio/gpio.h>
0012 #include <dt-bindings/reset/snps,hsdk-reset.h>
0013
0014 / {
0015 model = "snps,hsdk";
0016 compatible = "snps,hsdk";
0017
0018 #address-cells = <2>;
0019 #size-cells = <2>;
0020
0021 chosen {
0022 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
0023 };
0024
0025 aliases {
0026 ethernet = &gmac;
0027 };
0028
0029 cpus {
0030 #address-cells = <1>;
0031 #size-cells = <0>;
0032
0033 cpu@0 {
0034 device_type = "cpu";
0035 compatible = "snps,archs38";
0036 reg = <0>;
0037 clocks = <&core_clk>;
0038 };
0039
0040 cpu@1 {
0041 device_type = "cpu";
0042 compatible = "snps,archs38";
0043 reg = <1>;
0044 clocks = <&core_clk>;
0045 };
0046
0047 cpu@2 {
0048 device_type = "cpu";
0049 compatible = "snps,archs38";
0050 reg = <2>;
0051 clocks = <&core_clk>;
0052 };
0053
0054 cpu@3 {
0055 device_type = "cpu";
0056 compatible = "snps,archs38";
0057 reg = <3>;
0058 clocks = <&core_clk>;
0059 };
0060 };
0061
0062 input_clk: input-clk {
0063 #clock-cells = <0>;
0064 compatible = "fixed-clock";
0065 clock-frequency = <33333333>;
0066 };
0067
0068 reg_5v0: regulator-5v0 {
0069 compatible = "regulator-fixed";
0070
0071 regulator-name = "5v0-supply";
0072 regulator-min-microvolt = <5000000>;
0073 regulator-max-microvolt = <5000000>;
0074 };
0075
0076 cpu_intc: cpu-interrupt-controller {
0077 compatible = "snps,archs-intc";
0078 interrupt-controller;
0079 #interrupt-cells = <1>;
0080 };
0081
0082 idu_intc: idu-interrupt-controller {
0083 compatible = "snps,archs-idu-intc";
0084 interrupt-controller;
0085 #interrupt-cells = <1>;
0086 interrupt-parent = <&cpu_intc>;
0087 };
0088
0089 arcpct: pct {
0090 compatible = "snps,archs-pct";
0091 interrupt-parent = <&cpu_intc>;
0092 interrupts = <20>;
0093 };
0094
0095 /* TIMER0 with interrupt for clockevent */
0096 timer {
0097 compatible = "snps,arc-timer";
0098 interrupts = <16>;
0099 interrupt-parent = <&cpu_intc>;
0100 clocks = <&core_clk>;
0101 };
0102
0103 /* 64-bit Global Free Running Counter */
0104 gfrc {
0105 compatible = "snps,archs-timer-gfrc";
0106 clocks = <&core_clk>;
0107 };
0108
0109 soc {
0110 compatible = "simple-bus";
0111 #address-cells = <1>;
0112 #size-cells = <1>;
0113 interrupt-parent = <&idu_intc>;
0114
0115 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
0116
0117 cgu_rst: reset-controller@8a0 {
0118 compatible = "snps,hsdk-reset";
0119 #reset-cells = <1>;
0120 reg = <0x8a0 0x4>, <0xff0 0x4>;
0121 };
0122
0123 core_clk: core-clk@0 {
0124 compatible = "snps,hsdk-core-pll-clock";
0125 reg = <0x00 0x10>, <0x14b8 0x4>;
0126 #clock-cells = <0>;
0127 clocks = <&input_clk>;
0128
0129 /*
0130 * Set initial core pll output frequency to 1GHz.
0131 * It will be applied at the core pll driver probing
0132 * on early boot.
0133 */
0134 assigned-clocks = <&core_clk>;
0135 assigned-clock-rates = <1000000000>;
0136 };
0137
0138 serial: serial@5000 {
0139 compatible = "snps,dw-apb-uart";
0140 reg = <0x5000 0x100>;
0141 clock-frequency = <33330000>;
0142 interrupts = <6>;
0143 baud = <115200>;
0144 reg-shift = <2>;
0145 reg-io-width = <4>;
0146 };
0147
0148 gmacclk: gmacclk {
0149 compatible = "fixed-clock";
0150 clock-frequency = <400000000>;
0151 #clock-cells = <0>;
0152 };
0153
0154 mmcclk_ciu: mmcclk-ciu {
0155 compatible = "fixed-clock";
0156 /*
0157 * DW sdio controller has external ciu clock divider
0158 * controlled via register in SDIO IP. Due to its
0159 * unexpected default value (it should divide by 1
0160 * but it divides by 8) SDIO IP uses wrong clock and
0161 * works unstable (see STAR 9001204800)
0162 * We switched to the minimum possible value of the
0163 * divisor (div-by-2) in HSDK platform code.
0164 * So add temporary fix and change clock frequency
0165 * to 50000000 Hz until we fix dw sdio driver itself.
0166 */
0167 clock-frequency = <50000000>;
0168 #clock-cells = <0>;
0169 };
0170
0171 mmcclk_biu: mmcclk-biu {
0172 compatible = "fixed-clock";
0173 clock-frequency = <400000000>;
0174 #clock-cells = <0>;
0175 };
0176
0177 gpu_core_clk: gpu-core-clk {
0178 compatible = "fixed-clock";
0179 clock-frequency = <400000000>;
0180 #clock-cells = <0>;
0181 };
0182
0183 gpu_dma_clk: gpu-dma-clk {
0184 compatible = "fixed-clock";
0185 clock-frequency = <400000000>;
0186 #clock-cells = <0>;
0187 };
0188
0189 gpu_cfg_clk: gpu-cfg-clk {
0190 compatible = "fixed-clock";
0191 clock-frequency = <200000000>;
0192 #clock-cells = <0>;
0193 };
0194
0195 dmac_core_clk: dmac-core-clk {
0196 compatible = "fixed-clock";
0197 clock-frequency = <400000000>;
0198 #clock-cells = <0>;
0199 };
0200
0201 dmac_cfg_clk: dmac-gpu-cfg-clk {
0202 compatible = "fixed-clock";
0203 clock-frequency = <200000000>;
0204 #clock-cells = <0>;
0205 };
0206
0207 gmac: ethernet@8000 {
0208 #interrupt-cells = <1>;
0209 compatible = "snps,dwmac";
0210 reg = <0x8000 0x2000>;
0211 interrupts = <10>;
0212 interrupt-names = "macirq";
0213 phy-mode = "rgmii-id";
0214 snps,pbl = <32>;
0215 snps,multicast-filter-bins = <256>;
0216 clocks = <&gmacclk>;
0217 clock-names = "stmmaceth";
0218 phy-handle = <&phy0>;
0219 resets = <&cgu_rst HSDK_ETH_RESET>;
0220 reset-names = "stmmaceth";
0221 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
0222 dma-coherent;
0223
0224 tx-fifo-depth = <4096>;
0225 rx-fifo-depth = <4096>;
0226
0227 mdio {
0228 #address-cells = <1>;
0229 #size-cells = <0>;
0230 compatible = "snps,dwmac-mdio";
0231 phy0: ethernet-phy@0 { /* Micrel KSZ9031 */
0232 reg = <0>;
0233 };
0234 };
0235 };
0236
0237 ohci@60000 {
0238 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
0239 reg = <0x60000 0x100>;
0240 interrupts = <15>;
0241 resets = <&cgu_rst HSDK_USB_RESET>;
0242 dma-coherent;
0243 };
0244
0245 ehci@40000 {
0246 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
0247 reg = <0x40000 0x100>;
0248 interrupts = <15>;
0249 resets = <&cgu_rst HSDK_USB_RESET>;
0250 dma-coherent;
0251 };
0252
0253 mmc@a000 {
0254 compatible = "altr,socfpga-dw-mshc";
0255 reg = <0xa000 0x400>;
0256 num-slots = <1>;
0257 fifo-depth = <16>;
0258 card-detect-delay = <200>;
0259 clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
0260 clock-names = "biu", "ciu";
0261 interrupts = <12>;
0262 bus-width = <4>;
0263 dma-coherent;
0264 };
0265
0266 spi0: spi@20000 {
0267 compatible = "snps,dw-apb-ssi";
0268 reg = <0x20000 0x100>;
0269 #address-cells = <1>;
0270 #size-cells = <0>;
0271 interrupts = <16>;
0272 num-cs = <2>;
0273 reg-io-width = <4>;
0274 clocks = <&input_clk>;
0275 cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>,
0276 <&creg_gpio 1 GPIO_ACTIVE_LOW>;
0277
0278 flash@0 {
0279 compatible = "sst26wf016b", "jedec,spi-nor";
0280 reg = <0>;
0281 #address-cells = <1>;
0282 #size-cells = <1>;
0283 spi-max-frequency = <4000000>;
0284 };
0285
0286 adc@1 {
0287 compatible = "ti,adc108s102";
0288 reg = <1>;
0289 vref-supply = <®_5v0>;
0290 spi-max-frequency = <1000000>;
0291 };
0292 };
0293
0294 creg_gpio: gpio@14b0 {
0295 compatible = "snps,creg-gpio-hsdk";
0296 reg = <0x14b0 0x4>;
0297 gpio-controller;
0298 #gpio-cells = <2>;
0299 ngpios = <2>;
0300 };
0301
0302 gpio: gpio@3000 {
0303 compatible = "snps,dw-apb-gpio";
0304 reg = <0x3000 0x20>;
0305 #address-cells = <1>;
0306 #size-cells = <0>;
0307
0308 gpio_port_a: gpio-controller@0 {
0309 compatible = "snps,dw-apb-gpio-port";
0310 gpio-controller;
0311 #gpio-cells = <2>;
0312 snps,nr-gpios = <24>;
0313 reg = <0>;
0314 };
0315 };
0316
0317 gpu_3d: gpu@90000 {
0318 compatible = "vivante,gc";
0319 reg = <0x90000 0x4000>;
0320 clocks = <&gpu_dma_clk>,
0321 <&gpu_cfg_clk>,
0322 <&gpu_core_clk>,
0323 <&gpu_core_clk>;
0324 clock-names = "bus", "reg", "core", "shader";
0325 interrupts = <28>;
0326 };
0327
0328 dmac: dmac@80000 {
0329 compatible = "snps,axi-dma-1.01a";
0330 reg = <0x80000 0x400>;
0331 interrupts = <27>;
0332 clocks = <&dmac_core_clk>, <&dmac_cfg_clk>;
0333 clock-names = "core-clk", "cfgr-clk";
0334
0335 dma-channels = <4>;
0336 snps,dma-masters = <2>;
0337 snps,data-width = <3>;
0338 snps,block-size = <4096 4096 4096 4096>;
0339 snps,priority = <0 1 2 3>;
0340 snps,axi-max-burst-len = <16>;
0341 };
0342 };
0343
0344 memory@80000000 {
0345 #address-cells = <2>;
0346 #size-cells = <2>;
0347 device_type = "memory";
0348 reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */
0349 /* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */
0350 };
0351 };
