0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
0004 */
0005 /dts-v1/;
0006
0007 /include/ "skeleton_hs_idu.dtsi"
0008
0009 / {
0010 model = "snps,zebu_hs-smp";
0011 compatible = "snps,zebu_hs";
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 interrupt-parent = <&core_intc>;
0015
0016 memory {
0017 device_type = "memory";
0018 reg = <0x80000000 0x20000000>; /* 512 */
0019 };
0020
0021 chosen {
0022 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
0023 };
0024
0025 aliases {
0026 serial0 = &uart0;
0027 };
0028
0029 fpga {
0030 compatible = "simple-bus";
0031 #address-cells = <1>;
0032 #size-cells = <1>;
0033
0034 /* child and parent address space 1:1 mapped */
0035 ranges;
0036
0037 core_clk: core_clk {
0038 #clock-cells = <0>;
0039 compatible = "fixed-clock";
0040 clock-frequency = <50000000>; /* 50 MHZ */
0041 };
0042
0043 core_intc: interrupt-controller {
0044 compatible = "snps,archs-intc";
0045 interrupt-controller;
0046 #interrupt-cells = <1>;
0047 };
0048
0049 idu_intc: idu-interrupt-controller {
0050 compatible = "snps,archs-idu-intc";
0051 interrupt-controller;
0052 interrupt-parent = <&core_intc>;
0053 #interrupt-cells = <1>;
0054 };
0055
0056 uart0: serial@f0000000 {
0057 compatible = "ns16550a";
0058 reg = <0xf0000000 0x2000>;
0059 interrupt-parent = <&idu_intc>;
0060 interrupts = <0>;
0061 clock-frequency = <50000000>;
0062 baud = <115200>;
0063 reg-shift = <2>;
0064 reg-io-width = <4>;
0065 no-loopback-test = <1>;
0066 };
0067
0068 arcpct0: pct {
0069 compatible = "snps,archs-pct";
0070 #interrupt-cells = <1>;
0071 interrupts = <20>;
0072 };
0073 };
0074 };
