0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Support for peripherals on the AXS10x mainboard
0004 *
0005 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
0006 */
0007
0008 / {
0009 aliases {
0010 ethernet = &gmac;
0011 };
0012
0013 axs10x_mb {
0014 compatible = "simple-bus";
0015 #address-cells = <1>;
0016 #size-cells = <1>;
0017 ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
0018 interrupt-parent = <&mb_intc>;
0019
0020 creg_rst: reset-controller@11220 {
0021 compatible = "snps,axs10x-reset";
0022 #reset-cells = <1>;
0023 reg = <0x11220 0x4>;
0024 };
0025
0026 i2sclk: i2sclk@100a0 {
0027 compatible = "snps,axs10x-i2s-pll-clock";
0028 reg = <0x100a0 0x10>;
0029 clocks = <&i2spll_clk>;
0030 #clock-cells = <0>;
0031 };
0032
0033 clocks {
0034 i2spll_clk: i2spll_clk {
0035 compatible = "fixed-clock";
0036 clock-frequency = <27000000>;
0037 #clock-cells = <0>;
0038 };
0039
0040 i2cclk: i2cclk {
0041 compatible = "fixed-clock";
0042 clock-frequency = <50000000>;
0043 #clock-cells = <0>;
0044 };
0045
0046 apbclk: apbclk {
0047 compatible = "fixed-clock";
0048 clock-frequency = <50000000>;
0049 #clock-cells = <0>;
0050 };
0051
0052 mmcclk: mmcclk {
0053 compatible = "fixed-clock";
0054 /*
0055 * DW sdio controller has external ciu clock divider
0056 * controlled via register in SDIO IP. It divides
0057 * sdio_ref_clk (which comes from CGU) by 16 for
0058 * default. So default mmcclk clock (which comes
0059 * to sdk_in) is 25000000 Hz.
0060 */
0061 clock-frequency = <25000000>;
0062 #clock-cells = <0>;
0063 };
0064 };
0065
0066 pguclk: pguclk@10080 {
0067 compatible = "snps,axs10x-pgu-pll-clock";
0068 reg = <0x10080 0x10>, <0x110 0x10>;
0069 #clock-cells = <0>;
0070 clocks = <&input_clk>;
0071 };
0072
0073 gmac: ethernet@18000 {
0074 #interrupt-cells = <1>;
0075 compatible = "snps,dwmac";
0076 reg = < 0x18000 0x2000 >;
0077 interrupts = < 4 >;
0078 interrupt-names = "macirq";
0079 phy-mode = "rgmii";
0080 snps,pbl = < 32 >;
0081 snps,multicast-filter-bins = <256>;
0082 clocks = <&apbclk>;
0083 clock-names = "stmmaceth";
0084 max-speed = <100>;
0085 resets = <&creg_rst 5>;
0086 reset-names = "stmmaceth";
0087 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
0088 };
0089
0090 ehci@40000 {
0091 compatible = "generic-ehci";
0092 reg = < 0x40000 0x100 >;
0093 interrupts = < 8 >;
0094 };
0095
0096 ohci@60000 {
0097 compatible = "generic-ohci";
0098 reg = < 0x60000 0x100 >;
0099 interrupts = < 8 >;
0100 };
0101
0102 /*
0103 * According to DW Mobile Storage databook it is required
0104 * to use "Hold Register" if card is enumerated in SDR12 or
0105 * SDR25 modes.
0106 *
0107 * Utilization of "Hold Register" is already implemented via
0108 * dw_mci_pltfm_prepare_command() which in its turn gets
0109 * used through dw_mci_drv_data->prepare_command call-back.
0110 * This call-back is used in Altera Socfpga platform and so
0111 * we may reuse it saying that we're compatible with their
0112 * "altr,socfpga-dw-mshc".
0113 *
0114 * Most probably "Hold Register" utilization is platform-
0115 * independent requirement which means that single unified
0116 * "snps,dw-mshc" should be enough for all users of DW MMC once
0117 * dw_mci_pltfm_prepare_command() is used in generic platform
0118 * code.
0119 */
0120 mmc@15000 {
0121 compatible = "altr,socfpga-dw-mshc";
0122 reg = < 0x15000 0x400 >;
0123 fifo-depth = < 16 >;
0124 card-detect-delay = < 200 >;
0125 clocks = <&apbclk>, <&mmcclk>;
0126 clock-names = "biu", "ciu";
0127 interrupts = < 7 >;
0128 bus-width = < 4 >;
0129 };
0130
0131 uart@20000 {
0132 compatible = "snps,dw-apb-uart";
0133 reg = <0x20000 0x100>;
0134 clock-frequency = <33333333>;
0135 interrupts = <17>;
0136 baud = <115200>;
0137 reg-shift = <2>;
0138 reg-io-width = <4>;
0139 };
0140
0141 uart@21000 {
0142 compatible = "snps,dw-apb-uart";
0143 reg = <0x21000 0x100>;
0144 clock-frequency = <33333333>;
0145 interrupts = <18>;
0146 baud = <115200>;
0147 reg-shift = <2>;
0148 reg-io-width = <4>;
0149 };
0150
0151 /* UART muxed with USB data port (ttyS3) */
0152 uart@22000 {
0153 compatible = "snps,dw-apb-uart";
0154 reg = <0x22000 0x100>;
0155 clock-frequency = <33333333>;
0156 interrupts = <19>;
0157 baud = <115200>;
0158 reg-shift = <2>;
0159 reg-io-width = <4>;
0160 };
0161
0162 i2c@1d000 {
0163 compatible = "snps,designware-i2c";
0164 reg = <0x1d000 0x100>;
0165 clock-frequency = <400000>;
0166 clocks = <&i2cclk>;
0167 interrupts = <14>;
0168 };
0169
0170 i2s: i2s@1e000 {
0171 compatible = "snps,designware-i2s";
0172 reg = <0x1e000 0x100>;
0173 clocks = <&i2sclk 0>;
0174 clock-names = "i2sclk";
0175 interrupts = <15>;
0176 #sound-dai-cells = <0>;
0177 };
0178
0179 i2c@1f000 {
0180 compatible = "snps,designware-i2c";
0181 #address-cells = <1>;
0182 #size-cells = <0>;
0183 reg = <0x1f000 0x100>;
0184 clock-frequency = <400000>;
0185 clocks = <&i2cclk>;
0186 interrupts = <16>;
0187
0188 adv7511:adv7511@39{
0189 compatible="adi,adv7511";
0190 reg = <0x39>;
0191 interrupts = <23>;
0192 adi,input-depth = <8>;
0193 adi,input-colorspace = "rgb";
0194 adi,input-clock = "1x";
0195 adi,clock-delay = <0x03>;
0196 #sound-dai-cells = <0>;
0197
0198 ports {
0199 #address-cells = <1>;
0200 #size-cells = <0>;
0201
0202 /* RGB/YUV input */
0203 port@0 {
0204 reg = <0>;
0205 adv7511_input:endpoint {
0206 remote-endpoint = <&pgu_output>;
0207 };
0208 };
0209
0210 /* HDMI output */
0211 port@1 {
0212 reg = <1>;
0213 adv7511_output: endpoint {
0214 remote-endpoint = <&hdmi_connector_in>;
0215 };
0216 };
0217 };
0218 };
0219
0220 eeprom@54{
0221 compatible = "atmel,24c01";
0222 reg = <0x54>;
0223 pagesize = <0x8>;
0224 };
0225
0226 eeprom@57{
0227 compatible = "atmel,24c04";
0228 reg = <0x57>;
0229 pagesize = <0x8>;
0230 };
0231 };
0232
0233 hdmi0: connector {
0234 compatible = "hdmi-connector";
0235 type = "a";
0236 port {
0237 hdmi_connector_in: endpoint {
0238 remote-endpoint = <&adv7511_output>;
0239 };
0240 };
0241 };
0242
0243 gpio0:gpio@13000 {
0244 compatible = "snps,dw-apb-gpio";
0245 reg = <0x13000 0x1000>;
0246 #address-cells = <1>;
0247 #size-cells = <0>;
0248
0249 gpio0_banka: gpio-controller@0 {
0250 compatible = "snps,dw-apb-gpio-port";
0251 gpio-controller;
0252 #gpio-cells = <2>;
0253 snps,nr-gpios = <32>;
0254 reg = <0>;
0255 };
0256
0257 gpio0_bankb: gpio-controller@1 {
0258 compatible = "snps,dw-apb-gpio-port";
0259 gpio-controller;
0260 #gpio-cells = <2>;
0261 snps,nr-gpios = <8>;
0262 reg = <1>;
0263 };
0264
0265 gpio0_bankc: gpio-controller@2 {
0266 compatible = "snps,dw-apb-gpio-port";
0267 gpio-controller;
0268 #gpio-cells = <2>;
0269 snps,nr-gpios = <8>;
0270 reg = <2>;
0271 };
0272 };
0273
0274 gpio1:gpio@14000 {
0275 compatible = "snps,dw-apb-gpio";
0276 reg = <0x14000 0x1000>;
0277 #address-cells = <1>;
0278 #size-cells = <0>;
0279
0280 gpio1_banka: gpio-controller@0 {
0281 compatible = "snps,dw-apb-gpio-port";
0282 gpio-controller;
0283 #gpio-cells = <2>;
0284 snps,nr-gpios = <30>;
0285 reg = <0>;
0286 };
0287
0288 gpio1_bankb: gpio-controller@1 {
0289 compatible = "snps,dw-apb-gpio-port";
0290 gpio-controller;
0291 #gpio-cells = <2>;
0292 snps,nr-gpios = <10>;
0293 reg = <1>;
0294 };
0295
0296 gpio1_bankc: gpio-controller@2 {
0297 compatible = "snps,dw-apb-gpio-port";
0298 gpio-controller;
0299 #gpio-cells = <2>;
0300 snps,nr-gpios = <8>;
0301 reg = <2>;
0302 };
0303 };
0304
0305 pgu@17000 {
0306 compatible = "snps,arcpgu";
0307 reg = <0x17000 0x400>;
0308 clocks = <&pguclk>;
0309 clock-names = "pxlclk";
0310 memory-region = <&frame_buffer>;
0311 port {
0312 pgu_output: endpoint {
0313 remote-endpoint = <&adv7511_input>;
0314 };
0315 };
0316 };
0317
0318 sound_playback {
0319 compatible = "simple-audio-card";
0320 simple-audio-card,name = "AXS10x HDMI Audio";
0321 simple-audio-card,format = "i2s";
0322 simple-audio-card,cpu {
0323 sound-dai = <&i2s>;
0324 };
0325 simple-audio-card,codec {
0326 sound-dai = <&adv7511>;
0327 };
0328 };
0329 };
0330 };
