0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
0004 */
0005
0006 /*
0007 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
0008 */
0009
0010 /include/ "skeleton_hs_idu.dtsi"
0011
0012 / {
0013 compatible = "snps,arc";
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016
0017 cpu_card {
0018 compatible = "simple-bus";
0019 #address-cells = <1>;
0020 #size-cells = <1>;
0021
0022 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
0023
0024 input_clk: input-clk {
0025 #clock-cells = <0>;
0026 compatible = "fixed-clock";
0027 clock-frequency = <33333333>;
0028 };
0029
0030 core_clk: core-clk@80 {
0031 compatible = "snps,axs10x-arc-pll-clock";
0032 reg = <0x80 0x10>, <0x100 0x10>;
0033 #clock-cells = <0>;
0034 clocks = <&input_clk>;
0035
0036 /*
0037 * Set initial core pll output frequency to 100MHz.
0038 * It will be applied at the core pll driver probing
0039 * on early boot.
0040 */
0041 assigned-clocks = <&core_clk>;
0042 assigned-clock-rates = <100000000>;
0043 };
0044
0045 core_intc: archs-intc@cpu {
0046 compatible = "snps,archs-intc";
0047 interrupt-controller;
0048 #interrupt-cells = <1>;
0049 };
0050
0051 idu_intc: idu-interrupt-controller {
0052 compatible = "snps,archs-idu-intc";
0053 interrupt-controller;
0054 interrupt-parent = <&core_intc>;
0055 #interrupt-cells = <1>;
0056 };
0057
0058 /*
0059 * this GPIO block ORs all interrupts on CPU card (creg,..)
0060 * to uplink only 1 IRQ to ARC core intc
0061 */
0062 dw-apb-gpio@2000 {
0063 compatible = "snps,dw-apb-gpio";
0064 reg = < 0x2000 0x80 >;
0065 #address-cells = <1>;
0066 #size-cells = <0>;
0067
0068 ictl_intc: gpio-controller@0 {
0069 compatible = "snps,dw-apb-gpio-port";
0070 gpio-controller;
0071 #gpio-cells = <2>;
0072 snps,nr-gpios = <30>;
0073 reg = <0>;
0074 interrupt-controller;
0075 #interrupt-cells = <2>;
0076 interrupt-parent = <&idu_intc>;
0077 interrupts = <1>;
0078 };
0079 };
0080
0081 debug_uart: dw-apb-uart@5000 {
0082 compatible = "snps,dw-apb-uart";
0083 reg = <0x5000 0x100>;
0084 clock-frequency = <33333000>;
0085 interrupt-parent = <&ictl_intc>;
0086 interrupts = <2 4>;
0087 baud = <115200>;
0088 reg-shift = <2>;
0089 reg-io-width = <4>;
0090 };
0091
0092 arcpct0: pct {
0093 compatible = "snps,archs-pct";
0094 #interrupt-cells = <1>;
0095 interrupt-parent = <&core_intc>;
0096 interrupts = <20>;
0097 };
0098 };
0099
0100 /*
0101 * Mark DMA peripherals connected via IOC port as dma-coherent. We do
0102 * it via overlay because peripherals defined in axs10x_mb.dtsi are
0103 * used for both AXS101 and AXS103 boards and only AXS103 has IOC (so
0104 * only AXS103 board has HW-coherent DMA peripherals)
0105 * We don't need to mark pgu@17000 as dma-coherent because it uses
0106 * external DMA buffer located outside of IOC aperture.
0107 */
0108 axs10x_mb {
0109 ethernet@18000 {
0110 dma-coherent;
0111 };
0112
0113 ehci@40000 {
0114 dma-coherent;
0115 };
0116
0117 ohci@60000 {
0118 dma-coherent;
0119 };
0120
0121 mmc@15000 {
0122 dma-coherent;
0123 };
0124 };
0125
0126 /*
0127 * This INTC is actually connected to DW APB GPIO
0128 * which acts as a wire between MB INTC and CPU INTC.
0129 * GPIO INTC is configured in platform init code
0130 * and here we mimic direct connection from MB INTC to
0131 * CPU INTC, thus we set "interrupts = <0 1>" instead of
0132 * "interrupts = <12>"
0133 *
0134 * This intc actually resides on MB, but we move it here to
0135 * avoid duplicating the MB dtsi file given that IRQ from
0136 * this intc to cpu intc are different for axs101 and axs103
0137 */
0138 mb_intc: interrupt-controller@e0012000 {
0139 #interrupt-cells = <1>;
0140 compatible = "snps,dw-apb-ictl";
0141 reg = < 0x0 0xe0012000 0x0 0x200 >;
0142 interrupt-controller;
0143 interrupt-parent = <&idu_intc>;
0144 interrupts = <0>;
0145 };
0146
0147 memory {
0148 device_type = "memory";
0149 /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
0150 reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */
0151 0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */
0152 };
0153
0154 reserved-memory {
0155 #address-cells = <2>;
0156 #size-cells = <2>;
0157 ranges;
0158 /*
0159 * Move frame buffer out of IOC aperture (0x8z-0xaz).
0160 */
0161 frame_buffer: frame_buffer@be000000 {
0162 compatible = "shared-dma-pool";
0163 reg = <0x0 0xbe000000 0x0 0x2000000>;
0164 no-map;
0165 };
0166 };
0167 };
