0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
0004 */
0005
0006 /*
0007 * Device tree for AXC003 CPU card: HS38x UP configuration
0008 */
0009
0010 /include/ "skeleton_hs.dtsi"
0011
0012 / {
0013 compatible = "snps,arc";
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016
0017 cpu_card {
0018 compatible = "simple-bus";
0019 #address-cells = <1>;
0020 #size-cells = <1>;
0021
0022 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
0023
0024 input_clk: input-clk {
0025 #clock-cells = <0>;
0026 compatible = "fixed-clock";
0027 clock-frequency = <33333333>;
0028 };
0029
0030 core_clk: core-clk@80 {
0031 compatible = "snps,axs10x-arc-pll-clock";
0032 reg = <0x80 0x10>, <0x100 0x10>;
0033 #clock-cells = <0>;
0034 clocks = <&input_clk>;
0035
0036 /*
0037 * Set initial core pll output frequency to 90MHz.
0038 * It will be applied at the core pll driver probing
0039 * on early boot.
0040 */
0041 assigned-clocks = <&core_clk>;
0042 assigned-clock-rates = <90000000>;
0043 };
0044
0045 core_intc: archs-intc@cpu {
0046 compatible = "snps,archs-intc";
0047 interrupt-controller;
0048 #interrupt-cells = <1>;
0049 };
0050
0051 /*
0052 * this GPIO block ORs all interrupts on CPU card (creg,..)
0053 * to uplink only 1 IRQ to ARC core intc
0054 */
0055 dw-apb-gpio@2000 {
0056 compatible = "snps,dw-apb-gpio";
0057 reg = < 0x2000 0x80 >;
0058 #address-cells = <1>;
0059 #size-cells = <0>;
0060
0061 ictl_intc: gpio-controller@0 {
0062 compatible = "snps,dw-apb-gpio-port";
0063 gpio-controller;
0064 #gpio-cells = <2>;
0065 snps,nr-gpios = <30>;
0066 reg = <0>;
0067 interrupt-controller;
0068 #interrupt-cells = <2>;
0069 interrupt-parent = <&core_intc>;
0070 interrupts = <25>;
0071 };
0072 };
0073
0074 debug_uart: dw-apb-uart@5000 {
0075 compatible = "snps,dw-apb-uart";
0076 reg = <0x5000 0x100>;
0077 clock-frequency = <33333000>;
0078 interrupt-parent = <&ictl_intc>;
0079 interrupts = <2 4>;
0080 baud = <115200>;
0081 reg-shift = <2>;
0082 reg-io-width = <4>;
0083 };
0084
0085 arcpct0: pct {
0086 compatible = "snps,archs-pct";
0087 #interrupt-cells = <1>;
0088 interrupt-parent = <&core_intc>;
0089 interrupts = <20>;
0090 };
0091 };
0092
0093 /*
0094 * Mark DMA peripherals connected via IOC port as dma-coherent. We do
0095 * it via overlay because peripherals defined in axs10x_mb.dtsi are
0096 * used for both AXS101 and AXS103 boards and only AXS103 has IOC (so
0097 * only AXS103 board has HW-coherent DMA peripherals)
0098 * We don't need to mark pgu@17000 as dma-coherent because it uses
0099 * external DMA buffer located outside of IOC aperture.
0100 */
0101 axs10x_mb {
0102 ethernet@18000 {
0103 dma-coherent;
0104 };
0105
0106 ehci@40000 {
0107 dma-coherent;
0108 };
0109
0110 ohci@60000 {
0111 dma-coherent;
0112 };
0113
0114 mmc@15000 {
0115 dma-coherent;
0116 };
0117 };
0118
0119 /*
0120 * The DW APB ICTL intc on MB is connected to CPU intc via a
0121 * DT "invisible" DW APB GPIO block, configured to simply pass thru
0122 * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)
0123 *
0124 * So here we mimic a direct connection betwen them, ignoring the
0125 * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
0126 * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
0127 *
0128 * This intc actually resides on MB, but we move it here to
0129 * avoid duplicating the MB dtsi file given that IRQ from
0130 * this intc to cpu intc are different for axs101 and axs103
0131 */
0132 mb_intc: interrupt-controller@e0012000 {
0133 #interrupt-cells = <1>;
0134 compatible = "snps,dw-apb-ictl";
0135 reg = < 0x0 0xe0012000 0x0 0x200 >;
0136 interrupt-controller;
0137 interrupt-parent = <&core_intc>;
0138 interrupts = < 24 >;
0139 };
0140
0141 memory {
0142 device_type = "memory";
0143 /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
0144 reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */
0145 0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */
0146 };
0147
0148 reserved-memory {
0149 #address-cells = <2>;
0150 #size-cells = <2>;
0151 ranges;
0152 /*
0153 * Move frame buffer out of IOC aperture (0x8z-0xaz).
0154 */
0155 frame_buffer: frame_buffer@be000000 {
0156 compatible = "shared-dma-pool";
0157 reg = <0x0 0xbe000000 0x0 0x2000000>;
0158 no-map;
0159 };
0160 };
0161 };
